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1. 发明授权

US06493268B1 Circuit device for performing hierarchic row decoding in non-volatile memory devices 有权
标题翻译：用于在非易失性存储器件中执行分级行解码的电路装置
公开(公告)号：US06493268B1
公开(公告)日：2002-12-10
申请号：US09905163
申请日：2001-07-12
申请人： Osama Khouri , Andrea Pierin , Rino Micheloni , Stefano Gregori , Guido Torelli , Miriam Sangalli
发明人： Osama Khouri , Andrea Pierin , Rino Micheloni , Stefano Gregori , Guido Torelli , Miriam Sangalli
IPC分类号： G11C1600
CPC分类号： G11C16/08
摘要： A circuit device for performing hierarchic row decoding in semiconductor memory devices of the non-volatile type, which memory devices include an array of memory cells with column-ordered sectors, wherein each sector has a respective group of local wordlines linked to a main wordline. The circuit device includes a main wordline driver provided at each main wordline, and a local decoder provided at each local wordline. This circuit device further comprises, for each main wordline, a dedicated path connected between the main wordline and the local decoders of the associated local wordlines and connected to an external terminal arranged to receive a read/program voltage, the dedicated path enabling transfer of the read/program voltage to the local decoders.
摘要翻译：一种用于在非易失性类型的半导体存储器件中执行分级行解码的电路装置，该存储器件包括具有列排列扇区的存储器单元阵列，其中每个扇区具有链接到主字线的相应组的本地字线。电路装置包括在每个主字线处提供的主字线驱动器和在每个本地字线处提供的本地解码器。该电路装置还包括对于每个主字线，连接在相关联的本地字线的主字线和本地解码器之间的专用路径，并连接到布置成接收读/写电压的外部端子，该专用路径使得能够传送读/编程电压到本地解码器。

2. 发明授权

US06788579B2 Method for programming nonvolatile memory cells with program and verify algorithm using a staircase voltage with varying step amplitude 有权
标题翻译：使用程序和验证算法编程非易失性存储单元的方法，使用具有不同步长幅度的阶梯电压
公开(公告)号：US06788579B2
公开(公告)日：2004-09-07
申请号：US10119523
申请日：2002-04-09
申请人： Stefano Gregori , Rino Micheloni , Andrea Pierin , Osama Khouri , Guido Torelli
发明人： Stefano Gregori , Rino Micheloni , Andrea Pierin , Osama Khouri , Guido Torelli
IPC分类号： G11C1604
CPC分类号： G11C11/5628 , G11C16/12
摘要： A method for programming a nonvolatile memory cell envisages applying in succession, to the gate terminal of the memory cell, a first and a second programming pulse trains with pulse amplitude increasing in staircase fashion, in which the amplitude increment between one pulse and the next in the first programming pulse train is greater than the amplitude increment between one pulse and the next in the second programming pulse train. The programming method envisages applying, to the gate terminal of the memory cell and before the first programming pulse train, a third programming pulse train with pulse amplitude increasing in staircase fashion, in which the amplitude increment between one pulse and the next may be less than the amplitude increment in the first programming pulse train and substantially equal to the amplitude increment in the second programming pulse train, or else may be greater than the amplitude increment in the first programming pulse train.
摘要翻译：用于编程非易失性存储器单元的方法设想连续地应用到存储器单元的栅极端，第一和第二编程脉冲串，其阶梯形式的脉冲幅度增加，其中在一个脉冲和下一个脉冲之间的振幅增量第一编程脉冲序列大于第二编程脉冲串中的一个脉冲和下一个脉冲之间的振幅增量。编程方法设想在存储器单元的栅极端子和第一编程脉冲串之前施加具有阶梯式脉冲幅度增加的第三编程脉冲串，其中，一个脉冲与下一个脉冲之间的振幅增量可能小于第一编程脉冲序列中的振幅增量基本上等于第二编程脉冲串中的幅度增量，或者可以大于第一编程脉冲序列中的振幅增量。

3. 发明授权

US06542404B2 Small size, low consumption, multilevel nonvolatile memory 有权
标题翻译：小尺寸，低功耗，多级非易失性存储器
公开(公告)号：US06542404B2
公开(公告)日：2003-04-01
申请号：US09972726
申请日：2001-10-04
申请人： Andrea Pierin , Stefano Gregori , Rino Micheloni , Osama Khouri , Guido Torelli
发明人： Andrea Pierin , Stefano Gregori , Rino Micheloni , Osama Khouri , Guido Torelli
IPC分类号： G11C1604
CPC分类号： G11C16/30 , G11C5/145 , G11C7/06 , G11C11/5621 , G11C11/5642 , G11C16/26
摘要： A multilevel nonvolatile memory includes a supply line (28) supplying a supply voltage (VDD), a voltage boosting circuit (26) supplying a boosted voltage (Vp), higher than the supply voltage (VDD), a boosted line (30) connected to the voltage boosting circuit (26) and a reading circuit (25) including at least one comparator (35). The comparator (35) includes a first and a second input (35a, 35b), a first and a second output (45a, 45b), at least one amplification stage (40) connected to the boosted line (30), and a boosted line latch stage (41) connected to the supply line (28).
摘要翻译：多级非易失性存储器包括提供电源电压（VDD）的电源线（28），提供高于电源电压（VDD）的升压电压（Vp）的升压电路（26），连接的升压线路到升压电路（26）和包括至少一个比较器（35）的读取电路（25）。比较器（35）包括第一和第二输入（35a，35b），第一和第二输出（45a，45b），连接到升压线（30）的至少一个放大级（40）线路锁存级（41）连接到电源线（28）。

4. 发明授权

US06674385B2 Analog-to-digital conversion method and device, in high-density multilevel non-volatile memory devices 有权
标题翻译：模数转换方法和器件，在高密度多级非易失性存储器件中
公开(公告)号：US06674385B2
公开(公告)日：2004-01-06
申请号：US10060076
申请日：2002-01-29
申请人： Rino Micheloni , Osama Khouri , Andrea Pierin , Stefano Gregori , Guido Torelli
发明人： Rino Micheloni , Osama Khouri , Andrea Pierin , Stefano Gregori , Guido Torelli
IPC分类号： H03M112
CPC分类号： G11C11/56 , G11C27/005 , H03M1/146 , H03M1/361
摘要： An analog-to-digital conversion method and device for a multilevel non-volatile memory device that includes a multilevel memory cell. The method comprises a first step of converting the most significant bits contained in the memory cell, followed by a second step of converting the least significant bits. The first step is completed within a time interval corresponding to the rise transient of the gate voltage, and the second step is initiated at the end of the transient. Also disclosed is a scheme for error control coding in multilevel Flash memories. The n bits stored in a single memory cell are organized in different “bit-layers”, which are independent from one another. Error correction is carried out separately for each bit-layer. The correction of any failure in a single memory cell is achieved by using a simple error control code providing single-bit correction, regardless of the number of bits stored in a single cell.
摘要翻译：一种用于包括多电平存储器单元的多级非易失性存储器件的模数转换方法和装置。该方法包括转换存储单元中包含的最高有效位的第一步骤，随后转换最低有效位的第二步骤。在对应于栅极电压的上升瞬变的时间间隔内完成第一步，并且在瞬态结束时启动第二步。还公开了一种用于多电平闪存中的错误控制编码的方案。存储在单个存储器单元中的n位被组织在彼此独立的不同“位层”中。针对每个位层分别执行错误校正。通过使用提供单位校正的简单误差控制代码来实现单个存储器单元中的任何故障的校正，而不管存储在单个单元中的位数。

5. 发明授权

US06404273B1 Voltage booster with a low output resistance 有权
标题翻译：电压增压器具有低输出电阻
公开(公告)号：US06404273B1
公开(公告)日：2002-06-11
申请号：US09785083
申请日：2001-02-13
申请人： Stefano Gregori , Osama Khouri , Andrea Pierin , Rino Micheloni , Guido Torelli , Dario Soltesz
发明人： Stefano Gregori , Osama Khouri , Andrea Pierin , Rino Micheloni , Guido Torelli , Dario Soltesz
IPC分类号： G05F110
CPC分类号： H02M3/073 , H02M2003/075
摘要： A charge pump voltage booster circuit for generating, from a first voltage supplied at the input to the circuit, an output voltage with an absolute value that is higher than the first voltage, comprises at least one stage having a charge pass element and a charge storage capacitor with a first plate connected to an output of the charge pass element and a second plate controlled by a square-wave control signal of period varying between a reference voltage and the first voltage, supplied to the second plate of the capacitor by means of a driver circuit comprising a pull-up transistor and a pull-down transistor connected in series between the first voltage and the reference voltage. Means of overdriving at least one of the said transistors, either the pull-up transistor or the pull-down transistor, supply to the said at least one transistor a firing control voltage that has a higher absolute value than the first voltage.
摘要翻译：一种电荷泵升压电路，用于根据从所述电路的输入端提供的第一电压产生具有高于所述第一电压的绝对值的输出电压，所述电压泵电压升压电路包括至少一个具有充电通路元件和电荷存储器电容器，其具有连接到所述电荷通过元件的输出端的第一板，以及第二板，其由在基准电压和所述第一电压之间变化的周期的方波控制信号控制，所述方波控制信号通过驱动器电路包括串联在第一电压和参考电压之间的上拉晶体管和下拉晶体管。过载驱动所述晶体管中的至少一个（上拉晶体管或下拉晶体管）的装置向所述至少一个晶体管提供具有比第一电压更高的绝对值的点火控制电压。

6. 发明授权

US06249112B1 Voltage regulating circuit for a capacitive load 有权
标题翻译：用于容性负载的电压调节电路
公开(公告)号：US06249112B1
公开(公告)日：2001-06-19
申请号：US09608445
申请日：2000-06-29
申请人： Osama Khouri , Rino Micheloni , Ilaria Motta , Guido Torelli
发明人： Osama Khouri , Rino Micheloni , Ilaria Motta , Guido Torelli
IPC分类号： G05F140
CPC分类号： G05F3/242
摘要： Presented is a voltage regulating circuit for a capacitive load, which is connected between first and second terminals of a supply voltage generator. The regulating circuit has an input terminal and an output terminal, and includes an operational amplifier having an inverting input terminal connected to the input terminal of the regulating circuit and a non-inverting input terminal connected to an intermediate node of a voltage divider. The voltage divider is connected between an output node, which is connected to the output terminal of the regulating circuit, and the second terminal of the supply voltage generator. The operational amplifier has an output terminal connected, for driving a first field-effect transistor, between the output node and the first terminal of the supply voltage generator. The output terminal of the operational amplifier is also connected to the output node through a compensation network. The voltage regulating circuit also includes a second field-effect transistor connected between the output node and the second terminal of the supply voltage generator, which has its gate terminal connected to a constant voltage generating circuit means.
摘要翻译：提出了一种用于容性负载的电压调节电路，其连接在电源电压发生器的第一和第二端子之间。调节电路具有输入端子和输出端子，并且包括具有连接到调节电路的输入端子的反相输入端子和连接到分压器的中间节点的非反相输入端子的运算放大器。分压器连接在与调节电路的输出端子连接的输出节点和电源电压发生器的第二端子之间。运算放大器在输出节点和电源电压发生器的第一端之间连接有用于驱动第一场效应晶体管的输出端子。运算放大器的输出端也通过补偿网络连接到输出节点。电压调节电路还包括连接在电源电压发生器的输出节点和第二端子之间的第二场效应晶体管，其栅极端子连接到恒压产生电路装置。

7. 发明授权

US06650173B1 Programmable voltage generator 有权
标题翻译：可编程电压发生器
公开(公告)号：US06650173B1
公开(公告)日：2003-11-18
申请号：US09714852
申请日：2000-11-15
申请人： Osama Khouri , Rino Micheloni , Andrea Sacco , Guido Torelli
发明人： Osama Khouri , Rino Micheloni , Andrea Sacco , Guido Torelli
IPC分类号： G05F110
CPC分类号： G11C29/021 , G11C5/147 , G11C11/56 , G11C16/30 , G11C29/028 , G11C2029/5004
摘要： The voltage generator comprises a negative feedback loop including a programmable voltage divider having a feedback node. The voltage divider comprises a programmable resistor disposed between the output of the voltage generator and the feedback node and having variable resistance. The programmable resistor includes a fixed resistor and a plurality of additional resistors arranged in series with each other and defining a plurality of intermediate nodes. The additional resistors may be selectively connected by means of switches disposed between the output of the voltage generator and a respective intermediate node so as to define an output voltage V0 programmable on the basis of command signals supplied to the switches.
摘要翻译：电压发生器包括负反馈回路，其包括具有反馈节点的可编程分压器。分压器包括设置在电压发生器的输出端和反馈节点之间并具有可变电阻的可编程电阻器。可编程电阻器包括固定电阻器和彼此串联布置并且限定多个中间节点的多个附加电阻器。附加电阻器可以通过设置在电压发生器的输出端和各个中间节点之间的开关选择性地连接，以便根据提供给开关的命令信号来定义可编程的输出电压V0。

8. 发明授权

US06259632B1 Capacitive compensation circuit for the regulation of the word line reading voltage in non-volatile memories 有权
标题翻译：用于调节非易失性存储器中字线读取电压的电容补偿电路
公开(公告)号：US06259632B1
公开(公告)日：2001-07-10
申请号：US09491475
申请日：2000-01-19
申请人： Osama Khouri , Rino Micheloni , Ilaria Motta , Andrea Sacco , Guido Torelli
发明人： Osama Khouri , Rino Micheloni , Ilaria Motta , Andrea Sacco , Guido Torelli
IPC分类号： G11C1606
CPC分类号： G11C11/5621 , G11C8/14 , G11C16/08 , G11C16/30
摘要： Circuit for the regulation of the word line voltage in a memory, including a voltage regulator suitable to generate an output regulated voltage to be supplied to one or more word lines of the memory when said one or more word lines are being selected, and charge accumulation means that are selectively connectable with the output of the voltage regulator and suitable to accumulate a compensation charge for a voltage drop that takes place on said regulated voltage upon the selection of said one or more word lines of the memory.
摘要翻译：用于调节存储器中的字线电压的电路，包括适于在选择所述一个或多个字线时产生要提供给存储器的一个或多个字线的输出调节电压的电压调节器，以及电荷累积意味着可以选择性地与电压调节器的输出端连接，并且适合于在选择存储器的所述一个或多个字线时，对在所述调节电压上发生的电压降累积补偿电荷。

9. 发明授权

US06559627B2 Voltage regulator for low-consumption circuits 有权
公开(公告)号：US06559627B2
公开(公告)日：2003-05-06
申请号：US10008540
申请日：2001-11-07
申请人： Osama Khouri , Ilaria Motta , Rino Micheloni , Guido Torelli
发明人： Osama Khouri , Ilaria Motta , Rino Micheloni , Guido Torelli
IPC分类号： G05F156
CPC分类号： G05F1/56
摘要： A voltage regulator having a comparator with an output terminal that is the output of the regulator, terminals for connection to a voltage supply, a source of a reference voltage connected to an input terminal of the comparator, and a feedback circuit connected between the output terminal and the other input terminal of the comparator. To prevent transients upon the transition from the standby state to the active state, there is provided a second reference-voltage source that provides a reference voltage substantially equal to that of the first source, a switch for connecting the second source to the other input terminal of the comparator, and a control circuit that can activate the supply of the regulator and can close the switch for a predetermined period of time when the supply of the regulator is activated.

10. 发明授权

US06504758B2 Control circuit for a variable-voltage regulator of a nonvolatile memory with hierarchical row decoding 有权
公开(公告)号：US06504758B2
公开(公告)日：2003-01-07
申请号：US09960851
申请日：2001-09-21
申请人： Andrea Sacco , Osama Khouri , Rino Micheloni , Guido Torelli
发明人： Andrea Sacco , Osama Khouri , Rino Micheloni , Guido Torelli
IPC分类号： G11C1604
CPC分类号： G11C16/08 , G11C5/147 , G11C8/08 , G11C8/10 , G11C8/14
摘要： Described herein is a nonvolatile memory comprising a memory array organized according to global word lines and local word lines; a global row decoder; a local row decoder; a first supply stage for supplying the global row decoder; and a second supply stage for supplying the local row decoder; and a third supply stage for biasing the drain and source terminals of the memory cells of the memory array. Each of the supply stages comprises a respective resistive divider formed by a plurality of series-connected resistors, and a plurality of pass-gate CMOS switches each connected in parallel to a respective resistor. The nonvolatile memory further comprises a control circuit for controlling the pass-gate CMOS switches of the supply stages, and a switching circuit for selectively connecting the supply input of the control circuit to the output of the second supply stage during reading and programming of the memory, and to the output of the third supply stage during erasing of the memory.

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