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1. 发明授权

US08553462B2 Method of programming a multi-level memory device 有权
标题翻译：编程多级存储器件的方法
公开(公告)号：US08553462B2
公开(公告)日：2013-10-08
申请号：US12551383
申请日：2009-08-31
申请人： Luca Crippa , Rino Micheloni
发明人： Luca Crippa , Rino Micheloni
IPC分类号： G11C16/06 , G11C16/10 , G11C16/34 , G11C16/04 , G11C16/26
CPC分类号： G11C16/10 , G11C11/5628
摘要： Methods and apparatus for programming a memory include programming cells to a first threshold voltage, verifying programming using a first verify voltage, and applying a test read voltage to verify again that the cells are programmed to the first threshold voltage. The test read voltage is lower than the first verify voltage.
摘要翻译：用于编程存储器的方法和装置包括将单元编程为第一阈值电压，使用第一验证电压验证编程，以及施加测试读取电压以再次验证单元被编程为第一阈值电压。测试读取电压低于第一个验证电压。

2. 发明授权

US07863967B2 Multistage regulator for charge-pump boosted voltage applications 有权
标题翻译：用于电荷泵升压电压应用的多级调节器
公开(公告)号：US07863967B2
公开(公告)日：2011-01-04
申请号：US11460370
申请日：2006-07-27
申请人： Luca Crippa , Miriam Sangalli , Giancarlo Ragone , Rino Micheloni
发明人： Luca Crippa , Miriam Sangalli , Giancarlo Ragone , Rino Micheloni
IPC分类号： G05F1/46 , G11C16/30
CPC分类号： G11C5/145 , G11C16/30
摘要： A multistage circuit for regulating the charge voltage or the discharge current of a capacitance of an integrated device at a certain charge-pump generated boosted voltage is implemented without integrating high voltage transistor structures having a type of conductivity corresponding to the same sign of the boosted voltage (high-side transistors). The multistage circuit current includes at least a first stage, and an output stage in cascade to the first stage and coupled to the capacitance. The first stage is supplied at an unboosted power supply voltage of the integrated device, and the output stage is supplied at an unregulated charge-pump generated boosted voltage. The first stage includes a transistor having a type of conductivity corresponding to an opposite sign of the boosted voltage and of the power supply voltage. The drain of the output stage transistor is coupled to the boosted voltage either through a resistive pull-up or a voltage limiter.
摘要翻译：在一定的电荷泵产生的升压电压下，用于调节集成器件的电容的充电电压或放电电流的多级电路不需要集成具有对应于升压电压相同符号的电导率类型的高压晶体管结构，（高侧晶体管）。多级电路电流包括至少第一级和级联到第一级并耦合到电容的输出级。第一级是在集成器件的未升压的电源电压下提供的，并且输出级以未调节的电荷泵产生的升压电压供电。第一级包括具有对应于升压电压和电源电压的相反符号的导电类型的晶体管。输出级晶体管的漏极通过电阻上拉或电压限制器耦合到升压电压。

3. 发明申请

US20090316482A1 METHOD OF PROGRAMMING A MULTI-LEVEL MEMORY DEVICE 有权
标题翻译：编程多级存储器件的方法
公开(公告)号：US20090316482A1
公开(公告)日：2009-12-24
申请号：US12551383
申请日：2009-08-31
申请人： Luca Crippa , Rino Micheloni
发明人： Luca Crippa , Rino Micheloni
IPC分类号： G11C16/04 , G11C7/10
CPC分类号： G11C16/10 , G11C11/5628
摘要： Embodiments of the present disclosure provide methods and apparatuses related to programming multilevel memory cells of a memory device. Other embodiments may be described and claimed.
摘要翻译：本公开的实施例提供了与存储器件的多级存储器单元的编程有关的方法和装置。可以描述和要求保护其他实施例。

4. 发明授权

US07529136B2 Method for compacting the erased threshold voltage distribution of flash memory devices during writing operations 有权
标题翻译：在写入操作期间压缩闪存器件的擦除阈值电压分布的方法
公开(公告)号：US07529136B2
公开(公告)日：2009-05-05
申请号：US11844480
申请日：2007-08-24
申请人： Rino Micheloni , Luca Crippa , Roberto Ravasio , Federico Pio
发明人： Rino Micheloni , Luca Crippa , Roberto Ravasio , Federico Pio
IPC分类号： G11C16/04
CPC分类号： G11C16/344
摘要： A method for operating a flash memory device. The memory device includes a matrix of memory cells each one having a programmable threshold voltage defining a value stored in the memory cell. The method includes the steps of erasing a block of memory cells, and compacting the threshold voltages of the memory cells of the block within a predefined compacting range, wherein the step of compacting includes: selecting at least one first memory cell of the block for writing a target value; restoring the threshold voltage of a subset of the memory cells of the block to the compacting range, the subset including the at least one first memory cell and/or at least one second memory cell of the block being adjacent to the at least one first memory cell; and at least partially writing the target value into the at least one first memory cell.
摘要翻译：一种用于操作闪存设备的方法。存储器件包括存储器单元矩阵，每个存储器单元具有限定存储在存储器单元中的值的可编程阈值电压。该方法包括以下步骤：擦除存储器单元块，以及在预定的压缩范围内压缩块的存储单元的阈值电压，其中压缩步骤包括：选择块写入的至少一个第一存储单元目标值将块的存储器单元的子集的阈值电压恢复到压缩范围，该子集包括与至少一个第一存储器相邻的块的至少一个第一存储器单元和/或至少一个第二存储器单元细胞; 并且至少部分地将目标值写入至少一个第一存储单元。

5. 发明授权

US07521983B2 High-voltage switch with low output ripple for non-volatile floating-gate memories 有权
标题翻译：非挥发性浮栅存储器具有低输出纹波的高压开关
公开(公告)号：US07521983B2
公开(公告)日：2009-04-21
申请号：US11437405
申请日：2006-05-19
申请人： Giancarlo Ragone , Luca Crippa , Miriam Sangalli , Rino Micheloni
发明人： Giancarlo Ragone , Luca Crippa , Miriam Sangalli , Rino Micheloni
IPC分类号： H03K17/687
CPC分类号： H02M3/073 , G11C5/145 , G11C8/08 , G11C16/08 , G11C16/12 , H02M2003/077 , H03K3/356104 , H03K17/063 , H03K17/6872 , H03K17/6874
摘要： A high-voltage switch has a high-voltage input terminal, receiving a high voltage, and an output terminal. A pass transistor, having a control terminal, is connected between the high-voltage input terminal and the output terminal. The output of a voltage-multiplying circuit of the charge-pump type is connected to the control terminal. The voltage-multiplying circuit is of a symmetrical type, has first and second charge-storage means, receiving a clock signal of a periodic type, and has a first circuit branch and a second circuit branch, which are symmetrical to one another and operate in phase opposition with respect to the clock signal.
摘要翻译：高压开关具有高电压输入端子，接收高电压和输出端子。具有控制端子的传输晶体管连接在高电压输入端子和输出端子之间。电荷泵型的倍压电路的输出端与控制端子连接。电压倍增电路是对称型的，具有第一和第二电荷存储装置，接收周期型的时钟信号，并且具有第一电路支路和第二电路支路，它们彼此对称并在相对于时钟信号的相位相反。

6. 发明授权

US07499345B2 Non-volatile memory implemented with low-voltages transistors and related system and method 有权
标题翻译：采用低压晶体管实现的非易失性存储器及相关系统及方法
公开(公告)号：US07499345B2
公开(公告)日：2009-03-03
申请号：US11605209
申请日：2006-11-27
申请人： Giovanni Campardo , Rino Micheloni , Luca Crippa , Giancarlo Ragone , Miram Sangalli
发明人： Giovanni Campardo , Rino Micheloni , Luca Crippa , Giancarlo Ragone , Miram Sangalli
IPC分类号： G11C5/14 , G11C16/04 , G05F3/24
CPC分类号： H02M3/07
摘要： An embodiment of an electronic apparatus is provided. The electronic apparatus includes a supplying block for supplying a plurality of operative voltages, one or more operative circuits and a distribution bus for distributing at least part of the operative voltages to each operative circuit. Each operative circuit includes a set of devices for generating a set of output voltages from a set of input ones of the distributed operative voltages. The input and output voltages span an effective range. Each device is capable of sustaining at most a safe voltage between each pair of terminals thereof not higher than the effective range. The devices are controlled by a set of auxiliary ones of the distributed operative voltages spanning an auxiliary range within the effective range, so that a difference between the voltage applied to each pair of terminals thereof is not higher than the safe voltage.
摘要翻译：提供电子设备的实施例。电子设备包括用于提供多个操作电压的供应块，一个或多个操作电路和分配总线，用于将至少部分工作电压分配给每个操作电路。每个操作电路包括一组用于从一组分布式操作电压的输入端产生一组输出电压的装置。输入和输出电压跨越有效范围。每个装置能够在每对终端之间至多维持不高于有效范围的安全电压。这些器件由跨越有效范围内的辅助范围的一组分布式工作电压控制，使得施加到其每对端子的电压之间的差不高于安全电压。

7. 发明授权

US07408819B2 Semiconductor memory device with a page buffer having an improved layout arrangement 有权
标题翻译：具有页面缓冲器的半导体存储器件具有改进的布局布置
公开(公告)号：US07408819B2
公开(公告)日：2008-08-05
申请号：US11459831
申请日：2006-07-25
申请人： Luca Crippa , Rino Micheloni
发明人： Luca Crippa , Rino Micheloni
IPC分类号： G11C7/10
CPC分类号： G11C11/5628 , G11C5/025 , G11C11/5642 , G11C2211/5642
摘要： A memory device is provided. The memory device includes a matrix of memory cells adapted to store data and arranged in a plurality of bit lines, the bit lines extending along a first direction; a page buffer adapted to interface the matrix with a downstream circuitry, the page buffer comprising a plurality of read/program units. Each read/program unit is associated with at least one bit line. The memory device further includes at least two groups each including at least two respective read/program units, wherein the read/program units of a generic one of said groups are generically aligned along the first direction. Each group comprises at least one signal track shared by the at least two read/program units of the group.
摘要翻译：提供存储器件。存储器件包括适于存储数据并且布置在多个位线中的存储单元矩阵，位线沿第一方向延伸; 页面缓冲器，其适于使矩阵与下游电路接口，所述页面缓冲器包括多个读取/编程单元。每个读取/编程单元与至少一个位线相关联。存储器装置还包括至少两组，每组包括至少两个相应的读/写单元，其中所述组中的通用一个的读/写单元沿第一方向一般对准。每个组包括由组的至少两个读/写单元共享的至少一个信号轨道。

8. 发明授权

US07366014B2 Double page programming system and method 有权
标题翻译：双页编程系统和方法
公开(公告)号：US07366014B2
公开(公告)日：2008-04-29
申请号：US11495876
申请日：2006-07-28
申请人： Rino Micheloni , Luca Crippa , Roberto Ravasio
发明人： Rino Micheloni , Luca Crippa , Roberto Ravasio
IPC分类号： G11C16/04
CPC分类号： G11C16/12 , G11C11/5628 , G11C16/0483 , G11C2211/5621 , G11C2211/5642 , G11C2216/14
摘要： A method for programming an electrically programmable memory including a plurality of memory cells arranged in individually-selectable memory cell sets each including at least one memory cell. The programming method includes causing the memory cells of a selected memory cells set to be brought into a predetermined, starting programming state. Receiving a target value for the first data bits groups of the memory cells of the selected memory cells set. Receiving a target value for the second data bits groups of the memory cells of the selected memory cells set. After having received the target values of both the first and the second data bits groups, applying to the memory cells of the selected memory cells set a programming sequence adapted to cause the memory cells of the selected memory cells sets to be brought into a target programming state jointly determined by the target values of the first and second data bits groups.
摘要翻译：一种用于编程电可编程存储器的方法，包括布置在各自包括至少一个存储单元的可单独选择的存储单元组中的多个存储单元。编程方法包括使所设置的选定存储单元的存储单元进入预定的开始编程状态。接收所选存储器单元的存储单元的第一数据位组的目标值。接收所选存储器单元的存储单元的第二数据位组的目标值。在接收到第一和第二数据位组两者的目标值之后，将所选择的存储器单元的存储单元应用到所设置的编程顺序，以使所选择的存储单元组的存储器单元进入目标编程状态由第一和第二数据位组的目标值联合确定。

9. 发明授权

US07336538B2 Page buffer circuit and method for multi-level NAND programmable memories 有权
标题翻译：页面缓冲电路和多级NAND可编程存储器的方法
公开(公告)号：US07336538B2
公开(公告)日：2008-02-26
申请号：US11495874
申请日：2006-07-28
申请人： Luca Crippa , Chiara Missiroli , Roberto Ravasio , Rino Micheloni , Angelo Bovino
发明人： Luca Crippa , Chiara Missiroli , Roberto Ravasio , Rino Micheloni , Angelo Bovino
IPC分类号： G11C16/04
CPC分类号： G11C16/12 , G11C11/5628 , G11C16/0483 , G11C2211/5621 , G11C2211/5642 , G11C2216/14
摘要： A page buffer for an electrically programmable memory including at least one read/program unit having a coupling line operatively associable with at least one of said bit lines and adapted to at least temporarily storing data bits read from or to be written into either one of the first or second memory page stored in the memory cells of a selected memory cell sets. The read/program unit includes enabling means for selectively enabling a change in programming state of a selected memory cell by causing the coupling line to take one among a program enabling potential and a program inhibition potential, conditioned to a target data value to be stored in the first group of data bits of the selected memory cell and an existing data value already stored in the second group of data bits of the selected memory cell. The enabling means includes reading means for retrieving the existing data value, means for receiving an indication of the target data value, combining means for combining the received target data value with the retrieved existing data value, thereby modifying said indication of the target data value so as to obtain a modified indication. Conditioning means in the combining means condition a potential of the coupling line based on the existing data value and the modified indication so as to cause the coupling line to take the program enabling potential or the program inhibition potential.
摘要翻译：一种用于电可编程存储器的页面缓冲器，包括至少一个读/程序单元，其具有可操作地与至少一个所述位线相关联的耦合线，并且适于至少临时存储从或写入到存储在所选存储单元组的存储单元中的第一或第二存储器页。读/程序单元包括启用装置，用于通过使耦合线在程序使能电位和程序禁止电位之间采取一种方式来有选择地启用所选择的存储单元的编程状态的改变，所选存储单元的第一组数据位和已存储在所选存储单元的第二组数据位中的现有数据值。启用装置包括用于检索现有数据值的读取装置，用于接收目标数据值的指示的装置，用于将接收的目标数据值与所检索的现有数据值组合的组合装置，从而修改目标数据值的所述指示，从而以获得修改的指示。组合装置中的调节装置基于现有数据值和修改的指示来条件耦合线的电位，以使耦合线采取程序使能电位或程序禁止电位。

10. 发明授权

US07221212B2 Trimming functional parameters in integrated circuits 有权
标题翻译：在集成电路中修剪功能参数
公开(公告)号：US07221212B2
公开(公告)日：2007-05-22
申请号：US11113818
申请日：2005-04-25
申请人： Luca Crippa , Miriam Sangalli , Salvatrice Scommegna , Rino Micheloni
发明人： Luca Crippa , Miriam Sangalli , Salvatrice Scommegna , Rino Micheloni
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： G11C5/147 , G11C29/02 , G11C29/021 , G11C29/028
摘要： A trimming structure for trimming functional parameters of an Integrated Circuit—IC—(100) includes a first (115a) and at least one second functional blocks (115b, . . . ,115n) with which a first (Vrg,a) and at least one second IC functional parameters (Vrg,b, . . . ,Vrg,n) are respectively associated. The trimming structure includes respective trimmable circuit structures (205a,210a, . . . ,205n,210n) included in the first and at least one second functional blocks, and trimming configuration storage (110) for storing trimming configurations for the trimmable circuit structures. A change in the trimming configuration of the first functional block causes a corresponding change in the trimming configuration of the second functional block. Further, a change in the second IC functional parameter in response to the corresponding change in the trimming configuration of the second functional block is proportional to the change in the first IC functional parameter consequent to the change in the trimming configuration of the first functional block.
摘要翻译：用于修整集成电路IC-（100）的功能参数的修整结构包括第一（115a）和至少一个第二功能块（115b，...，115n），第一（Vr1，...，115n））和至少一个第二IC功能参数（Vrg，b，...，Vrg，n）分别相关联。修剪结构包括包括在第一和至少一个第二功能块中的相应可调节电路结构（205a，210a，...，205n，210n），以及修剪配置存储（110），用于存储用于可调节电路结构。第一功能块的修整配置的变化导致第二功能块的修整配置的相应变化。此外，响应于第二功能块的修整配置的相应变化，第二IC功能参数的变化与第一功能块的修整配置的改变所引起的第一IC功能参数的变化成比例。

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