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1. 发明授权

US08621318B1 Nonvolatile memory controller with error detection for concatenated error correction codes 有权
标题翻译：具有错误检测功能的非易失性存储器控制器，用于级联纠错码
公开(公告)号：US08621318B1
公开(公告)日：2013-12-31
申请号：US13435572
申请日：2012-03-30
申请人： Rino Micheloni , Alessia Marelli , Peter Z. Onufryk , Christopher I. W. Norrie
发明人： Rino Micheloni , Alessia Marelli , Peter Z. Onufryk , Christopher I. W. Norrie
IPC分类号： H03M13/00
CPC分类号： H03M13/3707 , G06F11/1012 , G06F11/108 , G06F2211/109 , H03M13/1102 , H03M13/1108 , H03M13/1111 , H03M13/152 , H03M13/2906
摘要： A nonvolatile memory controller to recover encoded data by performing a hard-decision inner error correction code decoding and an outer error correction code decoding of the data decoded using the hard-decision inner error correction code decoding and then determining if the encoded data has been successfully decoded. If the encoded data has not been successfully decoded, the controller performs a soft-decision inner error correction code decoding of the encoded data using a soft-decision algorithm and an outer error correction code decoding of the data decoded using the soft-decision inner error correction code decoding and then determining if the encoded data has been successfully decoded. If the encoded data has not been successfully decoded, the controller recovers the data by performing a RAID operation on the encoded data.
摘要翻译：一种非易失性存储器控制器，用于通过执行硬判决内纠错码解码和使用硬判决内纠错码解码解码的数据的外纠错码解码来恢复编码数据，然后确定编码数据是否已成功解码。如果编码数据尚未成功解码，则控制器使用软判决算法和使用软判决内部误差解码的数据的外部纠错码解码来对编码数据执行软判决内部纠错码解码校正码解码，然后确定编码数据是否已被成功解码。如果编码数据尚未成功解码，则控制器通过对编码数据执行RAID操作来恢复数据。

2. 发明授权

US07777466B2 Voltage regulator or non-volatile memories implemented with low-voltage transistors 有权
标题翻译：用低压晶体管实现的稳压器或非易失性存储器
公开(公告)号：US07777466B2
公开(公告)日：2010-08-17
申请号：US11844470
申请日：2007-08-24
申请人： Luca Crippa , Giancarlo Ragone , Miriam Sangalli , Giovanni Campardo , Rino Micheloni
发明人： Luca Crippa , Giancarlo Ragone , Miriam Sangalli , Giovanni Campardo , Rino Micheloni
IPC分类号： G05F1/40
CPC分类号： G11C5/147 , G05F1/565 , G11C16/30
摘要： A voltage regulator integrated in a chip of semiconductor material is provided. The regulator has a first input terminal for receiving a first voltage and an output terminal for providing a regulated voltage being obtained from the first voltage, the regulator including: a differential amplifier for receiving a comparison voltage and a feedback signal being a function of the regulated voltage, and for proving a regulation signal according to a comparison between the comparison voltage and the feedback signal, the differential amplifier having a first supply terminal being coupled with a reference terminal for receiving a reference voltage and a second supply terminal, a regulation transistor having a control terminal for receiving the regulation signal, and a conduction first terminal and a conduction second terminal being coupled through loading means between the reference terminal and the first input terminal of the regulator, the second terminal of the regulation transistor being coupled with the output terminal of the regulator, wherein the second supply terminal of the differential amplifier is coupled with a second input terminal of the regulator for receiving a second voltage being lower than the first voltage in absolute value, and wherein the regulator further includes a set of auxiliary transistors being connected in series between the second terminal of the regulation transistor and the output terminal of the regulator, and control means for controlling the auxiliary transistors according to the regulated voltage.
摘要翻译：提供集成在半导体材料芯片中的电压调节器。所述调节器具有用于接收第一电压的第一输入端子和用于提供从所述第一电压获得的调节电压的输出端子，所述调节器包括：用于接收比较电压的差分放大器和作为所述第一电压的函数的反馈信号电压，并且为了根据比较电压和反馈信号之间的比较来证明调节信号，差分放大器具有与用于接收参考电压的参考端子耦合的第一电源端子和第二电源端子，调节晶体管具有用于接收所述调节信号的控制端子，以及通过所述参考端子和所述调节器的所述第一输入端子之间的负载装置耦合的导通第一端子和导通第二端子，所述调节晶体管的所述第二端子与所述输出端子的调节器，其中第二电源差分放大器的nal与调节器的第二输入端耦合，用于接收低于绝对值中的第一电压的第二电压，并且其中调节器还包括一组辅助晶体管，串联连接在第二端调节器的调节晶体管和输出端子，以及用于根据调节电压控制辅助晶体管的控制装置。

3. 发明授权

US07730357B2 Integrated memory system 有权
标题翻译：集成内存系统
公开(公告)号：US07730357B2
公开(公告)日：2010-06-01
申请号：US10805182
申请日：2004-03-19
申请人： Rino Micheloni , Roberto Ravasio
发明人： Rino Micheloni , Roberto Ravasio
IPC分类号： G06F11/00
CPC分类号： G06F11/1068 , G06F11/1048
摘要： An embodiment of the present invention relates to an integrated memory system comprising at least a non-volatile memory and an automatic storage error corrector, and wherein the memory is connected to a controller by means of an interface bus. Advantageously, the system comprises in the memory circuit means, functionally independent, each being responsible for the correction of a predetermined storage error; at least one of said means generating a signal to ask a correction being external to the memory.
摘要翻译：本发明的实施例涉及至少包括非易失性存储器和自动存储错误校正器的集成存储器系统，并且其中存储器通过接口总线连接到控制器。有利地，该系统在存储器电路装置中包括功能上独立的，每个都负责校正预定的存储错误; 所述装置中的至少一个产生要求校正在存储器外部的信号。

4. 发明授权

US07719894B2 Method of programming cells of a NAND memory device 有权
标题翻译：对NAND存储器件的单元进行编程的方法
公开(公告)号：US07719894B2
公开(公告)日：2010-05-18
申请号：US11828716
申请日：2007-07-26
申请人： Luca Crippa , Roberto Ravasio , Rino Micheloni
发明人： Luca Crippa , Roberto Ravasio , Rino Micheloni
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C7/18 , G11C11/5628 , G11C16/0483 , G11C16/24 , G11C16/3427
摘要： The capacitive coupling between two adjacent bitlines of a NAND memory device may be exploited for boosting the voltage of bitlines that are not to be programmed in order to inhibit program operations on them. The even (odd) bitlines that include cells not to be programmed are biased with a first voltage for inhibiting them from being programmed while the even (odd) bitlines that include cells to be programmed are grounded. The adjacent odd (even) bitlines are biased at the supply voltage or at an auxiliary voltage for boosting the bias voltage of the even (odd) bitlines above the supply voltage. The bias voltage of the even (odd) bitlines that include cells not to be programmed is boosted because of the relevant parasitic coupling capacitances between adjacent bitlines.
摘要翻译：可以利用NAND存储器件的两个相邻位线之间的电容耦合来升高不被编程的位线的电压，以便禁止对它们的编程操作。包括不被编程的单元的偶数（奇数）位线用第一电压偏置，以阻止它们被编程，而包括要编程的单元的偶数（奇数）位线接地。相邻的奇数（偶数）位线在电源电压或辅助电压处偏置，用于将偶数（奇数）位线的偏置电压升高到电源电压以上。由于相邻位线之间的相关寄生耦合电容，包括不编程单元的偶数（奇数）位线的偏置电压会升高。

5. 发明授权

US07630238B2 Page buffer for multi-level NAND electrically-programmable semiconductor memories 有权
标题翻译：多级NAND电可编程半导体存储器的页缓冲器
公开(公告)号：US07630238B2
公开(公告)日：2009-12-08
申请号：US11821131
申请日：2007-06-21
申请人： Luca Crippa , Rino Micheloni
发明人： Luca Crippa , Rino Micheloni
IPC分类号： G11C11/34
CPC分类号： G11C7/1021 , G11C7/1039 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/3459 , G11C2211/5621
摘要： A page buffer for an electrically programmable memory is provided. The page buffer includes a plurality of memory cells, a plurality of distinct programming states defined for each memory cell, corresponding to a number N>=2 of data bits storable in each memory cell, wherein the data bits include at least a first data bits group and a second data bits group and at least one read/program unit having a coupling line operatively associable with selected memory cells.
摘要翻译：提供了用于电可编程存储器的页面缓冲器。页面缓冲器包括多个存储器单元，对于每个存储器单元定义的多个不同的编程状态，对应于可存储在每个存储器单元中的数据位数N> = 2，其中数据位至少包括第一数据位组和第二数据位组以及至少一个具有与所选存储单元可操作地相关联的耦合线的读/写单元。

6. 发明授权

US07444543B2 Data control unit capable of correcting boot errors, and corresponding self-correction method 有权
标题翻译：能够修正启动错误的数据控制单元及相应的自校正方法
公开(公告)号：US07444543B2
公开(公告)日：2008-10-28
申请号：US11149948
申请日：2005-06-09
申请人： Irene Babudri , Marco Roveda , Rino Micheloni
发明人： Irene Babudri , Marco Roveda , Rino Micheloni
IPC分类号： G06F11/00
CPC分类号： G06F11/1417 , G06F11/076
摘要： A boot method for a data control unit downloads boot information from a nonvolatile memory into a temporary buffer of a boot-activation unit. A processing unit is activated by the boot-activation unit; a boot code is executed by the processing unit; and an operating code is downloaded from the nonvolatile memory into a volatile memory through the boot-activation unit. To correct possible errors in the block of the nonvolatile memory containing information and boot codes, the boot-activation unit verifies whether the boot information downloaded into its volatile memory has a critical-error condition and activates a spare memory portion of the nonvolatile memory in presence of the critical-error condition.
摘要翻译：用于数据控制单元的引导方法将引导信息从非易失性存储器下载到引导启动单元的临时缓冲器中。处理单元由启动激活单元激活; 由处理单元执行引导代码; 并且通过引导启动单元将操作代码从非易失性存储器下载到易失性存储器中。为了纠正包含信息和引导代码的非易失性存储器的块中的可能错误，引导激活单元验证下载到其易失性存储器中的引导信息是否具有关键错误状况，并在存在时激活非易失性存储器的备用存储器部分的关键错误条件。

7. 发明申请

US20080062767A1 METHOD OF FIXING A READ EVALUATION TIME OR THE DIFFERENCE BETWEEN A READ CHARGE VOLTAGE AND A READ DISCRIMINATING VOLTAGE IN A NON-VOLATILE NAND TYPE MEMORY DEVICE 审中-公开
标题翻译：固定读取评估时间的方法或读取电荷电压与非易失性NAND型存储器件中的读取分辨电压之间的差异
公开(公告)号：US20080062767A1
公开(公告)日：2008-03-13
申请号：US11854713
申请日：2007-09-13
申请人： Luca CRIPPA , Roberto RAVASIO , Rino MICHELONI
发明人： Luca CRIPPA , Roberto RAVASIO , Rino MICHELONI
IPC分类号： G11C16/04
CPC分类号： G11C29/02 , G11C16/04 , G11C29/023 , G11C29/025 , G11C29/028 , G11C29/50012 , G11C2029/1204
摘要： The evaluation time or the difference between the read charge voltage and the read discrimination voltage of the programmed or erased state of a cell of a NAND memory array is set for the individual memory device. This is done in such a way that at least partially compensates the generally large spread of parasitic capacitance values of the array bitlines in the mass production fabrication process of the NAND memory array.
摘要翻译：针对各个存储器件设置评估时间或NAND存储器阵列的单元的编程或擦除状态的读取充电电压和读取判别电压之间的差。这样做的方式是至少部分地补偿NAND存储器阵列的批量生产制造过程中阵列位线的寄生电容值的普遍大的扩展。

8. 发明申请

US20070047316A1 READING METHOD OF A NAND-TYPE MEMORY DEVICE AND NAND-TYPE MEMORY DEVICE 有权
标题翻译： NAND型存储器件和NAND型存储器件的读取方法
公开(公告)号：US20070047316A1
公开(公告)日：2007-03-01
申请号：US11458916
申请日：2006-07-20
申请人： Luca Crippa , Chiara Missiroli , Rino Micheloni
发明人： Luca Crippa , Chiara Missiroli , Rino Micheloni
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C16/26
摘要： A reading method of a NAND memory device includes the steps of first connecting a first end terminal of a stack of cells to a reference line, second connecting a second end terminal of the stack of cells to a respective bitline, and charging the bitline to a predetermined bitline read voltage, where one of the steps of first connecting and second connecting is carried out before charging the bitline and the other of the steps of first connecting and second connecting is carried out after charging the bitline. An order of carrying out the steps of first connecting and second connecting is determined based on an address of a selected cell.
摘要翻译： NAND存储器件的读取方法包括以下步骤：首先将单元堆叠的第一端子连接到参考线，然后将单元堆叠的第二端子连接到相应的位线，以及将位线充电到预定的位线读取电压，其中在对位线充电之前执行第一连接和第二连接的步骤之一，并且在对位线充电之后执行第一连接和第二连接的另一个步骤。基于所选择的单元的地址来确定执行第一连接和第二连接的步骤的顺序。

9. 发明申请

US20060291322A1 Circuit and method for retrieving data stored in semiconductor memory cells 有权
公开(公告)号：US20060291322A1
公开(公告)日：2006-12-28
申请号：US11444892
申请日：2006-05-31
申请人： Luca Crippa , Giancarlo Ragone , Miriam Sangalli , Rino Micheloni
发明人： Luca Crippa , Giancarlo Ragone , Miriam Sangalli , Rino Micheloni
IPC分类号： G11C8/00
CPC分类号： G11C11/5642 , G11C7/04 , G11C16/30
摘要： A circuit comprises at least one memory cell adapted to store data in terms of values of an electrical characteristic thereof, which exhibits a variability with temperature according to a first variation law; a voltage generator is provided for generating a voltage to be supplied to the at least one memory cell for retrieving the data stored therein, the voltage generator including first means adapted to cause the generated voltage take a value in a set of target values including at least one target value, corresponding to an operation to be performed on the memory cell. The voltage generator comprises second means for causing the value taken by the generated voltage vary with temperature according to a prescribed second variation law exploiting a compensation circuit element having said electrical characteristic.

10. 发明授权

US07068540B2 Method and device for programming an electrically programmable non-volatile semiconductor memory 有权
标题翻译：用于编程电可编程非易失性半导体存储器的方法和装置
公开(公告)号：US07068540B2
公开(公告)日：2006-06-27
申请号：US10729829
申请日：2003-12-05
申请人： Rino Micheloni , Roberto Ravasio
发明人： Rino Micheloni , Roberto Ravasio
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/3454
摘要： A device and method for programming an electrically programmable memory applies at least one first programming pulse to a group of memory cells (MC1–MCk) of the memory, accesses the memory cells of the group to ascertain a programming state thereof, and applies at least one second programming pulse to those memory cells in the group whose programming state is not ascertained to correspond to a desired programming state. A voltage applied to a control electrode of the memory cells is varied between the at least one first programming pulse and the at least one second programming pulse according to a forecasted change in biasing conditions of the memory cells in the group between said at least one first and at least one second programming pulses. Undesired over-programming of the memory cells is thus avoided.
摘要翻译：用于编程电可编程存储器的装置和方法将至少一个第一编程脉冲施加到存储器的一组存储器单元（MC 1 -MC k），访问该组的存储器单元以确定其编程状态，并应用于至少一秒编程脉冲到组中编程状态未被确定以对应于期望的编程状态的那些存储器单元。根据在所述至少一个第一编程脉冲和所述至少一个第二编程脉冲之间的所述组中的存储器单元的偏置条件的预测变化，施加到所述存储器单元的控制电极的电压在所述至少一个第一编程脉冲和所述至少一个第二编程脉冲之间变化和至少一个第二编程脉冲。因此避免了对存储器单元的不期望的过度编程。

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