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1. 发明授权

US08659969B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08659969B2
公开(公告)日：2014-02-25
申请号：US13215217
申请日：2011-08-22
申请人： Hidehiro Fujiwara , Koji Nii , Makoto Yabuuchi , Kazutami Arimoto
发明人： Hidehiro Fujiwara , Koji Nii , Makoto Yabuuchi , Kazutami Arimoto
IPC分类号： G11C5/14
CPC分类号： G11C16/20 , G11C7/24 , G11C29/44
摘要： By using a fact that a bit error in an on-chip embedded memory occurs at a random address, means for creating a chip-unique ID and utilizing this ID are provided. A controller having received a verification request from outside instructs a variable power supply circuit to decrease a voltage supplied to a memory to be lower than that at the normal operation time. When the voltage supplied to the memory is stabilized, the controller requests a memory test to a memory BIST. By using an address where an error occurs due to a result of the memory test, the controller creates the chip-unique ID and uses the ID as a response to the verification request.
摘要翻译：通过使用片上嵌入式存储器中的位错误发生在随机地址处的事实，提供了用于创建芯片唯一ID并利用该ID的装置。已经从外部接收到验证请求的控制器指示可变电源电路将提供给存储器的电压降低到低于正常操作时间的电压。当提供给存储器的电压稳定时，控制器向存储器BIST请求存储器测试。通过使用由于存储器测试的结果而出现错误的地址，控制器创建芯片唯一ID，并使用ID作为对验证请求的响应。

2. 发明授权

US08169807B2 Content addressable memory device having match line equalizer circuit 有权
标题翻译：具有匹配线均衡器电路的内容可寻址存储器件
公开(公告)号：US08169807B2
公开(公告)日：2012-05-01
申请号：US12261598
申请日：2008-10-30
申请人： Katsumi Dosaka , Kazutami Arimoto , Yoshio Matsuda
发明人： Katsumi Dosaka , Kazutami Arimoto , Yoshio Matsuda
IPC分类号： G11C15/00
CPC分类号： G06F17/30982 , G11C15/04 , Y02D10/45
摘要： In a content addressable memory device, before search operations in two TCAM cells connected to first and second match lines, respectively, a memory controller connects the first match line to a power source and connects the second match line to a ground, and then connects the first and second match lines to each other so as that electric potentials of the first and second match lines are the same as each other.
摘要翻译：在内容可寻址存储器件中，在分别连接到第一和第二匹配线的两个TCAM单元中的搜索操作之前，存储器控制器将第一匹配线连接到电源，并将第二匹配线连接到地，然后将第一和第二匹配线彼此之间，使得第一和第二匹配线的电位彼此相同。

3. 发明申请

US20120044777A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20120044777A1
公开(公告)日：2012-02-23
申请号：US13215217
申请日：2011-08-22
申请人： Hidehiro FUJIWARA , Koji NII , Makoto Yabuuchi , Kazutami Arimoto
发明人： Hidehiro FUJIWARA , Koji NII , Makoto Yabuuchi , Kazutami Arimoto
IPC分类号： G11C7/00
CPC分类号： G11C16/20 , G11C7/24 , G11C29/44
摘要： By using a fact that a bit error in an on-chip embedded memory occurs at a random address, means for creating a chip-unique ID and utilizing this ID are provided. A controller having received a verification request from outside instructs a variable power supply circuit to decrease a voltage supplied to a memory to be lower than that at the normal operation time. When the voltage supplied to the memory is stabilized, the controller requests a memory test to a memory BIST. By using an address where an error occurs due to a result of the memory test, the controller creates the chip-unique ID and uses the ID as a response to the verification request.
摘要翻译：通过使用片上嵌入式存储器中的位错误发生在随机地址处的事实，提供了用于创建芯片唯一ID并利用该ID的装置。已经从外部接收到验证请求的控制器指示可变电源电路将提供给存储器的电压降低到低于正常操作时间的电压。当提供给存储器的电压稳定时，控制器向存储器BIST请求存储器测试。通过使用由于存储器测试的结果而出现错误的地址，控制器创建芯片唯一ID，并使用ID作为对验证请求的响应。

4. 发明授权

US08098080B2 Semiconductor programmable device 有权
标题翻译：半导体可编程器件
公开(公告)号：US08098080B2
公开(公告)日：2012-01-17
申请号：US12919356
申请日：2008-12-24
申请人： Kazutami Arimoto
发明人： Kazutami Arimoto
IPC分类号： G06F7/38 , H01L25/00
CPC分类号： H03K19/17756 , H03K19/1733
摘要： An ePLX unit includes a logic unit having an SRAM and a MUX, and a switch unit having an SRAM and a TG for establishing wiring connection in the logic unit. When a composite module is set in the first mode, an Add/Flag control unit uses the SRAMs as a data field and a flag field, respectively, to autonomously control the read address of each of the data field and the flag field in accordance with a control flag stored in the flag field. Furthermore, when the composite module is set in the second mode, the Add/Flag control unit writes configuration information into each of the SRAMs to reconfigure a logic circuit. Consequently, the granularity of the circuit configuration can be rendered variable, which allows improvement in flexibility when configuring a function.
摘要翻译： ePLX单元包括具有SRAM和MUX的逻辑单元，以及具有用于在逻辑单元中建立布线连接的SRAM和TG的开关单元。当复合模块被设置为第一模式时，加法/标志控制单元分别使用SRAM作为数据字段和标志字段，以依照下述方式自主地控制每个数据字段和标志字段的读取地址存储在标志字段中的控制标志。此外，当复合模块被设置为第二模式时，加法/标志控制单元将配置信息写入每个SRAM以重新配置逻辑电路。因此，电路配置的粒度可以变化，这允许在配置功能时提高灵活性。

5. 发明申请

US20110127609A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20110127609A1
公开(公告)日：2011-06-02
申请号：US13022864
申请日：2011-02-08
申请人： Fukashi MORISHITA , Kazutami ARIMOTO
发明人： Fukashi MORISHITA , Kazutami ARIMOTO
IPC分类号： H01L27/12
CPC分类号： G11C11/405 , G11C2211/4016 , H01L27/108 , H01L27/10802
摘要： The present invention aims at providing a semiconductor memory device that can be manufactured by a MOS process and can realize a stable operation. A storage transistor has impurity diffusion regions, a channel formation region, a charge accumulation node, a gate oxide film, and a gate electrode. The gate electrode is connected to a gate line and the impurity diffusion region is connected to a source line. The storage transistor creates a state where holes are accumulated in the charge accumulation node and a state where the holes are not accumulated in the charge accumulation node to thereby store data “1” and data “0”, respectively. An access transistor has impurity diffusion regions, a channel formation region, a gate oxide film, and a gate electrode. The impurity diffusion region is connected to a bit line.
摘要翻译：本发明的目的在于提供一种可以通过MOS工艺制造并可实现稳定操作的半导体存储器件。存储晶体管具有杂质扩散区域，沟道形成区域，电荷累积节点，栅极氧化膜和栅电极。栅电极连接到栅极线，杂质扩散区连接到源极线。存储晶体管产生在电荷累积节点中积累空穴的状态和空穴未积累在电荷累积节点中的状态，从而分别存储数据“1”和数据“0”。存取晶体管具有杂质扩散区，沟道形成区，栅极氧化膜和栅电极。杂质扩散区域连接到位线。

6. 发明授权

US07910975B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07910975B2
公开(公告)日：2011-03-22
申请号：US10593275
申请日：2005-06-03
申请人： Fukashi Morishita , Kazutami Arimoto
发明人： Fukashi Morishita , Kazutami Arimoto
IPC分类号： H01L29/788 , H01L27/01 , H01L27/12
CPC分类号： G11C11/405 , G11C2211/4016 , H01L27/108 , H01L27/10802
摘要： The present invention aims at providing a semiconductor memory device that can be manufactured by a MOS process and can realize a stable operation. A storage transistor has impurity diffusion regions, a channel formation region, a charge accumulation node, a gate oxide film, and a gate electrode. The gate electrode is connected to a gate line and the impurity diffusion region is connected to a source line. The storage transistor creates a state where holes are accumulated in the charge accumulation node and a state where the holes are not accumulated in the charge accumulation node to thereby store data “1” and data “0”, respectively. An access transistor has impurity diffusion regions, a channel formation region, a gate oxide film, and a gate electrode. The impurity diffusion region is connected to a bit line.
摘要翻译：本发明的目的在于提供一种可以通过MOS工艺制造并可实现稳定操作的半导体存储器件。存储晶体管具有杂质扩散区域，沟道形成区域，电荷累积节点，栅极氧化膜和栅电极。栅电极连接到栅极线，杂质扩散区连接到源极线。存储晶体管产生在电荷累积节点中积累空穴的状态和空穴未积累在电荷累积节点中的状态，从而分别存储数据“1”和数据“0”。存取晶体管具有杂质扩散区，沟道形成区，栅极氧化膜和栅电极。杂质扩散区域连接到位线。

7. 发明申请

US20100179976A1 SEMICONDUCTOR DEVICE PERFORMING OPERATIONAL PROCESSING 审中-公开
标题翻译：执行操作处理的半导体器件
公开(公告)号：US20100179976A1
公开(公告)日：2010-07-15
申请号：US12687756
申请日：2010-01-14
申请人： Masakatsu ISHIZAKI , Takeshi Kumaki , Masaharu Tagami , Yuta Imai , Tetsushi Koide , Hans Jürgen Mattausch , Takayuki Gyoten , Hideyuki Noda , Yoshihiro Okuno , Kazutami Arimoto
发明人： Masakatsu ISHIZAKI , Takeshi Kumaki , Masaharu Tagami , Yuta Imai , Tetsushi Koide , Hans Jürgen Mattausch , Takayuki Gyoten , Hideyuki Noda , Yoshihiro Okuno , Kazutami Arimoto
IPC分类号： G06F7/44 , G06F5/01 , G06F7/552
CPC分类号： G06F7/5235 , G06F7/5324 , G06F7/5338
摘要： A semiconductor device includes a decoder receiving first multiplier data of 3 bits indicating a multiplier to output a shift flag, an inversion flag, and an operation flag in accordance with Booth's algorithm, and a first partial product calculation unit receiving first multiplicand data of 2 bits indicating a multiplicand, a shift flag, an inversion flag, and an operation flag to select one of the higher order bit and lower order bit of the first multiplicand data based on the shift flag, invert or non-invert the selected bit based on the inversion flag, select one of the inverted or non-inverted data and data of a predetermined logic level based on the operation flag, and output the selected data as partial product data indicating the partial product of the first multiplier data and the first multiplicand data.
摘要翻译：半导体器件包括：解码器，接收根据布斯（Booth）算法的3比特的第一乘法器数据，指示乘法器输出移位标志，反转标志和操作标志，第一部分乘积计算单元接收2位的第一被乘数数据指示被乘数，移位标志，反转标志和操作标志，以基于移位标志来选择第一被乘数数据的高位位和低位位之一，基于该选择位反转或非反转所选位反转标志，基于操作标志选择反相或非反相数据和预定逻辑电平的数据之一，并将选择的数据作为指示第一乘法器数据和第一被乘数数据的部分乘积的部分乘积数据输出。

8. 发明申请

US20090070525A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20090070525A1
公开(公告)日：2009-03-12
申请号：US12268017
申请日：2008-11-10
申请人： Katsumi DOSAKA , Kazutami Arimoto , Kazunori Saito , Hideyuki Noda
发明人： Katsumi DOSAKA , Kazutami Arimoto , Kazunori Saito , Hideyuki Noda
IPC分类号： G06F12/00
CPC分类号： G11C15/04 , G11C15/00
摘要： A CAM (Content Addressable Memory) cell includes first and second data storage portions storing data, horizontal port write gates for storing data applied through a match line pair in the data storage portions in a data write through a horizontal port, and search/read gates for driving the match lines of the match line pair in accordance with the data stored in the data storage portions in a search operation and in a data read through the horizontal port. The match lines are used as horizontal bit line pair, or signal lines for accessing the horizontal port. As the first and second data storage portions are used, it becomes possible to store ternary data, and accordingly, a write mask function of inhibiting a data write at a destination of data transfer is realized. Further, as the CAM cell is used, an arithmetic/logic operation following a search process can be executed selectively, and high speed data writing/reading becomes possible.
摘要翻译： CAM（内容可寻址存储器）单元包括存储数据的第一和第二数据存储部分，水平端口写入门，用于通过水平端口在数据存储部分中存储通过匹配线对应用的数据，以及搜索/读取门用于根据搜索操作中存储在数据存储部分中的数据和通过水平端口读取的数据来驱动匹配线对的匹配线。匹配线用作水平位线对或用于访问水平端口的信号线。当使用第一和第二数据存储部分时，可以存储三进制数据，因此实现了在数据传送目的地禁止数据写入的写掩码功能。此外，当使用CAM单元时，可以选择性地执行搜索处理之后的算术/逻辑运算，并且可以进行高速数据写入/读取。

9. 发明授权

US07480168B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07480168B2
公开(公告)日：2009-01-20
申请号：US11819583
申请日：2007-06-28
申请人： Kazutami Arimoto , Hiroki Shimano
发明人： Kazutami Arimoto , Hiroki Shimano
IPC分类号： G11C11/24
CPC分类号： G11C7/18 , G11C8/14 , G11C11/4085 , G11C11/4087 , G11C11/4097 , G11C2211/4013 , H01L27/0207 , H01L27/108 , H01L27/1085 , H01L27/10873 , H01L27/10882
摘要： Conductive lines constituting word lines of memory cells and conductive lines constituting memory cell plate electrodes are formed in the same interconnecting layer in a memory device including a plurality of memory cells each including a capacitor for storing data in an electrical charge form. By forming the capacitors of the memory cells into a planar capacitor configuration, a step due to the capacitors is removed. Thus a dynamic semiconductor memory device can be formed through CMOS process, and a dynamic semiconductor memory device suitable for merging with logic is achieved. Data of 1 bit is stored by two memory cells, and data can be reliably stored even if the capacitance value of the memory cell is reduced due to the planar type capacitor.
摘要翻译：构成存储单元板的导体线的导电线和构成存储单元板电极的导线被形成在包括多个存储单元的存储器件的同一互连层中，每个存储单元均包括用于以电荷形式存储数据的电容器。通过将存储单元的电容器形成为平面电容器配置，由于电容器而导致的步骤被去除。因此，可以通过CMOS工艺形成动态半导体存储器件，并且实现适合于与逻辑并入的动态半导体存储器件。 1位的数据由两个存储单元存储，即使由于平面型电容器而使存储单元的电容值减小，也可以可靠地存储数据。

10. 发明授权

US07139208B2 Refresh-free dynamic semiconductor memory device 失效
公开(公告)号：US07139208B2
公开(公告)日：2006-11-21
申请号：US11165273
申请日：2005-06-24
申请人： Kazutami Arimoto , Hiroki Shimano , Takeshi Fujino , Takeshi Hashizume
发明人： Kazutami Arimoto , Hiroki Shimano , Takeshi Fujino , Takeshi Hashizume
IPC分类号： G11C7/20 , G11C5/14
CPC分类号： G11C29/006 , G11C7/1045 , G11C11/401 , G11C11/406 , G11C11/4087 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/50 , G11C29/50012 , G11C29/50016 , G11C29/83 , G11C2029/1204 , G11C2207/104 , G11C2211/4013 , G11C2211/5641
摘要： In a data holding mode, data storage in a one bit/one cell scheme in a normal operating mode are rearranged into data storage in a twin-cell mode in which data are stored in a one bit/two cell scheme. In the twin-cell mode, two sub word lines are simultaneously driven into a selected state, and storage data of memory cells are read out on both of bit lines in a pair, to perform a sense operation. Thus, the read-out voltage can be increased to improve the data retention characteristics for lengthening a refresh interval, resulting in a reduced power consumption in the data holding mode.

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