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1. 发明申请

US20090070525A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20090070525A1
公开(公告)日：2009-03-12
申请号：US12268017
申请日：2008-11-10
申请人： Katsumi DOSAKA , Kazutami Arimoto , Kazunori Saito , Hideyuki Noda
发明人： Katsumi DOSAKA , Kazutami Arimoto , Kazunori Saito , Hideyuki Noda
IPC分类号： G06F12/00
CPC分类号： G11C15/04 , G11C15/00
摘要： A CAM (Content Addressable Memory) cell includes first and second data storage portions storing data, horizontal port write gates for storing data applied through a match line pair in the data storage portions in a data write through a horizontal port, and search/read gates for driving the match lines of the match line pair in accordance with the data stored in the data storage portions in a search operation and in a data read through the horizontal port. The match lines are used as horizontal bit line pair, or signal lines for accessing the horizontal port. As the first and second data storage portions are used, it becomes possible to store ternary data, and accordingly, a write mask function of inhibiting a data write at a destination of data transfer is realized. Further, as the CAM cell is used, an arithmetic/logic operation following a search process can be executed selectively, and high speed data writing/reading becomes possible.
摘要翻译： CAM（内容可寻址存储器）单元包括存储数据的第一和第二数据存储部分，水平端口写入门，用于通过水平端口在数据存储部分中存储通过匹配线对应用的数据，以及搜索/读取门用于根据搜索操作中存储在数据存储部分中的数据和通过水平端口读取的数据来驱动匹配线对的匹配线。匹配线用作水平位线对或用于访问水平端口的信号线。当使用第一和第二数据存储部分时，可以存储三进制数据，因此实现了在数据传送目的地禁止数据写入的写掩码功能。此外，当使用CAM单元时，可以选择性地执行搜索处理之后的算术/逻辑运算，并且可以进行高速数据写入/读取。

2. 发明申请

US20100165691A1 CONTENT ADDRESSABLE MEMORY 有权
标题翻译：内容可寻址内存
公开(公告)号：US20100165691A1
公开(公告)日：2010-07-01
申请号：US12720561
申请日：2010-03-09
申请人： Naoya WATANABE , Isamu HAYASHI , Teruhiko AMANO , Fukashi MORISHITA , Kenji YOSHINAGA , Mihoko AKIYAMA , Shinya MIYAZAKI , Masakazu ISHIBASHI , Katsumi DOSAKA
发明人： Naoya WATANABE , Isamu HAYASHI , Teruhiko AMANO , Fukashi MORISHITA , Kenji YOSHINAGA , Mihoko AKIYAMA , Shinya MIYAZAKI , Masakazu ISHIBASHI , Katsumi DOSAKA
IPC分类号： G11C15/00 , G11C7/00 , G11C7/02
CPC分类号： G11C15/043 , G11C7/06 , G11C7/12 , G11C7/14 , G11C7/22 , G11C15/04 , G11C15/046
摘要： An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry.A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.
摘要翻译：包括存储数据位的单位单元的多个比特的条目耦合到匹配线。匹配线具有一个充电电流，该充电电流的限制电流值小于在一个条目中以一位未命中状态流动的匹配线电流，但大于在一个条目中以全位匹配状态流动的匹配线电流。匹配线的预充电电压电平被限制为电源电压的一半或更小的电压电平。可以减少内容可寻址存储器的搜索周期中的功耗，并且可以提高搜索操作速度。

3. 发明申请

US20120170344A1 CONTENT ADDRESSABLE MEMORY 有权
标题翻译：内容可寻址内存
公开(公告)号：US20120170344A1
公开(公告)日：2012-07-05
申请号：US13419217
申请日：2012-03-13
申请人： Naoya WATANABE , Isamu HAYASHI , Teruhiko AMANO , Fukashi MORISHITA , Kenji YOSHINAGA , Mihoko AKIYAMA , Shinya MIYAZAKI , Masakazu ISHIBASHI , Katsumi DOSAKA
发明人： Naoya WATANABE , Isamu HAYASHI , Teruhiko AMANO , Fukashi MORISHITA , Kenji YOSHINAGA , Mihoko AKIYAMA , Shinya MIYAZAKI , Masakazu ISHIBASHI , Katsumi DOSAKA
IPC分类号： G11C15/00
CPC分类号： G11C15/043 , G11C7/06 , G11C7/12 , G11C7/14 , G11C7/22 , G11C15/04 , G11C15/046
摘要： An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.
摘要翻译：包括存储数据位的单位单元的多个比特的条目耦合到匹配线。匹配线具有一个充电电流，该充电电流的限制电流值小于在一个条目中以一位未命中状态流动的匹配线电流，但大于在一个条目中以全位匹配状态流动的匹配线电流。匹配线的预充电电压电平被限制为电源电压的一半或更小的电压电平。可以减少内容可寻址存储器的搜索周期中的功耗，并且可以提高搜索操作速度。

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