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1. 发明授权

US08659969B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08659969B2
公开(公告)日：2014-02-25
申请号：US13215217
申请日：2011-08-22
申请人： Hidehiro Fujiwara , Koji Nii , Makoto Yabuuchi , Kazutami Arimoto
发明人： Hidehiro Fujiwara , Koji Nii , Makoto Yabuuchi , Kazutami Arimoto
IPC分类号： G11C5/14
CPC分类号： G11C16/20 , G11C7/24 , G11C29/44
摘要： By using a fact that a bit error in an on-chip embedded memory occurs at a random address, means for creating a chip-unique ID and utilizing this ID are provided. A controller having received a verification request from outside instructs a variable power supply circuit to decrease a voltage supplied to a memory to be lower than that at the normal operation time. When the voltage supplied to the memory is stabilized, the controller requests a memory test to a memory BIST. By using an address where an error occurs due to a result of the memory test, the controller creates the chip-unique ID and uses the ID as a response to the verification request.
摘要翻译：通过使用片上嵌入式存储器中的位错误发生在随机地址处的事实，提供了用于创建芯片唯一ID并利用该ID的装置。已经从外部接收到验证请求的控制器指示可变电源电路将提供给存储器的电压降低到低于正常操作时间的电压。当提供给存储器的电压稳定时，控制器向存储器BIST请求存储器测试。通过使用由于存储器测试的结果而出现错误的地址，控制器创建芯片唯一ID，并使用ID作为对验证请求的响应。

2. 发明授权

US08310883B2 Semiconductor memory device comprising a plurality of static memory cells 有权
标题翻译：半导体存储器件包括多个静态存储单元
公开(公告)号：US08310883B2
公开(公告)日：2012-11-13
申请号：US13193258
申请日：2011-07-28
申请人： Makoto Yabuuchi , Koji Nii
发明人： Makoto Yabuuchi , Koji Nii
IPC分类号： G11C7/00
CPC分类号： G11C8/08 , G11C5/147 , G11C11/412 , G11C11/413
摘要： A driver power supply circuit stepping down a power supply voltage is arranged at a power supply node of a word line driver. The driver power supply circuit includes a non-silicide resistance element of N+ doped polycrystalline silicon, and a pull-down circuit lowering a voltage level of the driver power supply node. The pull-down circuit includes a pull-down transistor having the same threshold voltage characteristics as a memory cell transistor pulling down a voltage level of the driver power supply node, and a gate control circuit adjusting at least a gate voltage of the pull-down transistor. The gate control circuit corrects the gate potential of the pull-down transistor in a manner linked to variations in threshold voltage of the memory cell transistor.
摘要翻译：降低电源电压的驱动器电源电路被布置在字线驱动器的电源节点处。驱动器电源电路包括N +掺杂多晶硅的非硅化物电阻元件和降低驱动器电源节点的电压电平的下拉电路。下拉电路包括具有与下拉驱动器电源节点的电压电平的存储单元晶体管相同的阈值电压特性的下拉晶体管，以及至少调节下拉电路的栅极电压的栅极控制电路晶体管。栅极控制电路以与存储单元晶体管的阈值电压的变化相关联的方式校正下拉晶体管的栅极电位。

3. 发明授权

US07876625B2 Semiconductor memory device comprising a plurality of static memory cells 有权
公开(公告)号：US07876625B2
公开(公告)日：2011-01-25
申请号：US12555447
申请日：2009-09-08
申请人： Makoto Yabuuchi , Koji Nii
发明人： Makoto Yabuuchi , Koji Nii
IPC分类号： G11C7/00
CPC分类号： G11C8/08 , G11C5/147 , G11C11/412 , G11C11/413
摘要： A driver power supply circuit stepping down a power supply voltage is arranged at a power supply node of a word line driver. The driver power supply circuit includes a non-silicide resistance element of N+ doped polycrystalline silicon, and a pull-down circuit lowering a voltage level of the driver power supply node. The pull-down circuit includes a pull-down transistor having the same threshold voltage characteristics as a memory cell transistor pulling down a voltage level of the driver power supply node, and a gate control circuit adjusting at least a gate voltage of the pull-down transistor. The gate control circuit corrects the gate potential of the pull-down transistor in a manner linked to variations in threshold voltage of the memory cell transistor.

4. 发明授权

US10032781B2 Static random access memory device with halo regions having different impurity concentrations 有权
公开(公告)号：US10032781B2
公开(公告)日：2018-07-24
申请号：US14236067
申请日：2011-07-29
申请人： Koji Nii , Makoto Yabuuchi , Yasumasa Tsukamoto , Kengo Masuda
发明人： Koji Nii , Makoto Yabuuchi , Yasumasa Tsukamoto , Kengo Masuda
IPC分类号： H01L27/088 , H01L27/11 , H01L27/02 , H01L21/265 , H01L29/66 , H01L29/10 , G11C11/412
摘要： In a region just below an access gate electrode in an SRAM memory cell, a second halo region is formed adjacent to a source-drain region and a first halo region is formed adjacent to a first source-drain region. In a region just below a drive gate electrode, a third halo region is formed adjacent to the third source-drain region and a fourth halo region is formed adjacent to a fourth source-drain region. The second halo region is set to have an impurity concentration higher than the impurity concentration of the first halo region. The third halo region is set to have an impurity concentration higher than the impurity concentration of the fourth halo region. The impurity concentration of the first halo region and the impurity concentration of the fourth halo region are different from each other.

5. 发明授权

US08098533B2 Semiconductor memory device with adjustable selected word line potential under low voltage condition 有权
标题翻译：半导体存储器件，在低电压条件下具有可选择的字线电位
公开(公告)号：US08098533B2
公开(公告)日：2012-01-17
申请号：US12457936
申请日：2009-06-25
申请人： Koji Nii , Shigeki Ohbayashi , Yasumasa Tsukamoto , Makoto Yabuuchi
发明人： Koji Nii , Shigeki Ohbayashi , Yasumasa Tsukamoto , Makoto Yabuuchi
IPC分类号： G11C7/00
CPC分类号： G11C11/419 , G11C5/06 , G11C5/14 , G11C8/08 , G11C11/417 , G11C11/418
摘要： A level shift element adjusting a voltage level at the time of selection of a word line according to fluctuations in threshold voltage of a memory cell transistor is arranged for each word line. This level shift element lowers a driver power supply voltage, and transmits the level-shifted voltage onto a selected word line. The level shift element can be replaced with a pull-down element for pulling down the word line voltage according to the threshold voltage level of the memory cell transistor. In either case, the selected word line voltage level can be adjusted according to the fluctuations in threshold voltage of the memory cell transistor without using another power supply system. Thus, the power supply circuitry is not complicated, and it is possible to achieve a semiconductor memory device that can stably read and write data even with a low power supply voltage.
摘要翻译：针对每个字线布置根据存储单元晶体管的阈值电压的波动来调整在选择字线时的电压电平的电平移动元件。该电平移动元件降低驱动器电源电压，并将电平移位电压发送到所选择的字线上。电平移位元件可以用用于根据存储单元晶体管的阈值电压电平来拉低字线电压的下拉元件来代替。在任一情况下，可以根据存储单元晶体管的阈值电压的波动来调整所选字线电压电平，而不使用另一电源系统。因此，电源电路不复杂，即使在低电源电压下也可以实现能够稳定地读写数据的半导体存储器件。

6. 发明授权

US08018785B2 Semiconductor memory device comprising a plurality of static memory cells 有权
标题翻译：半导体存储器件包括多个静态存储单元
公开(公告)号：US08018785B2
公开(公告)日：2011-09-13
申请号：US12909465
申请日：2010-10-21
申请人： Makoto Yabuuchi , Koji Nii
发明人： Makoto Yabuuchi , Koji Nii
IPC分类号： G11C7/00
CPC分类号： G11C8/08 , G11C5/147 , G11C11/412 , G11C11/413
摘要： A driver power supply circuit stepping down a power supply voltage is arranged at a power supply node of a word line driver. The driver power supply circuit includes a non-silicide resistance element of N+ doped polycrystalline silicon, and a pull-down circuit lowering a voltage level of the driver power supply node. The pull-down circuit includes a pull-down transistor having the same threshold voltage characteristics as a memory cell transistor pulling down a voltage level of the driver power supply node, and a gate control circuit adjusting at least a gate voltage of the pull-down transistor. The gate control circuit corrects the gate potential of the pull-down transistor in a manner linked to variations in threshold voltage of the memory cell transistor.
摘要翻译：降低电源电压的驱动器电源电路被布置在字线驱动器的电源节点处。驱动器电源电路包括N +掺杂多晶硅的非硅化物电阻元件和降低驱动器电源节点的电压电平的下拉电路。下拉电路包括具有与下拉驱动器电源节点的电压电平的存储单元晶体管相同的阈值电压特性的下拉晶体管，以及至少调节下拉电路的栅极电压的栅极控制电路晶体管。栅极控制电路以与存储单元晶体管的阈值电压的变化相关联的方式校正下拉晶体管的栅极电位。

7. 发明授权

US07602654B2 Semiconductor memory device comprising a plurality of static memory cells 有权
标题翻译：半导体存储器件包括多个静态存储单元
公开(公告)号：US07602654B2
公开(公告)日：2009-10-13
申请号：US11889145
申请日：2007-08-09
申请人： Makoto Yabuuchi , Koji Nii
发明人： Makoto Yabuuchi , Koji Nii
IPC分类号： G11C7/00
CPC分类号： G11C8/08 , G11C5/147 , G11C11/412 , G11C11/413
摘要： A driver power supply circuit stepping down a power supply voltage is arranged at a power supply node of a word line driver. The driver power supply circuit includes a non-silicide resistance element of N+ doped polycrystalline silicon, and a pull-down circuit lowering a voltage level of the driver power supply node. The pull-down circuit includes a pull-down transistor having the same threshold voltage characteristics as a memory cell transistor pulling down a voltage level of the driver power supply node, and a gate control circuit adjusting at least a gate voltage of the pull-down transistor. The gate control circuit corrects the gate potential of the pull-down transistor in a manner linked to variations in threshold voltage of the memory cell transistor.
摘要翻译：降低电源电压的驱动器电源电路被布置在字线驱动器的电源节点处。驱动器电源电路包括N +掺杂多晶硅的非硅化物电阻元件和降低驱动器电源节点的电压电平的下拉电路。下拉电路包括具有与下拉驱动器电源节点的电压电平的存储单元晶体管相同的阈值电压特性的下拉晶体管，以及至少调节下拉电路的栅极电压的栅极控制电路晶体管。栅极控制电路以与存储单元晶体管的阈值电压的变化相关联的方式校正下拉晶体管的栅极电位。

8. 发明授权

US08743645B2 Semiconductor memory device for stably reading and writing data 有权
标题翻译：用于稳定读取和写入数据的半导体存储器件
公开(公告)号：US08743645B2
公开(公告)日：2014-06-03
申请号：US13325945
申请日：2011-12-14
申请人： Koji Nii , Shigeki Ohbayashi , Yasumasa Tsukamoto , Makoto Yabuuchi
发明人： Koji Nii , Shigeki Ohbayashi , Yasumasa Tsukamoto , Makoto Yabuuchi
IPC分类号： G11C5/14
CPC分类号： G11C11/419 , G11C5/06 , G11C5/14 , G11C8/08 , G11C11/417 , G11C11/418
摘要： In a semiconductor memory device, static memory cells are arranged in rows and columns, word lines correspond to respective memory cell rows, and word line drivers drive correspond to word lines. Cell power supply lines correspond to respective memory cell columns and are coupled to cell power supply nodes of a memory cell in a corresponding column. Down power supply lines are arranged corresponding to respective memory cell columns, maintained at ground voltage in data reading and rendered electrically floating in data writing. Write assist elements are arranged corresponding to the cell power supply lines, and according to a write column instruction signal for stopping supply of a cell power supply voltage to the cell power supply line in a selected column, and for coupling the cell power supply line arranged corresponding to the selected column at least to the down power supply line on the corresponding column.
摘要翻译：在半导体存储器件中，静态存储单元以行和列排列，字线对应于相应的存储单元行，并且字线驱动器对应于字线。单元电源线对应于相应的存储单元列并且耦合到相应列中的存储器单元的单元电源节点。向下电源线被布置成对应于相应的存储单元列，保持在数据读取中的接地电压并且在数据写入中被电浮动。写入辅助元件对应于单电池电源线布置，并且根据写入列指示信号，用于停止向所选列中的单元电源线提供单元电源电压，并且用于耦合布置的单元电源线对应于所选列至少至相应列上的下电源线。

9. 发明申请

US20120087198A1 SEMICONDUCTOR MEMORY DEVICE WITH ADJUSTABLE SELECTED WORK LINE POTENTIAL UNDER LOW VOLTAGE CONDITION 有权
标题翻译：在低电压条件下具有可调节选择的工作线电位的半导体存储器件
公开(公告)号：US20120087198A1
公开(公告)日：2012-04-12
申请号：US13325945
申请日：2011-12-14
申请人： Koji Nii , Shigeki Ohbayashi , Yasumasa Tsukamoto , Makoto Yabuuchi
发明人： Koji Nii , Shigeki Ohbayashi , Yasumasa Tsukamoto , Makoto Yabuuchi
IPC分类号： G11C5/14
CPC分类号： G11C11/419 , G11C5/06 , G11C5/14 , G11C8/08 , G11C11/417 , G11C11/418
摘要： A level shift element adjusting a voltage level at the time of selection of a word line according to fluctuations in threshold voltage of a memory cell transistor is arranged for each word line. This level shift element lowers a driver power supply voltage, and transmits the level-shifted voltage onto a selected word line. The level shift element can be replaced with a pull-down element for pulling down the word line voltage according to the threshold voltage level of the memory cell transistor. In either case, the selected word line voltage level can be adjusted according to the fluctuations in threshold voltage of the memory cell transistor without using another power supply system. Thus, the power supply circuitry is not complicated, and it is possible to achieve a semiconductor memory device that can stably read and write data even with a low power supply voltage.
摘要翻译：针对每个字线布置根据存储单元晶体管的阈值电压的波动来调整在选择字线时的电压电平的电平移动元件。该电平移动元件降低驱动器电源电压，并将电平移位电压发送到所选择的字线上。电平移位元件可以用用于根据存储单元晶体管的阈值电压电平来拉低字线电压的下拉元件来代替。在任一情况下，可以根据存储单元晶体管的阈值电压的波动来调整所选字线电压电平，而不使用另一电源系统。因此，电源电路不复杂，即使在低电源电压下也可以实现能够稳定地读写数据的半导体存储器件。

10. 发明申请

US20070030741A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20070030741A1
公开(公告)日：2007-02-08
申请号：US11492031
申请日：2006-07-25
申请人： Koji Nii , Shigeki Ohbayashi , Yasumasa Tsukamoto , Makoto Yabuuchi
发明人： Koji Nii , Shigeki Ohbayashi , Yasumasa Tsukamoto , Makoto Yabuuchi
IPC分类号： G11C7/00
CPC分类号： G11C11/419 , G11C5/06 , G11C5/14 , G11C8/08 , G11C11/417 , G11C11/418
摘要： A level shift element adjusting a voltage level at the time of selection of a word line according to fluctuations in threshold voltage of a memory cell transistor is arranged for each word line. This level shift element lowers a driver power supply voltage, and transmits the level-shifted voltage onto a selected word line. The level shift element can be replaced with a pull-down element for pulling down the word line voltage according to the threshold voltage level of the memory cell transistor. In either case, the selected word line voltage level can be adjusted according to the fluctuations in threshold voltage of the memory cell transistor without using another power supply system. Thus, the power supply circuitry is not complicated, and it is possible to achieve a semiconductor memory device that can stably read and write data even with a low power supply voltage.
摘要翻译：针对每个字线布置根据存储单元晶体管的阈值电压的波动来调整在选择字线时的电压电平的电平移动元件。该电平移动元件降低驱动器电源电压，并将电平移位电压发送到所选择的字线上。电平移位元件可以用用于根据存储单元晶体管的阈值电压电平来拉低字线电压的下拉元件来代替。在任一情况下，可以根据存储单元晶体管的阈值电压的波动来调整所选字线电压电平，而不使用另一电源系统。因此，电源电路不复杂，即使在低电源电压下也可以实现能够稳定地读写数据的半导体存储器件。

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