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1. 发明授权

US08169807B2 Content addressable memory device having match line equalizer circuit 有权
标题翻译：具有匹配线均衡器电路的内容可寻址存储器件
公开(公告)号：US08169807B2
公开(公告)日：2012-05-01
申请号：US12261598
申请日：2008-10-30
申请人： Katsumi Dosaka , Kazutami Arimoto , Yoshio Matsuda
发明人： Katsumi Dosaka , Kazutami Arimoto , Yoshio Matsuda
IPC分类号： G11C15/00
CPC分类号： G06F17/30982 , G11C15/04 , Y02D10/45
摘要： In a content addressable memory device, before search operations in two TCAM cells connected to first and second match lines, respectively, a memory controller connects the first match line to a power source and connects the second match line to a ground, and then connects the first and second match lines to each other so as that electric potentials of the first and second match lines are the same as each other.
摘要翻译：在内容可寻址存储器件中，在分别连接到第一和第二匹配线的两个TCAM单元中的搜索操作之前，存储器控制器将第一匹配线连接到电源，并将第二匹配线连接到地，然后将第一和第二匹配线彼此之间，使得第一和第二匹配线的电位彼此相同。

2. 发明申请

US20090113122A1 CONTENT ADDRESSABLE MEMORY DEVICE HAVING MATCH LINE EQUALIZER CIRCUIT 有权
标题翻译：具有匹配线路均衡器电路的内容可寻址存储器件
公开(公告)号：US20090113122A1
公开(公告)日：2009-04-30
申请号：US12261598
申请日：2008-10-30
申请人： Katsumi Dosaka , Kazutami Arimoto , Yoshio Matsuda
发明人： Katsumi Dosaka , Kazutami Arimoto , Yoshio Matsuda
IPC分类号： G06F12/00 , G06F17/30
CPC分类号： G06F17/30982 , G11C15/04 , Y02D10/45
摘要： In a content addressable memory device, before search operations in two TCAM cells connected to first and second match lines, respectively, a memory controller connects the first match line to a power source and connects the second match line to a ground, and then connects the first and second match lines to each other so as that electric potentials of the first and second match lines are the same as each other.
摘要翻译：在内容可寻址存储器件中，在分别连接到第一和第二匹配线的两个TCAM单元中的搜索操作之前，存储器控制器将第一匹配线连接到电源，并将第二匹配线连接到地，然后将第一和第二匹配线彼此之间，使得第一和第二匹配线的电位彼此相同。

3. 发明申请

US20090070525A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20090070525A1
公开(公告)日：2009-03-12
申请号：US12268017
申请日：2008-11-10
申请人： Katsumi DOSAKA , Kazutami Arimoto , Kazunori Saito , Hideyuki Noda
发明人： Katsumi DOSAKA , Kazutami Arimoto , Kazunori Saito , Hideyuki Noda
IPC分类号： G06F12/00
CPC分类号： G11C15/04 , G11C15/00
摘要： A CAM (Content Addressable Memory) cell includes first and second data storage portions storing data, horizontal port write gates for storing data applied through a match line pair in the data storage portions in a data write through a horizontal port, and search/read gates for driving the match lines of the match line pair in accordance with the data stored in the data storage portions in a search operation and in a data read through the horizontal port. The match lines are used as horizontal bit line pair, or signal lines for accessing the horizontal port. As the first and second data storage portions are used, it becomes possible to store ternary data, and accordingly, a write mask function of inhibiting a data write at a destination of data transfer is realized. Further, as the CAM cell is used, an arithmetic/logic operation following a search process can be executed selectively, and high speed data writing/reading becomes possible.
摘要翻译： CAM（内容可寻址存储器）单元包括存储数据的第一和第二数据存储部分，水平端口写入门，用于通过水平端口在数据存储部分中存储通过匹配线对应用的数据，以及搜索/读取门用于根据搜索操作中存储在数据存储部分中的数据和通过水平端口读取的数据来驱动匹配线对的匹配线。匹配线用作水平位线对或用于访问水平端口的信号线。当使用第一和第二数据存储部分时，可以存储三进制数据，因此实现了在数据传送目的地禁止数据写入的写掩码功能。此外，当使用CAM单元时，可以选择性地执行搜索处理之后的算术/逻辑运算，并且可以进行高速数据写入/读取。

4. 发明授权

US06400625B2 Semiconductor integrated circuit device capable of performing operational test for contained memory core at operating frequency higher than that of memory tester 失效
标题翻译：半导体集成电路器件能够以比存储器测试器更高的工作频率对包含的存储器核进行操作测试
公开(公告)号：US06400625B2
公开(公告)日：2002-06-04
申请号：US09810503
申请日：2001-03-19
申请人： Kazutami Arimoto , Hiroki Shimano , Katsumi Dosaka
发明人： Kazutami Arimoto , Hiroki Shimano , Katsumi Dosaka
IPC分类号： G11C700
CPC分类号： G11C29/48
摘要： A test interface circuit carries out an operational test based on a signal input to test pin terminals by directly accessing a DRAM core. A frequency multiplication circuit generates an internal test clock signal by multiplying the frequency of an external test clock signal input to the test pin terminal. A data shifter shifts read data from the DRAM core which operates according to the internal test clock signal in a test mode by N clock cycles (N is an integer of at least 0 determined by column latency) of the internal test clock signal to output the read data from the test pin terminals in synchronization with the external clock test signal.
摘要翻译：测试接口电路基于通过直接访问DRAM内核来测试引脚端子的信号输入进行操作测试。倍频电路通过将输入到测试引脚端子的外部测试时钟信号的频率相乘来生成内部测试时钟信号。数据移位器根据内部测试时钟信号在内部测试时钟信号的N个时钟周期（N为至少为0的整数，由列延迟确定）中，根据测试模式的内部测试时钟信号来移动读取数据，以输出从外部时钟测试信号同步读取测试引脚端子的数据。

5. 发明授权

US07463501B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07463501B2
公开(公告)日：2008-12-09
申请号：US11517441
申请日：2006-09-08
申请人： Katsumi Dosaka , Kazutami Arimoto , Kazunori Saito , Hideyuki Noda
发明人： Katsumi Dosaka , Kazutami Arimoto , Kazunori Saito , Hideyuki Noda
IPC分类号： G11C7/00
CPC分类号： G11C15/04 , G11C15/00
摘要： A CAM (Content Addressable Memory) cell includes first and second data storage portions storing data, horizontal port write gates for storing data applied through a match line pair in the data storage portions in a data write through a horizontal port, and search/read gates for driving the match lines of the match line pair in accordance with the data stored in the data storage portions in a search operation and in a data read through the horizontal port. The match lines are used as horizontal bit line pair, or signal lines for accessing the horizontal port. As the first and second data storage portions are used, it becomes possible to store ternary data, and accordingly, a write mask function of inhibiting a data write at a destination of data transfer is realized. Further, as the CAM cell is used, an arithmetic/logic operation following a search process can be executed selectively, and high speed data writing/reading becomes possible.
摘要翻译： CAM（内容可寻址存储器）单元包括存储数据的第一和第二数据存储部分，水平端口写入门，用于通过水平端口在数据存储部分中存储通过匹配线对应用的数据，以及搜索/读取门用于根据搜索操作中存储在数据存储部分中的数据和通过水平端口读取的数据来驱动匹配线对的匹配线。匹配线用作水平位线对或用于访问水平端口的信号线。当使用第一和第二数据存储部分时，可以存储三进制数据，因此实现了在数据传送目的地禁止数据写入的写掩码功能。此外，当使用CAM单元时，可以选择性地执行搜索处理之后的算术/逻辑运算，并且可以进行高速数据写入/读取。

6. 发明授权

US08089819B2 Semiconductor device and semiconductor signal processing apparatus 失效
标题翻译：半导体装置及半导体信号处理装置
公开(公告)号：US08089819B2
公开(公告)日：2012-01-03
申请号：US12857063
申请日：2010-08-16
申请人： Hideyuki Noda , Kazunori Saitoh , Kazutami Arimoto , Katsumi Dosaka
发明人： Hideyuki Noda , Kazunori Saitoh , Kazutami Arimoto , Katsumi Dosaka
IPC分类号： G11C7/06
CPC分类号： G11C7/1006
摘要： A memory cell mat is divided into a plurality of entries, and an arithmetic logic unit is arranged corresponding to each entry. Between the entries and the corresponding arithmetic logic units, arithmetic/logic operation is executed in bit-serial and entry-parallel manner. Where parallel operation is not very effective, data is transferred in entry-serial and bit-parallel manner to a group of processors provided at a lower portion of the memory mat. In this manner, a large amount of data can be processed at high speed regardless of the contents of operation or data bit width.
摘要翻译：存储单元垫被分成多个条目，并且对应于每个条目布置了算术逻辑单元。在条目和相应的算术逻辑单元之间，以比特串行和并行方式执行算术/逻辑运算。在并行操作不是非常有效的情况下，数据以串行和位并行方式传送到设置在存储器垫的下部的一组处理器。以这种方式，无论操作内容或数据位宽度如何，都可以高速处理大量的数据。

7. 发明授权

US06649984B1 Logic-merged memory 有权
标题翻译：逻辑合并记忆
公开(公告)号：US06649984B1
公开(公告)日：2003-11-18
申请号：US09632333
申请日：2000-08-03
申请人： Hideyuki Noda , Kazutami Arimoto , Katsumi Dosaka , Takeshi Fujino
发明人： Hideyuki Noda , Kazutami Arimoto , Katsumi Dosaka , Takeshi Fujino
IPC分类号： H01L29792
CPC分类号： H01L27/10897 , G11C5/025 , G11C7/1006 , G11C7/18 , G11C29/12
摘要： In a memory circuit, a transistor formed in the same process as that of a logic transistor is used for peripheral circuitry except for a region to be supplied with high voltage. Thus, the manufacturing process can be simplified and a logic-merged memory operating at a high speed is provided.
摘要翻译：在存储器电路中，以与逻辑晶体管相同的工艺形成的晶体管用于外围电路，除了要被提供高电压的区域之外。因此，可以简化制造过程，并且提供以高速运行的逻辑合并存储器。

8. 发明申请

US20070058407A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20070058407A1
公开(公告)日：2007-03-15
申请号：US11517441
申请日：2006-09-08
申请人： Katsumi Dosaka , Kazutami Arimoto , Kazunori Saito , Hideyuki Noda
发明人： Katsumi Dosaka , Kazutami Arimoto , Kazunori Saito , Hideyuki Noda
IPC分类号： G11C15/00
CPC分类号： G11C15/04 , G11C15/00
摘要： A CAM (Content Addressable Memory) cell includes first and second data storage portions storing data, horizontal port write gates for storing data applied through a match line pair in the data storage portions in a data write through a horizontal port, and search/read gates for driving the match lines of the match line pair in accordance with the data stored in the data storage portions in a search operation and in a data read through the horizontal port. The match lines are used as horizontal bit line pair, or signal lines for accessing the horizontal port. As the first and second data storage portions are used, it becomes possible to store ternary data, and accordingly, a write mask function of inhibiting a data write at a destination of data transfer is realized. Further, as the CAM cell is used, an arithmetic/logic operation following a search process can be executed selectively, and high speed data writing/reading becomes possible.
摘要翻译： CAM（内容可寻址存储器）单元包括存储数据的第一和第二数据存储部分，水平端口写入门，用于通过水平端口在数据存储部分中存储通过匹配线对应用的数据，以及搜索/读取门用于根据搜索操作中存储在数据存储部分中的数据和通过水平端口读取的数据来驱动匹配线对的匹配线。匹配线用作水平位线对或用于访问水平端口的信号线。当使用第一和第二数据存储部分时，可以存储三进制数据，因此实现了在数据传送目的地禁止数据写入的写掩码功能。此外，当使用CAM单元时，可以选择性地执行搜索处理之后的算术/逻辑运算，并且可以进行高速数据写入/读取。

9. 发明授权

US07102954B2 Semiconductor integrated circuit device having logic circuit and dynamic random access memory on the same chip 有权
标题翻译：具有在同一芯片上的逻辑电路和动态随机存取存储器的半导体集成电路器件
公开(公告)号：US07102954B2
公开(公告)日：2006-09-05
申请号：US10714393
申请日：2003-11-17
申请人： Hideyuki Noda , Kazutami Arimoto , Katsumi Dosaka , Takeshi Fujino
发明人： Hideyuki Noda , Kazutami Arimoto , Katsumi Dosaka , Takeshi Fujino
IPC分类号： G11C5/14 , G11C29/06
CPC分类号： H01L27/10897 , G11C5/025 , G11C7/1006 , G11C7/18 , G11C29/12
摘要： In a memory circuit, a transistor formed in the same process as that of a logic transistor is used for peripheral circuitry except for a region to be supplied with high voltage. Thus, the manufacturing process can be simplified and a logic-merged memory operating at a high speed is provided.
摘要翻译：在存储器电路中，以与逻辑晶体管相同的工艺形成的晶体管用于外围电路，除了要被提供高电压的区域之外。因此，可以简化制造过程，并且提供以高速运行的逻辑合并存储器。

10. 发明申请

US20060143428A1 Semiconductor signal processing device 审中-公开
标题翻译：半导体信号处理装置
公开(公告)号：US20060143428A1
公开(公告)日：2006-06-29
申请号：US11282714
申请日：2005-11-21
申请人： Hideyuki Noda , Kazutami Arimoto , Katsumi Dosaka , Kazunori Saito
发明人： Hideyuki Noda , Kazutami Arimoto , Katsumi Dosaka , Kazunori Saito
IPC分类号： G06F15/00 , G06F7/48
CPC分类号： G06F7/785 , G11C5/025 , G11C7/1006 , G11C7/18 , G11C8/16 , G11C11/419 , G11C2207/104
摘要： An orthogonal memory for transforming arrangements of system bus data and processing data is placed between a system bus interface and a memory cell mat storing the processing data. The orthogonal memory includes two-port memory cells, and changes data train transferred in a bit parallel and word serial fashion into a data train of word parallel and bit serial data. Data transfer efficiency in a signal processing device performing parallel operational processing can be increased without impairing parallelism of the processing.
摘要翻译：用于变换系统总线数据和处理数据的布置的正交存储器被放置在系统总线接口和存储处理数据的存储单元矩阵之间。正交存储器包括双端口存储器单元，并且将以位并行和字串行方式传送的数据串改变成字并行和位串行数据的数据串。可以增加执行并行操作处理的信号处理装置中的数据传送效率，而不会削弱处理的并行性。

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