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1. 发明授权

US06535937B1 Write command verification across a PCI bus system 失效
标题翻译：通过PCI总线系统编写命令验证
公开(公告)号：US06535937B1
公开(公告)日：2003-03-18
申请号：US09503911
申请日：2000-02-15
申请人： Brent Cameron Beardsley , Michael Thomas Benhase , Russell Lee Ellison , Gregg Steven Lucas , Juan Antonio Yanes
发明人： Brent Cameron Beardsley , Michael Thomas Benhase , Russell Lee Ellison , Gregg Steven Lucas , Juan Antonio Yanes
IPC分类号： G06F1338
CPC分类号： G06F13/4221 , G06F13/4027
摘要： A method and system to verify the passage of one or more write commands sent from an originating location through a PCI bus system. An addressable data storage is located substantially at the end of the PCI bus system with respect to the originating location. A write command is sent by the originator subsequent to the one or more write commands, to a predetermined special end location address identifying the addressable storage. The command is accompanied by data comprising a predetermined special return address at the originating location. The PCI bus system transmits the write commands on a FIFO basis, so the one or more write commands precede the subsequently sent write command. Logic senses the subsequently sent write command, and responds to the command, sending a return echo write command to the predetermined special return address. The returning echo write command verifies the passage of the write commands and data through the PCI bus system. The predetermined special end location address is the key to identify the subsequently sent write command.
摘要翻译：一种用于验证从始发位置通过PCI总线系统发送的一个或多个写入命令的通过的方法和系统。相对于始发位置，可寻址数据存储器基本上位于PCI总线系统的末端。写命令由发起者在一个或多个写入命令之后发送到标识可寻址存储器的预定特殊结束位置地址。该命令伴随着在始发位置处包括预定的特殊返回地址的数据。 PCI总线系统以FIFO为基础发送写命令，因此一个或多个写命令先于随后发送的写命令。逻辑检测随后发送的写入命令，并响应该命令，向预定的特殊返回地址发送返回回显写命令。返回的回写写命令通过PCI总线系统验证写命令和数据的通过。预定的特殊终端位置地址是识别随后发送的写命令的关键。

2. 发明授权

US06490644B1 Limiting write data fracturing in PCI bus systems 失效
$Limiting write data fracturing in PCI bus systems$
标题翻译：限制PCI总线系统中的写入数据压缩
公开(公告)号：US06490644B1
公开(公告)日：2002-12-03
申请号：US09521387
申请日：2000-03-08
申请人： Joseph Smith Hyde, II , Robert Earl Medlin , Juan Antonio Yanes
发明人： Joseph Smith Hyde, II , Robert Earl Medlin , Juan Antonio Yanes
IPC分类号： G06F13372
CPC分类号： G06F13/362
摘要： A system for limiting fracturing of write data by a PCI bus adapter which queues operation commands in a command queue. The write data is in the form of bursts comprising a plurality of contiguous words. Fracture detection logic senses fracturing of the write data. A bus arbiter is responsive to the sensed fracturing of write data by the target, and blocks access to the PCI bus. Queue level detection logic is employed, subsequent to the blocking, to monitor completion of the queued operation commands of the PCI bus target. The bus arbiter is then responsive to the queue level detection logic indicating that the PCI bus target has completed enough operations that a predetermined number (such as one) of the operation commands remain queued at its command queue, and grants access to the PCI bus to complete the burst write operation without fracturing.
摘要翻译：用于通过PCI总线适配器限制写数据压缩的系统，其将命令队列中的操作命令排队。写数据是包括多个连续字的突发的形式。断裂检测逻辑检测写入数据的压裂。总线仲裁器响应于由目标感测到的写入数据的压缩，并阻止对PCI总线的访问。在阻塞之后采用队列级检测逻辑来监视PCI总线目标的排队操作命令的完成。总线仲裁器然后响应于队列等级检测逻辑，指示PCI总线目标已经完成足够的操作，其中预定数量（诸如一个）操作命令在其命令队列中保持排队，并且授予对PCI总线的访问完成突发写入操作而不破裂。

3. 发明授权

US06189117B1 Error handling between a processor and a system managed by the processor 有权
标题翻译：处理器与由处理器管理的系统之间的错误处理
公开(公告)号：US06189117B1
公开(公告)日：2001-02-13
申请号：US09135835
申请日：1998-08-18
申请人： Gary William Batchelor , Brent Cameron Beardsley , Michael Thomas Benhase , Jack Harvey Derenburger , Carl Evan Jones , Robert Earl Medlin , Belayneh Tafesse , Juan Antonio Yanes
发明人： Gary William Batchelor , Brent Cameron Beardsley , Michael Thomas Benhase , Jack Harvey Derenburger , Carl Evan Jones , Robert Earl Medlin , Belayneh Tafesse , Juan Antonio Yanes
IPC分类号： G06F1100
CPC分类号： G06F11/0796
摘要： Disclosed is a system for handling errors. A system managed by a processor processes an error in the system. The system then generates an interrupt to the processor indicating that an error occurred and executes an error mode before the processor interprets the interrupt. As part of the error mode, the system prevents data from transferring between the system and the processor and processes a read request from the processor to the system by returning data to the processor unrelated to the requested data. The processor would then process the interrupt indicating the error and execute a diagnostic mode to diagnose the error in the system.
摘要翻译：公开了一种处理错误的系统。由处理器管理的系统处理系统中的错误。系统然后在处理器解释中断之前，向处理器产生指示发生错误的中断并执行错误模式。作为错误模式的一部分，系统防止数据在系统和处理器之间传输，并通过将数据返回到与请求的数据无关的处理器来处理从处理器到系统的读取请求。然后处理器将处理指示错误的中断，并执行诊断模式以诊断系统中的错误。

4. 发明授权

US6038613A Prefetching and storing device work information from multiple data storage devices 失效
标题翻译：从多个数据存储设备预取和存储设备工作信息
公开(公告)号：US6038613A
公开(公告)日：2000-03-14
申请号：US971085
申请日：1997-11-14
申请人： Enrique Q Garcia , Gregg Steven Lucas , James Richard Pollock , Juan Antonio Yanes
发明人： Enrique Q Garcia , Gregg Steven Lucas , James Richard Pollock , Juan Antonio Yanes
IPC分类号： G06F3/06 , G06F13/12 , G06F13/00
CPC分类号： G06F3/0607 , G06F13/122 , G06F3/0632 , G06F3/0653 , G06F3/0674
摘要： A device controller is described within a data storage system for pre-fetching device work information from multiple data storage devices, and accumulating the device work information to immediately respond to a subsequent device poll command from a storage controller. The device controller includes a device receiver to receive the device poll command, a device transmitter to transmit a response to the device poll command, a device information register for storing the pre-fetched device work information for each data storage device, and a sequencer for periodically pre-fetching the device work information from each data storage device. The sequencer pre-fetches such information by verifying that no device subsystem command from the storage controller is pending in the device receiver, then issuing a background poll command to a selected device to query the device for its device work information, and storing the device work information in the device information register. The device controller can then immediately respond to a subsequent device poll command issued from the storage controller by copying the device work information from the device information register to the device transmitter.
摘要翻译：在数据存储系统内描述设备控制器，用于从多个数据存储设备预取设备工作信息，并累积设备工作信息以立即响应来自存储控制器的后续设备轮询命令。设备控制器包括接收设备轮询命令的设备接收器，用于发送对设备轮询命令的响应的设备发送器，用于存储每个数据存储设备的预取设备工作信息的设备信息寄存器，以及用于定期从每个数据存储设备预取设备工作信息。定序器通过验证设备接收器中没有来自存储控制器的设备子系统命令等待处理，然后向所选设备发出后台轮询命令来查询设备的设备工作信息，并存储设备工作，从而预取这些信息设备信息寄存器中的信息。然后，设备控制器可以通过将设备工作信息从设备信息寄存器复制到设备发送器来立即响应从存储控制器发出的后续设备轮询命令。

5. 发明授权

US5928375A Method for enhancing data transmission in parity based data processing systems 失效
标题翻译：在基于奇偶校验的数据处理系统中增强数据传输的方法
公开(公告)号：US5928375A
公开(公告)日：1999-07-27
申请号：US780570
申请日：1997-01-08
申请人： Gregg Steven Lucas , Juan Antonio Yanes
发明人： Gregg Steven Lucas , Juan Antonio Yanes
IPC分类号： G06F13/42 , G06F13/00 , H03M13/09 , H04L1/00 , H04L7/00 , G06F11/10 , H03M13/00
CPC分类号： H04L1/0057 , H03M13/09
摘要： A data transfer system providing parity uses a method and apparatus for transmitting a data clocking signal in a parity bit location along a data bus to latch an accompanying data byte at a receiving device. A transmitting device, coupled to the receiving device through the data bus, generates a data clock signal and latches the clock signal into the parity bit location of the data bus. The clock signal and data byte are then transmitted along the data bus to the receiving device. The receiving device uses the clock signal to latch the data byte from the data bus. Thus, the data transfer system uses the data clock signal transmitted in the parity bit location of the data bus to validate and synchronize the accompanying data byte at the receiving device.
摘要翻译：提供奇偶校验的数据传送系统使用方法和装置，用于沿着数据总线在奇偶位位置发送数据时钟信号，以在接收装置处锁存伴随的数据字节。通过数据总线耦合到接收装置的发送装置产生数据时钟信号并将时钟信号锁存到数据总线的奇偶校验位。然后，时钟信号和数据字节沿数据总线发送到接收装置。接收设备使用时钟信号来锁存数据总线上的数据字节。因此，数据传输系统使用在数据总线的奇偶校验位位置中发送的数据时钟信号来验证并同步接收设备附带的数据字节。

6. 发明授权

US06246726B1 High speed digital data transmission by separately clocking and recombining interleaved data subgroups 失效
标题翻译：通过单独计时和重组交错数据子组实现高速数字数据传输
公开(公告)号：US06246726B1
公开(公告)日：2001-06-12
申请号：US09514025
申请日：2000-02-25
申请人： Enrique Garcia , Gregg Steven Lucas , Juan Antonio Yanes
发明人： Enrique Garcia , Gregg Steven Lucas , Juan Antonio Yanes
IPC分类号： H04L2704
CPC分类号： H04L7/0008
摘要： To exchange a digital data input stream, a transmitter sends the digital data input stream to a receiver, and the receiver sequentially divides the stream into different interleaved substreams and later combines the substreams to provide an output including the original digital data input stream. The original digital data input stream includes multiple subgroups of data, such as bytes. Each subgroup is stored in a selected buffer of the receiver. Buffers are selected in a predetermined order of rotation to store sequentially received subgroups. Thus, each buffer receives subgroups in a defined order. Later, each buffer outputs its stored subgroups in the same order as received. A data assembler assembles the subgroups output by the various buffers, reconstructing the original digital input stream.
摘要翻译：为了交换数字数据输入流，发送器将数字数据输入流发送到接收机，并且接收机将该流顺序地划分成不同的交错子流，并且稍后组合子流以提供包括原始数字数据输入流的输出。原始数字数据输入流包括多个数据子集，例如字节。每个子组存储在接收器的选定缓冲器中。以预定的旋转顺序选择缓冲器以存储顺序接收的子组。因此，每个缓冲器以定义的顺序接收子组。后来，每个缓冲区按照接收的顺序输出其存储的子组。数据汇编器组装由各种缓冲器输出的子组，重构原始数字输入流。

7. 发明授权

US6084934A Natural throttling of data transfer across asynchronous boundaries 失效
标题翻译：跨越异步边界的数据传输的自然节流
公开(公告)号：US6084934A
公开(公告)日：2000-07-04
申请号：US811776
申请日：1997-03-06
申请人： Enrique Garcia , Adalberto Guillermo Yanes , Juan Antonio Yanes
发明人： Enrique Garcia , Adalberto Guillermo Yanes , Juan Antonio Yanes
IPC分类号： G06F5/06 , H04L7/00 , H04L25/49 , H04L25/38 , H04J3/06
CPC分类号： H04L7/0008 , G06F5/06 , H04L25/4904
摘要： A data transmission system includes a sender and a receiver, both employing different clock rates and a data bus coupled between the sender and the receiver for transmitting signals therebetween. The receiver generates an enable signal from the receiver clock to control data transmission at the sender. The enable signal is a pulse generated at each rising edge of the receiver clock and corresponds to the data transfer rate of the receiver clock. A detector module, located at the sender, receives and captures the asynchronous enable signal and initiates transmission of one data byte for each pulse of the enable signal, thereby automatically adjusting the data transfer rate of the sender to the data transfer rate of the receiver.
摘要翻译：数据传输系统包括发送器和接收器，它们采用不同的时钟速率，耦合在发送器和接收器之间的数据总线用于在它们之间传输信号。接收机从接收器时钟产生使能信号以控制发送器处的数据传输。使能信号是在接收机时钟的每个上升沿产生的脉冲，对应于接收机时钟的数据传送速率。位于发送器处的检测器模块接收并捕获异步使能信号，并启动对使能信号的每个脉冲的一个数据字节的传输，从而自动将发送器的数据传输速率调整到接收机的数据传输速率。

8. 发明授权

US06557087B1 Management of PCI read access to a central resource 失效
标题翻译：管理PCI读取访问中央资源
公开(公告)号：US06557087B1
公开(公告)日：2003-04-29
申请号：US09510505
申请日：2000-02-22
申请人： Russell Lee Ellison , Joseph Smith Hyde, II , Juan Antonio Yanes
发明人： Russell Lee Ellison , Joseph Smith Hyde, II , Juan Antonio Yanes
IPC分类号： G06F1300
CPC分类号： G06F13/4036
摘要： A PCI read access management system and method to manage read access between two agents providing PCI read requests to conduct contiguous read operations to a central resource at a PCI bus. Dual transaction control logic units are each respectively coupled to a separate one of the agents. An arbitration request connection couples the dual transaction control logic units. A PCI read request by one of the agents (e.g., agent A), and recognized by one of the dual transaction control logic units (e.g., unit 1), is signaled to the arbitration request connection, which arbitrates between the transaction control logic units for reserving the PCI bus for the one agent (agent A), and the one transaction control logic unit (unit 1) provides read access to the PCI bus for the one agent (agent A) for the contiguous read operations. The one transaction control logic unit (unit 1) then maintains the reservation until completion of the contiguous read operations.
摘要翻译： PCI读取访问管理系统和方法，用于管理提供PCI读取请求的两个代理之间的读取访问，以在PCI总线上对中央资源执行连续的读取操作。双事务控制逻辑单元各自分别耦合到单独的一个代理。仲裁请求连接耦合双事务控制逻辑单元。一个代理（例如，代理A）的PCI读取请求被双重事务控制逻辑单元（例如，单元1）之一识别，被发送到仲裁请求连接，仲裁请求连接在事务控制逻辑单元用于为一个代理（代理A）预留PCI总线，并且一个事务控制逻辑单元（单元1）为连续的读取操作提供用于一个代理（代理A）的PCI总线的读取访问。一个事务控制逻辑单元（单元1）然后保持预留，直到连续读操作完成。

9. 发明授权

US06530043B1 Write data error checking in a PCI Bus system 失效
标题翻译：在PCI总线系统中写入数据错误检查
公开(公告)号：US06530043B1
公开(公告)日：2003-03-04
申请号：US09522440
申请日：2000-03-09
申请人： Brent Cameron Beardsley , Michael Thomas Benhase , Gregg Steven Lucas , Juan Antonio Yanes
发明人： Brent Cameron Beardsley , Michael Thomas Benhase , Gregg Steven Lucas , Juan Antonio Yanes
IPC分类号： G06F1108
CPC分类号： H04L1/0061 , H04L1/0041 , H04L1/0045
摘要： In a PCI bus system, a method and system check for errors in rite data transferred from a PCI data source across a PCI bus to the PCI bus system, the data comprising a plurality of blocks. Redundancy calculation logic receives the write data across the PCI bus, calculates a check value for each block of the data transferred across the PCI bus, and updating any previously calculated check value with the calculated check value at a storage location of a storage memory. Data path logic is coupled to the PCI bus and to the storage memory, and responds to a unique identifier of a redundancy write command sent subsequent to completion of the transfer of the write data across the PCI interface. The data path logic responds to the write command unique identifier, detecting the updated calculated check value at the storage location of the storage memory. Error check logic coupled to the data path logic determines whether the detected updated calculated check value indicates an error, and upon the detected updated calculated check value indicating an error, signals the error.
摘要翻译：在PCI总线系统中，方法和系统检查从PCI数据源通过PCI总线传输到PCI总线系统的仪表数据中的错误，该数据包括多个块。冗余计算逻辑通过PCI总线接收写入数据，计算通过PCI总线传输的数据的每个块的校验值，并且在存储存储器的存储位置处用计算出的校验值更新任何先前计算的校验值。数据路径逻辑耦合到PCI总线和存储存储器，并且响应在完成跨PCI接口的写入数据传送之后发送的冗余写入命令的唯一标识符。数据路径逻辑响应写入命令唯一标识符，检测在存储存储器的存储位置处更新的计算的检查值。耦合到数据路径逻辑的错误检查逻辑确定检测到的更新的计算的检查值是否指示错误，并且在检测到的更新的指示错误的计算的检查值时，发信号通知错误。

10. 发明授权

US06449678B1 Method and system for multiple read/write transactions across a bridge system 失效
标题翻译：跨桥系统进行多次读/写交易的方法和系统
公开(公告)号：US06449678B1
公开(公告)日：2002-09-10
申请号：US09275470
申请日：1999-03-24
申请人： Gary William Batchelor , Russell Lee Ellison , Carl Evan Jones , Robert Earl Medlin , Belayneh Tafesse , Forrest Lee Wade , Juan Antonio Yanes
发明人： Gary William Batchelor , Russell Lee Ellison , Carl Evan Jones , Robert Earl Medlin , Belayneh Tafesse , Forrest Lee Wade , Juan Antonio Yanes
IPC分类号： G06F1300
CPC分类号： G06F13/4027
摘要： Disclosed is a system for processing read/write transactions from a plurality of agents over a bus. The bridge includes at least one request buffer for each agent in communication with the bridge. The request buffer for an agent buffers transactions originating from that agent. The bridge further includes a return buffer for each agent in communication with the bridge. The return buffer for an agent buffers return data in connection with a transaction. Address translation circuitry is in communication with the bus and request and return buffers. The address translation circuitry locates a request buffer to queue the transaction, such that a transaction is stored in the request buffer corresponding to the agent that originated the transaction. Further, the address translation circuitry stores read return data for a read transaction in the return buffer corresponding to the agent originating the transaction.
摘要翻译：公开了一种用于通过总线处理来自多个代理的读/写交易的系统。该桥包括与桥接通信的每个代理的至少一个请求缓冲器。代理的请求缓冲区缓冲来自该代理的事务。桥接器还包括与桥接器通信的每个代理的返回缓冲器。代理缓冲区缓冲区返回与事务相关的数据。地址转换电路与总线通信，请求和返回缓冲器。地址转换电路定位请求缓冲器以对事务进行排队，使得事务存储在与发起事务的代理相对应的请求缓冲器中。此外，地址转换电路将用于读取事务的读取返回数据存储在与发起事务的代理相对应的返回缓冲器中。

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