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1. 发明授权

US06747656B2 Image processing apparatus and method of the same, and display apparatus using the image processing apparatus 失效
标题翻译：图像处理装置及其方法以及使用该图像处理装置的显示装置
公开(公告)号：US06747656B2
公开(公告)日：2004-06-08
申请号：US09826084
申请日：2001-04-04
申请人： Shinichi Matsushita
发明人： Shinichi Matsushita
IPC分类号： G06F13372
CPC分类号： G09G5/001 , G09G5/391 , G09G5/395 , G09G2320/0261 , G09G2340/0407 , H04N5/21 , H04N7/0122
摘要： An image processing apparatus and method, and a display apparatus capable of preventing field tearing caused by memory overrun even when performing a read operation and a write operation of input/output images with respect to a single image memory, wherein a system microcomputer (MC) is used for generating and supplying output delay data for delaying an image output timing based on the write speed to the image memory, the read speed from the image memory, and the read area so that the timing of access to the read end address address and the timing for performing a write operation to the same address match and of a scan converter for receiving the output delay data supplied by the system MC and delaying the image output timing so that the timing of access to the read end address and the timing for performing a write operation to the same address match.
摘要翻译：一种图像处理装置和方法以及即使当对单个图像存储器执行输入/输出图像的读取操作和写入操作时，也能够防止存储器超限引起的场撕裂，其中系统微计算机（MC）用于产生和提供输出延迟数据，用于基于图像存储器的写入速度延迟图像输出定时，来自图像存储器的读取速度和读取区域，使得访问读取结束地址地址的时间和用于执行对相同地址匹配的写操作的定时和用于接收由系统MC提供的输出延迟数据的扫描转换器，并延迟图像输出定时，使得访问读结束地址的定时和执行定时对同一地址进行写操作匹配。

2. 发明授权

US06515672B1 Managing prefetching from a data buffer 失效
标题翻译：从数据缓冲区管理预取
公开(公告)号：US06515672B1
公开(公告)日：2003-02-04
申请号：US09470971
申请日：1999-12-23
申请人： Gad S. Sheaffer , Roman Surgutchik , Oded Lempel
发明人： Gad S. Sheaffer , Roman Surgutchik , Oded Lempel
IPC分类号： G06F13372
CPC分类号： G09G3/3644 , G09G5/395 , G09G2360/12
摘要： A method and apparatus for preventing over-prefetching from a buffer receives an address of a last data set item in a data buffer, and reads data from the data buffer into a read streamer buffer starting at a data buffer start address until the address of said last item.
摘要翻译：用于防止从缓冲器过度预取的方法和装置接收数据缓冲器中的最后数据集项目的地址，并且从数据缓冲器起始地址开始将数据从数据缓冲器读取到读数据流缓冲器中，直到所述最后一项。

3. 发明授权

US06381658B1 Apparatus and method to precisely position packets for a queue based memory controller 失效
标题翻译：为基于队列的存储器控制器精确定位数据包的装置和方法
公开(公告)号：US06381658B1
公开(公告)日：2002-04-30
申请号：US09474568
申请日：1999-12-29
申请人： Muthukumar P. Swaminathan
发明人： Muthukumar P. Swaminathan
IPC分类号： G06F13372
CPC分类号： G06F13/1642 , G06F13/1689
摘要： Disclosed is an apparatus, method, and system to precisely position packets for a queue based memory controller. The memory controller operates with a queue having a plurality of queue positions. A timestamp logic circuit in communication with the memory controller designates scheduled times for each queue position. The memory controller may schedule a packet for a queue position at a scheduled time. The timestamp logic circuit utilizes a plurality of bubble adders to add bubbles to queue positions to adjust the scheduled time for a packet to precisely position the packet.
摘要翻译：公开了一种用于精确定位用于基于队列的存储器控制器的分组的装置，方法和系统。存储器控制器具有具有多个队列位置的队列操作。与存储器控制器通信的时间戳逻辑电路指定每个队列位置的调度时间。存储器控制器可以在预定时间为队列位置调度分组。时间戳逻辑电路利用多个气泡加法器将气泡添加到队列位置以调整分组的调度时间以精确地定位分组。

4. 发明授权

US06754745B1 Method and apparatus for distributing a clock in a network 有权
标题翻译：用于在网络中分配时钟的方法和装置
公开(公告)号：US06754745B1
公开(公告)日：2004-06-22
申请号：US09370077
申请日：1999-08-06
申请人： Alexander Horvath , Alfred Abkarian , Richard Haydt
发明人： Alexander Horvath , Alfred Abkarian , Richard Haydt
IPC分类号： G06F13372
CPC分类号： H04J3/0691 , H04J3/0647 , H04J3/0688 , H04Q2213/13003 , H04Q2213/13214 , H04Q2213/1336
摘要： A network system is described having multiple network components. The multiple network components include at least one central office (CO) and at least one customer premise equipment (CPE) coupled to the at least one CO. One of either the CO or CPE captures a clock, generates a reference clock, and sends the clock to the remainder of the multiple network components to ensure synchronous operation.
摘要翻译：描述具有多个网络组件的网络系统。所述多个网络组件包括至少一个中心局（CO）和至少一个与所述至少一个CO耦合的客户驻地设备（CPE），所述CO或CPE中的一个捕获时钟，生成参考时钟，并发送时钟到多个网络组件的其余部分，以确保同步操作。

5. 发明授权

US06490644B1 Limiting write data fracturing in PCI bus systems 失效
$Limiting write data fracturing in PCI bus systems$
标题翻译：限制PCI总线系统中的写入数据压缩
公开(公告)号：US06490644B1
公开(公告)日：2002-12-03
申请号：US09521387
申请日：2000-03-08
申请人： Joseph Smith Hyde, II , Robert Earl Medlin , Juan Antonio Yanes
发明人： Joseph Smith Hyde, II , Robert Earl Medlin , Juan Antonio Yanes
IPC分类号： G06F13372
CPC分类号： G06F13/362
摘要： A system for limiting fracturing of write data by a PCI bus adapter which queues operation commands in a command queue. The write data is in the form of bursts comprising a plurality of contiguous words. Fracture detection logic senses fracturing of the write data. A bus arbiter is responsive to the sensed fracturing of write data by the target, and blocks access to the PCI bus. Queue level detection logic is employed, subsequent to the blocking, to monitor completion of the queued operation commands of the PCI bus target. The bus arbiter is then responsive to the queue level detection logic indicating that the PCI bus target has completed enough operations that a predetermined number (such as one) of the operation commands remain queued at its command queue, and grants access to the PCI bus to complete the burst write operation without fracturing.
摘要翻译：用于通过PCI总线适配器限制写数据压缩的系统，其将命令队列中的操作命令排队。写数据是包括多个连续字的突发的形式。断裂检测逻辑检测写入数据的压裂。总线仲裁器响应于由目标感测到的写入数据的压缩，并阻止对PCI总线的访问。在阻塞之后采用队列级检测逻辑来监视PCI总线目标的排队操作命令的完成。总线仲裁器然后响应于队列等级检测逻辑，指示PCI总线目标已经完成足够的操作，其中预定数量（诸如一个）操作命令在其命令队列中保持排队，并且授予对PCI总线的访问完成突发写入操作而不破裂。

6. 发明授权

US06336156B1 Increased speed initialization using dynamic slot allocation 有权
标题翻译：使用动态时隙分配提高速度初始化
公开(公告)号：US06336156B1
公开(公告)日：2002-01-01
申请号：US09296551
申请日：1999-04-22
申请人： John Chiang
发明人： John Chiang
IPC分类号： G06F13372
CPC分类号： H04L47/6215 , H04L47/50 , H04L49/205 , H04L49/30 , H04L49/3027 , H04L49/351 , H04L49/354
摘要： A method and apparatus are disclosed for decreasing the amount of time required to initialize a multiport switch. An address table stores addresses of source and destination stations that transmit and receive data frames to and from the multiport switch. Initialization logic is used for constructing and initializing the address table upon startup of the multiport switch. During normal operation of the multiport switch, a scheduler functions to allocate address table access bandwidth to various components of the multiport switch. Upon startup of the multiport switch, the scheduler increases the amount of bandwidth allocated to the initialization logic. The amount of bandwidth allocated to the initialization logic is decreased once the multiport switch is initialized.
摘要翻译：公开了一种用于减少初始化多端口开关所需的时间量的方法和装置。地址表存储与多端口交换机发送和接收数据帧的源站和目的站的地址。初始化逻辑用于在启动多端口交换机时构建和初始化地址表。在多端口交换机的正常操作期间，调度器用于将地址表访问带宽分配给多端口交换机的各种组件。在多端口交换机启动时，调度器增加分配给初始化逻辑的带宽量。一旦多端口开关被初始化，分配给初始化逻辑的带宽就会减少。

7. 发明授权

US06833833B1 Feedback path for video benchmark testing 失效
标题翻译：视频基准测试的反馈路径
公开(公告)号：US06833833B1
公开(公告)日：2004-12-21
申请号：US09671515
申请日：2000-09-26
申请人： Louis A. Lippincott
发明人： Louis A. Lippincott
IPC分类号： G06F13372
CPC分类号： H04N17/00 , G09G2340/125
摘要： A feedback path to the processor for a video signal in a computer. The video image data is not normally subjected to benchmark testing because it would make it susceptible to illegal copying. The digital video output signal is sent back to the processor one pixel at a time, with a delay between pixels equivalent to one line time. The result is that the pixel feed is so slow that digital copying is impractical. A lockout timer allows the pixel data to be sent to the processor only at intervals.
摘要翻译：计算机中视频信号到处理器的反馈路径。视频图像数据通常不会进行基准测试，因为它会使其易于非法复制。数字视频输出信号一次发送回处理器一个像素，相当于一行时间的像素之间的延迟。结果是像素馈送太慢，数字复制是不切实际的。锁定定时器允许像素数据间隔发送到处理器。

8. 发明授权

US06742064B2 Programmable throttle circuit for each control device of a processing system 失效
标题翻译：可编程节气门电路，用于处理系统的每个控制装置
公开(公告)号：US06742064B2
公开(公告)日：2004-05-25
申请号：US09829019
申请日：2001-04-09
申请人： Arthur Howard Waldie , Robert Ward James
发明人： Arthur Howard Waldie , Robert Ward James
IPC分类号： G06F13372
CPC分类号： G06F13/364
摘要： A processing system comprises: a shared system resource; a plurality of control devices, each assignable with a task having a predetermined maximum time to complete, the control devices time sharing the system resource in the process of performing their assigned tasks in accordance with a predetermined sequence; and an arbiter circuit for regulating access of said control devices to the system resource. Each control device includes a throttle circuit coupled to the arbiter circuit and individually programmable to control in cooperation with the arbiter circuit utilization of the system resource by the corresponding control device so that each control device may perform its task within the predetermined maximum completion time thereof.
摘要翻译：处理系统包括：共享系统资源; 多个控制装置，每个控制装置可以分配具有预定最大时间的任务来完成，控制装置根据预定的顺序在执行其分配的任务的过程中共享系统资源; 以及用于调节所述控制装置对系统资源的访问的仲裁电路。每个控制装置包括一个连接到仲裁器电路的节流电路，并可单独编程，以便与相应的控制装置的系统资源的仲裁器电路利用相配合地进行控制，从而每个控制装置可以在预定的最大完成时间内执行其任务。

9. 发明授权

US06535940B1 System and method for fast data transfers in an electronic network 有权
标题翻译：用于电子网络快速数据传输的系统和方法
公开(公告)号：US06535940B1
公开(公告)日：2003-03-18
申请号：US09363086
申请日：1999-07-28
申请人： Jung-Jen Liu , Scott Smyers , Bruce A. Fairman , Steve Pham
发明人： Jung-Jen Liu , Scott Smyers , Bruce A. Fairman , Steve Pham
IPC分类号： G06F13372
CPC分类号： H04L12/40058 , G06F9/30032 , G06F9/3879 , H04L12/40117
摘要： A system and method for fast data transfers in an electronic network comprises a data transfer engine configured to independently execute data transfer instructions and a processor configured to forward the data transfer instructions to the data transfer engine. The data transfer engine preferably executes the data transfer instructions while the processor proceeds to execute a next instruction. The data transfer engine includes a transmit engine that executes transmit transfer instructions and a receive engine that executes receive transfer instructions. The transmit engine and the receive engine operate independently and thus may operate concurrently.
摘要翻译：一种用于电子网络中快速数据传输的系统和方法，包括被配置为独立地执行数据传输指令的数据传输引擎和被配置为将数据传输指令转发到数据传输引擎的处理器。数据传输引擎优选地在处理器执行下一条指令时执行数据传输指令。数据传输引擎包括执行发送传送指令的发送引擎和执行接收转移指令的接收引擎。传输引擎和接收引擎独立运行，因此可以同时运行。

10. 发明授权

US06657634B1 Dynamic graphics and/or video memory power reducing circuit and method 有权
标题翻译：动态图形和/或视频存储器功耗的降低电路及方法
公开(公告)号：US06657634B1
公开(公告)日：2003-12-02
申请号：US09257291
申请日：1999-02-25
申请人： David E. Sinclair , Eric Young
发明人： David E. Sinclair , Eric Young
IPC分类号： G06F13372
CPC分类号： G06F1/3218 , G06F1/3265 , G06F13/1668 , G09G5/363 , G09G2330/022 , Y02D10/153 , Y02D50/20
摘要： An apparatus and method dynamically controls the graphics and/or video memory power dynamically during idle periods of the memory interface during active system modes. In one embodiment, a memory request detector generates memory request indication data, such as data representing whether memory requests have been received within a predetermined time, based on detection of graphics and/or video memory requests during an active mode of the display system operation. A dynamic activity based memory power controller analyzes the memory request indication data and controls the power consumption of the graphics and/or video memory based on whether memory requests are detected.
摘要翻译：一种装置和方法在主动系统模式期间在存储器接口的空闲周期期间动态地控制图形和/或视频存储器功率。在一个实施例中，存储器请求检测器基于在显示系统操作的活动模式期间的图形和/或视频存储器请求的检测，产生存储器请求指示数据，诸如表示在预定时间内是否已经接收到存储器请求的数据。基于动态活动的存储器功率控制器分析存储器请求指示数据，并且基于是否检测到存储器请求来控制图形和/或视频存储器的功耗。

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