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    • 1. 发明授权
    • Limiting write data fracturing in PCI bus systems
    • 限制PCI总线系统中的写入数据压缩
    • US06490644B1
    • 2002-12-03
    • US09521387
    • 2000-03-08
    • Joseph Smith Hyde, IIRobert Earl MedlinJuan Antonio Yanes
    • Joseph Smith Hyde, IIRobert Earl MedlinJuan Antonio Yanes
    • G06F13372
    • G06F13/362
    • A system for limiting fracturing of write data by a PCI bus adapter which queues operation commands in a command queue. The write data is in the form of bursts comprising a plurality of contiguous words. Fracture detection logic senses fracturing of the write data. A bus arbiter is responsive to the sensed fracturing of write data by the target, and blocks access to the PCI bus. Queue level detection logic is employed, subsequent to the blocking, to monitor completion of the queued operation commands of the PCI bus target. The bus arbiter is then responsive to the queue level detection logic indicating that the PCI bus target has completed enough operations that a predetermined number (such as one) of the operation commands remain queued at its command queue, and grants access to the PCI bus to complete the burst write operation without fracturing.
    • 用于通过PCI总线适配器限制写数据压缩的系统,其将命令队列中的操作命令排队。 写数据是包括多个连续字的突发的形式。 断裂检测逻辑检测写入数据的压裂。 总线仲裁器响应于由目标感测到的写入数据的压缩,并阻止对PCI总线的访问。 在阻塞之后采用队列级检测逻辑来监视PCI总线目标的排队操作命令的完成。 总线仲裁器然后响应于队列等级检测逻辑,指示PCI总线目标已经完成足够的操作,其中预定数量(诸如一个)操作命令在其命令队列中保持排队,并且授予对PCI总线的访问 完成突发写入操作而不破裂。
    • 2. 发明授权
    • Data length control of access to a data bus
    • 访问数据总线的数据长度控制
    • US06636913B1
    • 2003-10-21
    • US09551861
    • 2000-04-18
    • Gary William BatchelorMichael Thomas BenhaseJoseph Smith Hyde, IIRobert Earl MedlinJuan Antonio Yanes
    • Gary William BatchelorMichael Thomas BenhaseJoseph Smith Hyde, IIRobert Earl MedlinJuan Antonio Yanes
    • G06F1300
    • G06F13/126
    • A method and system for controlling access to a bus for transferring data in the form of multibyte data streams. Data transfer agents are coupled to and request access to the bus to transfer data thereon. The system for controlling access to the bus comprises a bus arbiter responsive to the access requests of the data transfer agents, granting access to the bus to one data transfer agent at a time. A data length counter accumulates, during the grant of access, signals indicating the length of the data transferred between the bus and the data transfer agent. The data length counter indicates completion of the transfer of a predetermined length of data, and bus arbiter logic responds to the data length counter indicating the transfer completion, causing the bus arbiter to terminate the grant of access to the data transfer agent. The control of access to the bus is thus based on the precise measurement of the length of the transferred data, rather than on timers.
    • 一种用于控制访问总线以用于以多字节数据流的形式传送数据的方法和系统。 数据传输代理被耦合到请求访问总线以在其上传送数据。 用于控制对总线的访问的系统包括响应于数据传输代理的访问请求的总线仲裁器,一次授予对一个数据传输代理的总线访问。 在授权访问期间,数据长度计数器累积指示在总线和数据传送代理之间传送的数据的长度的信号。 数据长度计数器指示传输预定长度的数据的完成,并且总线仲裁器逻辑响应指示传送完成的数据长度计数器,导致总线仲裁器终止对数据传输代理的访问许可。 因此,对总线访问的控制基于精确测量传输数据的长度,而不是基于定时器。
    • 3. 发明授权
    • Management of PCI read access to a central resource
    • 管理PCI读取访问中央资源
    • US06557087B1
    • 2003-04-29
    • US09510505
    • 2000-02-22
    • Russell Lee EllisonJoseph Smith Hyde, IIJuan Antonio Yanes
    • Russell Lee EllisonJoseph Smith Hyde, IIJuan Antonio Yanes
    • G06F1300
    • G06F13/4036
    • A PCI read access management system and method to manage read access between two agents providing PCI read requests to conduct contiguous read operations to a central resource at a PCI bus. Dual transaction control logic units are each respectively coupled to a separate one of the agents. An arbitration request connection couples the dual transaction control logic units. A PCI read request by one of the agents (e.g., agent A), and recognized by one of the dual transaction control logic units (e.g., unit 1), is signaled to the arbitration request connection, which arbitrates between the transaction control logic units for reserving the PCI bus for the one agent (agent A), and the one transaction control logic unit (unit 1) provides read access to the PCI bus for the one agent (agent A) for the contiguous read operations. The one transaction control logic unit (unit 1) then maintains the reservation until completion of the contiguous read operations.
    • PCI读取访问管理系统和方法,用于管理提供PCI读取请求的两个代理之间的读取访问,以在PCI总线上对中央资源执行连续的读取操作。 双事务控制逻辑单元各自分别耦合到单独的一个代理。 仲裁请求连接耦合双事务控制逻辑单元。 一个代理(例如,代理A)的PCI读取请求被双重事务控制逻辑单元(例如,单元1)之一识别,被发送到仲裁请求连接,仲裁请求连接在事务控制逻辑单元 用于为一个代理(代理A)预留PCI总线,并且一个事务控制逻辑单元(单元1)为连续的读取操作提供用于一个代理(代理A)的PCI总线的读取访问。 一个事务控制逻辑单元(单元1)然后保持预留,直到连续读操作完成。
    • 5. 发明授权
    • Data migration to high speed storage in accordance with I/O activity over time
    • 根据I / O活动随时间的推移,数据迁移到高速存储
    • US08230131B2
    • 2012-07-24
    • US12559362
    • 2009-09-14
    • Joseph Smith Hyde, IIBruce McNutt
    • Joseph Smith Hyde, IIBruce McNutt
    • G06F3/00G06F12/00G06F13/00
    • G06F3/0649G06F3/0613G06F3/0685
    • Methods, controllers for data storage, data storage systems, and computer program products are directed to migrating data after the initial placement of the data in data storage entities having higher speed and in other data storage. Steps of a method to migrate data to the higher speed data storage are (1) identifying at least one group of data having had at least one I/O activity in each of a plurality of intervals of time, occurring over a string of multiple intervals of time, wherein the I/O activity is with respect to the other data storage from which data is to be migrated. The time for each of the multiple intervals is selected such that bursts of the I/O activity are likely to be contained in one interval. (2) The identified group of data is classified to the higher speed data storage and migrated.
    • 用于数据存储,数据存储系统和计算机程序产品的控制器用于在将数据初始放置在具有较高速度的数据存储实体中并在其它数据存储中之后迁移数据。 将数据迁移到更高速度数据存储的方法的步骤是(1)识别至少一组在多个时间间隔中的每一个中具有至少一个I / O活动的数据,这些数据在多个间隔的串上发生 的时间,其中I / O活动是相对于要迁移数据的其他数据存储。 选择多个间隔中的每一个的时间,使得I / O活动的突发可能包含在一个间隔中。 (2)将所识别的数据组分类为更高速度的数据存储并进行迁移。