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1. 发明授权

US06535937B1 Write command verification across a PCI bus system 失效
标题翻译：通过PCI总线系统编写命令验证
公开(公告)号：US06535937B1
公开(公告)日：2003-03-18
申请号：US09503911
申请日：2000-02-15
申请人： Brent Cameron Beardsley , Michael Thomas Benhase , Russell Lee Ellison , Gregg Steven Lucas , Juan Antonio Yanes
发明人： Brent Cameron Beardsley , Michael Thomas Benhase , Russell Lee Ellison , Gregg Steven Lucas , Juan Antonio Yanes
IPC分类号： G06F1338
CPC分类号： G06F13/4221 , G06F13/4027
摘要： A method and system to verify the passage of one or more write commands sent from an originating location through a PCI bus system. An addressable data storage is located substantially at the end of the PCI bus system with respect to the originating location. A write command is sent by the originator subsequent to the one or more write commands, to a predetermined special end location address identifying the addressable storage. The command is accompanied by data comprising a predetermined special return address at the originating location. The PCI bus system transmits the write commands on a FIFO basis, so the one or more write commands precede the subsequently sent write command. Logic senses the subsequently sent write command, and responds to the command, sending a return echo write command to the predetermined special return address. The returning echo write command verifies the passage of the write commands and data through the PCI bus system. The predetermined special end location address is the key to identify the subsequently sent write command.
摘要翻译：一种用于验证从始发位置通过PCI总线系统发送的一个或多个写入命令的通过的方法和系统。相对于始发位置，可寻址数据存储器基本上位于PCI总线系统的末端。写命令由发起者在一个或多个写入命令之后发送到标识可寻址存储器的预定特殊结束位置地址。该命令伴随着在始发位置处包括预定的特殊返回地址的数据。 PCI总线系统以FIFO为基础发送写命令，因此一个或多个写命令先于随后发送的写命令。逻辑检测随后发送的写入命令，并响应该命令，向预定的特殊返回地址发送返回回显写命令。返回的回写写命令通过PCI总线系统验证写命令和数据的通过。预定的特殊终端位置地址是识别随后发送的写命令的关键。

2. 发明授权

US06530043B1 Write data error checking in a PCI Bus system 失效
标题翻译：在PCI总线系统中写入数据错误检查
公开(公告)号：US06530043B1
公开(公告)日：2003-03-04
申请号：US09522440
申请日：2000-03-09
申请人： Brent Cameron Beardsley , Michael Thomas Benhase , Gregg Steven Lucas , Juan Antonio Yanes
发明人： Brent Cameron Beardsley , Michael Thomas Benhase , Gregg Steven Lucas , Juan Antonio Yanes
IPC分类号： G06F1108
CPC分类号： H04L1/0061 , H04L1/0041 , H04L1/0045
摘要： In a PCI bus system, a method and system check for errors in rite data transferred from a PCI data source across a PCI bus to the PCI bus system, the data comprising a plurality of blocks. Redundancy calculation logic receives the write data across the PCI bus, calculates a check value for each block of the data transferred across the PCI bus, and updating any previously calculated check value with the calculated check value at a storage location of a storage memory. Data path logic is coupled to the PCI bus and to the storage memory, and responds to a unique identifier of a redundancy write command sent subsequent to completion of the transfer of the write data across the PCI interface. The data path logic responds to the write command unique identifier, detecting the updated calculated check value at the storage location of the storage memory. Error check logic coupled to the data path logic determines whether the detected updated calculated check value indicates an error, and upon the detected updated calculated check value indicating an error, signals the error.
摘要翻译：在PCI总线系统中，方法和系统检查从PCI数据源通过PCI总线传输到PCI总线系统的仪表数据中的错误，该数据包括多个块。冗余计算逻辑通过PCI总线接收写入数据，计算通过PCI总线传输的数据的每个块的校验值，并且在存储存储器的存储位置处用计算出的校验值更新任何先前计算的校验值。数据路径逻辑耦合到PCI总线和存储存储器，并且响应在完成跨PCI接口的写入数据传送之后发送的冗余写入命令的唯一标识符。数据路径逻辑响应写入命令唯一标识符，检测在存储存储器的存储位置处更新的计算的检查值。耦合到数据路径逻辑的错误检查逻辑确定检测到的更新的计算的检查值是否指示错误，并且在检测到的更新的指示错误的计算的检查值时，发信号通知错误。

3. 发明授权

US06246726B1 High speed digital data transmission by separately clocking and recombining interleaved data subgroups 失效
标题翻译：通过单独计时和重组交错数据子组实现高速数字数据传输
公开(公告)号：US06246726B1
公开(公告)日：2001-06-12
申请号：US09514025
申请日：2000-02-25
申请人： Enrique Garcia , Gregg Steven Lucas , Juan Antonio Yanes
发明人： Enrique Garcia , Gregg Steven Lucas , Juan Antonio Yanes
IPC分类号： H04L2704
CPC分类号： H04L7/0008
摘要： To exchange a digital data input stream, a transmitter sends the digital data input stream to a receiver, and the receiver sequentially divides the stream into different interleaved substreams and later combines the substreams to provide an output including the original digital data input stream. The original digital data input stream includes multiple subgroups of data, such as bytes. Each subgroup is stored in a selected buffer of the receiver. Buffers are selected in a predetermined order of rotation to store sequentially received subgroups. Thus, each buffer receives subgroups in a defined order. Later, each buffer outputs its stored subgroups in the same order as received. A data assembler assembles the subgroups output by the various buffers, reconstructing the original digital input stream.
摘要翻译：为了交换数字数据输入流，发送器将数字数据输入流发送到接收机，并且接收机将该流顺序地划分成不同的交错子流，并且稍后组合子流以提供包括原始数字数据输入流的输出。原始数字数据输入流包括多个数据子集，例如字节。每个子组存储在接收器的选定缓冲器中。以预定的旋转顺序选择缓冲器以存储顺序接收的子组。因此，每个缓冲器以定义的顺序接收子组。后来，每个缓冲区按照接收的顺序输出其存储的子组。数据汇编器组装由各种缓冲器输出的子组，重构原始数字输入流。

4. 发明授权

US6038613A Prefetching and storing device work information from multiple data storage devices 失效
标题翻译：从多个数据存储设备预取和存储设备工作信息
公开(公告)号：US6038613A
公开(公告)日：2000-03-14
申请号：US971085
申请日：1997-11-14
申请人： Enrique Q Garcia , Gregg Steven Lucas , James Richard Pollock , Juan Antonio Yanes
发明人： Enrique Q Garcia , Gregg Steven Lucas , James Richard Pollock , Juan Antonio Yanes
IPC分类号： G06F3/06 , G06F13/12 , G06F13/00
CPC分类号： G06F3/0607 , G06F13/122 , G06F3/0632 , G06F3/0653 , G06F3/0674
摘要： A device controller is described within a data storage system for pre-fetching device work information from multiple data storage devices, and accumulating the device work information to immediately respond to a subsequent device poll command from a storage controller. The device controller includes a device receiver to receive the device poll command, a device transmitter to transmit a response to the device poll command, a device information register for storing the pre-fetched device work information for each data storage device, and a sequencer for periodically pre-fetching the device work information from each data storage device. The sequencer pre-fetches such information by verifying that no device subsystem command from the storage controller is pending in the device receiver, then issuing a background poll command to a selected device to query the device for its device work information, and storing the device work information in the device information register. The device controller can then immediately respond to a subsequent device poll command issued from the storage controller by copying the device work information from the device information register to the device transmitter.
摘要翻译：在数据存储系统内描述设备控制器，用于从多个数据存储设备预取设备工作信息，并累积设备工作信息以立即响应来自存储控制器的后续设备轮询命令。设备控制器包括接收设备轮询命令的设备接收器，用于发送对设备轮询命令的响应的设备发送器，用于存储每个数据存储设备的预取设备工作信息的设备信息寄存器，以及用于定期从每个数据存储设备预取设备工作信息。定序器通过验证设备接收器中没有来自存储控制器的设备子系统命令等待处理，然后向所选设备发出后台轮询命令来查询设备的设备工作信息，并存储设备工作，从而预取这些信息设备信息寄存器中的信息。然后，设备控制器可以通过将设备工作信息从设备信息寄存器复制到设备发送器来立即响应从存储控制器发出的后续设备轮询命令。

5. 发明授权

US5928375A Method for enhancing data transmission in parity based data processing systems 失效
标题翻译：在基于奇偶校验的数据处理系统中增强数据传输的方法
公开(公告)号：US5928375A
公开(公告)日：1999-07-27
申请号：US780570
申请日：1997-01-08
申请人： Gregg Steven Lucas , Juan Antonio Yanes
发明人： Gregg Steven Lucas , Juan Antonio Yanes
IPC分类号： G06F13/42 , G06F13/00 , H03M13/09 , H04L1/00 , H04L7/00 , G06F11/10 , H03M13/00
CPC分类号： H04L1/0057 , H03M13/09
摘要： A data transfer system providing parity uses a method and apparatus for transmitting a data clocking signal in a parity bit location along a data bus to latch an accompanying data byte at a receiving device. A transmitting device, coupled to the receiving device through the data bus, generates a data clock signal and latches the clock signal into the parity bit location of the data bus. The clock signal and data byte are then transmitted along the data bus to the receiving device. The receiving device uses the clock signal to latch the data byte from the data bus. Thus, the data transfer system uses the data clock signal transmitted in the parity bit location of the data bus to validate and synchronize the accompanying data byte at the receiving device.
摘要翻译：提供奇偶校验的数据传送系统使用方法和装置，用于沿着数据总线在奇偶位位置发送数据时钟信号，以在接收装置处锁存伴随的数据字节。通过数据总线耦合到接收装置的发送装置产生数据时钟信号并将时钟信号锁存到数据总线的奇偶校验位。然后，时钟信号和数据字节沿数据总线发送到接收装置。接收设备使用时钟信号来锁存数据总线上的数据字节。因此，数据传输系统使用在数据总线的奇偶校验位位置中发送的数据时钟信号来验证并同步接收设备附带的数据字节。

6. 发明授权

US6091783A High speed digital data transmission by separately clocking and recombining interleaved data subgroups 失效
标题翻译：通过单独计时和重组交错数据子组实现高速数字数据传输
公开(公告)号：US6091783A
公开(公告)日：2000-07-18
申请号：US846517
申请日：1997-04-25
申请人： Enrique Garcia , Gregg Steven Lucas , Juan Antonio Yanes
发明人： Enrique Garcia , Gregg Steven Lucas , Juan Antonio Yanes
IPC分类号： G06F5/06 , G06F5/16 , H04L7/00 , H04L27/04
CPC分类号： H04L7/0008
摘要： To exchange a digital data input stream, a transmitter sends the digital data input stream to a receiver, and the receiver sequentially divides the stream into different interleaved substreams and later combines the substreams to provide an output including the original digital data input stream. The original digital data input stream includes multiple subgroups of data, such as bytes. Each subgroup is stored in a selected buffer of the receiver. Buffers are selected in a predetermined order of rotation to store sequentially received subgroups. Thus, each buffer receives subgroups in a defined order. Later, each buffer outputs its stored subgroups in the same order as received. A data assembler assembles the subgroups output by the various buffers, reconstructing the original digital input stream.
摘要翻译：为了交换数字数据输入流，发送器将数字数据输入流发送到接收机，并且接收机将该流顺序地划分成不同的交错子流，并且稍后组合子流以提供包括原始数字数据输入流的输出。原始数字数据输入流包括多个数据子集，例如字节。每个子组存储在接收器的选定缓冲器中。以预定的旋转顺序选择缓冲器以存储顺序接收的子组。因此，每个缓冲器以定义的顺序接收子组。后来，每个缓冲区按照接收的顺序输出其存储的子组。数据汇编器组装由各种缓冲器输出的子组，重构原始数字输入流。

7. 发明授权

US6085285A Intermixing different devices along a single data communication link by placing a strobe signal in a parity bit slot 失效
标题翻译：通过将奇偶校验位插槽中的选通信号置于单个数据通信链路上来混合不同的器件
公开(公告)号：US6085285A
公开(公告)日：2000-07-04
申请号：US969842
申请日：1997-11-13
申请人： Gregg Steven Lucas , Juan Antonio Yanes
发明人： Gregg Steven Lucas , Juan Antonio Yanes
IPC分类号： G06F13/00 , G11C7/00
CPC分类号： G06F13/423
摘要： A data storage system is described which allows data storage devices with different characteristics, such as differing data rates and transfer speeds, to be connected, and intermixed, along a single data and communication link. The data storage system comprises a storage controller, a first data storage device, a second data storage device, and a data and communication link coupled therebetween. The storage controller transfers data to and from the first data storage device using data locations within the data and communication link to transfer a data byte, a parity location to transfer the associated parity bit, and a communication signal location to transfer a data clocking signal. The storage controller further transfers data to and from the second data storage device using the data locations to transfer a data byte and the parity location to transfer a data clocking, or a data strobe, signal. The storage controller also provides cyclic redundancy checking (CRC) to detect data transmission errors to the second device type, since the parity bit is no longer used to detect these errors.
摘要翻译：描述了一种数据存储系统，其允许具有不同特征的数据存储设备，诸如不同的数据速率和传送速度，沿着单个数据和通信链路连接和混合。数据存储系统包括存储控制器，第一数据存储设备，第二数据存储设备以及耦合在其间的数据和通信链路。存储控制器使用数据和通信链路内的数据位置将数据传送到第一数据存储设备和/或从第一数据存储设备传送数据字节，用于传送相关奇偶校验位的奇偶校验位置，以及传送数据时钟信号的通信信号位置。存储控制器还使用数据位置将数据传送到第二数据存储设备和从第二数据存储设备传送数据字节和奇偶校验位置以传送数据时钟或数据选通信号。存储控制器还提供循环冗余校验（CRC）以检测到第二设备类型的数据传输错误，因为奇偶校验位不再用于检测这些错误。

8. 发明授权

US07020809B2 System and method for utilizing spare bandwidth to provide data integrity over a bus 有权
标题翻译：利用备用带宽在总线上提供数据完整性的系统和方法
公开(公告)号：US07020809B2
公开(公告)日：2006-03-28
申请号：US10255040
申请日：2002-09-25
申请人： Yvonne Hanson Kleppel , Russell Lee Ellison , Enrique Garcia , Rajendrasinh Banesinh Jadeja , Gregg Steven Lucas , Robert Earl Medlin
发明人： Yvonne Hanson Kleppel , Russell Lee Ellison , Enrique Garcia , Rajendrasinh Banesinh Jadeja , Gregg Steven Lucas , Robert Earl Medlin
IPC分类号： G06F11/00
CPC分类号： H04L12/4013 , H04L12/403 , H04L69/40
摘要： A system and method for verifying integrity of data signals communicated from a data transmit device to a receive device over a communications channel of limited bandwidth. The method comprising steps of: a) detecting instances of idle data transmit activity at the transmit device; b) accumulating data integrity information for data transmitted over the communication channel between detected idle transmit instances, the accumulating being performed by data integrity verifier devices at both transmit and receive devices; c) communicating accumulated data integrity information for data transmitted since a last detected idle data transmit instance during a current detected idle data transmit instance; and, d) verifying accumulated data integrity information communicated over the channel at the receiver device. The system and method of the invention may be used to provide intermediate data integrity checks when communication of packets belonging to a stream is interrupted without compromising bandwidth utilization. Moreover, the system and method of the invention may be used to provide data integrity verification for data communicated over two or more communications channels between instances of detected idle transmit states.
摘要翻译：一种用于验证通过有限带宽的通信信道从数据发送设备传送到接收设备的数据信号的完整性的系统和方法。该方法包括以下步骤：a）检测发送设备处的空闲数据发送活动的实例; b）累积针对在所检测到的空闲发送实例之间通过通信信道发送的数据的数据完整性信息，所述累积由数据完整性验证器在发送和接收设备两者执行; c）在当前检测到的空闲数据发送实例期间，传送从上次检测到的空闲数据发送实例以来发送的数据的累积数据完整性信息; 以及d）验证在所述接收机设备处通过所述信道传送的累积数据完整性信息。当属于流的分组的通信被中断而不影响带宽利用时，本发明的系统和方法可用于提供中间数据完整性检查。此外，本发明的系统和方法可以用于为在检测到的空闲发送状态的实例之间的两个或多个通信信道上传送的数据提供数据完整性验证。

9. 发明授权

US08856563B2 Remote power down control of a device 有权
标题翻译：远程关闭设备的掉电控制
公开(公告)号：US08856563B2
公开(公告)日：2014-10-07
申请号：US12573039
申请日：2009-10-02
申请人： Louie Arthur Dickens , Timothy A Johnson , Craig Anthony Klein , Gregg Steven Lucas , Daniel James Winarski
发明人： Louie Arthur Dickens , Timothy A Johnson , Craig Anthony Klein , Gregg Steven Lucas , Daniel James Winarski
IPC分类号： G06F1/26 , G06F1/32
CPC分类号： G06F1/3287 , G06F1/28 , G06F1/3203 , G06F1/3209 , G06F1/3215 , G06F1/3228 , G06F1/3234 , G06F1/3268 , G06F9/442 , Y02D10/154
摘要： In remote power down control of a device configured for externally initiated remote power down, such as over a network, activity of all externally connected sources of valid power down requests for the device is monitored; and the device is powered down in response to a combination of one of a received power down request and an inactivity time out with respect to each of the sources of valid power down requests for the device.
摘要翻译：在配置为外部启动的远程断电的设备的远程断电控制中，例如通过网络，监视所有外部连接的有用的设备停电请求的活动; 并且所述设备响应于接收到的功率下降请求和相对于所述设备的有效掉电请求的每个源的不活动超时时间中的一个的组合而被断电。

10. 发明申请

US20110145633A1 Blocking Write Acces to Memory Modules of a Solid State Drive 有权
标题翻译：阻止对固态硬盘的内存模块的写入
公开(公告)号：US20110145633A1
公开(公告)日：2011-06-16
申请号：US12638363
申请日：2009-12-15
申请人： Louie Arthur Dickens , Timothy A. Johnson , Craig Anthony Klein , Gregg Steven Lucas , Daniel James Winarski
发明人： Louie Arthur Dickens , Timothy A. Johnson , Craig Anthony Klein , Gregg Steven Lucas , Daniel James Winarski
IPC分类号： G06F11/20 , G06F11/00
CPC分类号： G06F11/0796 , G06F11/073 , G06F11/076 , G06F11/0793 , G06F11/1666
摘要： Described are embodiments of an invention for blocking write access to memory modules of a solid state drive. The solid state drive includes a controller access module or a memory access module that controls write access to the solid state drive and the memory modules of the solid state drive. Upon determining that a memory module has failed, the failed memory module or the entire solid state memory device is configured to be read only to prevent an errant write of data over critical data. Further, a failed memory module, or solid state device memory having a failed memory module, may be replaced upon failure.
摘要翻译：描述了用于阻止对固态驱动器的存储器模块的写访问的发明的实施例。固态驱动器包括控制器访问模块或存储器访问模块，其控制对固态驱动器和固态驱动器的存储器模块的写入访问。在确定存储器模块发生故障时，故障内存模块或整个固态存储设备被配置为只读，以防止在关键数据上错误地写入数据。此外，失败的存储器模块或具有故障存储器模块的固态设备存储器可以在故障时被替换。

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