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1. 发明授权

US06189117B1 Error handling between a processor and a system managed by the processor 有权
标题翻译：处理器与由处理器管理的系统之间的错误处理
公开(公告)号：US06189117B1
公开(公告)日：2001-02-13
申请号：US09135835
申请日：1998-08-18
申请人： Gary William Batchelor , Brent Cameron Beardsley , Michael Thomas Benhase , Jack Harvey Derenburger , Carl Evan Jones , Robert Earl Medlin , Belayneh Tafesse , Juan Antonio Yanes
发明人： Gary William Batchelor , Brent Cameron Beardsley , Michael Thomas Benhase , Jack Harvey Derenburger , Carl Evan Jones , Robert Earl Medlin , Belayneh Tafesse , Juan Antonio Yanes
IPC分类号： G06F1100
CPC分类号： G06F11/0796
摘要： Disclosed is a system for handling errors. A system managed by a processor processes an error in the system. The system then generates an interrupt to the processor indicating that an error occurred and executes an error mode before the processor interprets the interrupt. As part of the error mode, the system prevents data from transferring between the system and the processor and processes a read request from the processor to the system by returning data to the processor unrelated to the requested data. The processor would then process the interrupt indicating the error and execute a diagnostic mode to diagnose the error in the system.
摘要翻译：公开了一种处理错误的系统。由处理器管理的系统处理系统中的错误。系统然后在处理器解释中断之前，向处理器产生指示发生错误的中断并执行错误模式。作为错误模式的一部分，系统防止数据在系统和处理器之间传输，并通过将数据返回到与请求的数据无关的处理器来处理从处理器到系统的读取请求。然后处理器将处理指示错误的中断，并执行诊断模式以诊断系统中的错误。

2. 发明授权

US06535937B1 Write command verification across a PCI bus system 失效
标题翻译：通过PCI总线系统编写命令验证
公开(公告)号：US06535937B1
公开(公告)日：2003-03-18
申请号：US09503911
申请日：2000-02-15
申请人： Brent Cameron Beardsley , Michael Thomas Benhase , Russell Lee Ellison , Gregg Steven Lucas , Juan Antonio Yanes
发明人： Brent Cameron Beardsley , Michael Thomas Benhase , Russell Lee Ellison , Gregg Steven Lucas , Juan Antonio Yanes
IPC分类号： G06F1338
CPC分类号： G06F13/4221 , G06F13/4027
摘要： A method and system to verify the passage of one or more write commands sent from an originating location through a PCI bus system. An addressable data storage is located substantially at the end of the PCI bus system with respect to the originating location. A write command is sent by the originator subsequent to the one or more write commands, to a predetermined special end location address identifying the addressable storage. The command is accompanied by data comprising a predetermined special return address at the originating location. The PCI bus system transmits the write commands on a FIFO basis, so the one or more write commands precede the subsequently sent write command. Logic senses the subsequently sent write command, and responds to the command, sending a return echo write command to the predetermined special return address. The returning echo write command verifies the passage of the write commands and data through the PCI bus system. The predetermined special end location address is the key to identify the subsequently sent write command.
摘要翻译：一种用于验证从始发位置通过PCI总线系统发送的一个或多个写入命令的通过的方法和系统。相对于始发位置，可寻址数据存储器基本上位于PCI总线系统的末端。写命令由发起者在一个或多个写入命令之后发送到标识可寻址存储器的预定特殊结束位置地址。该命令伴随着在始发位置处包括预定的特殊返回地址的数据。 PCI总线系统以FIFO为基础发送写命令，因此一个或多个写命令先于随后发送的写命令。逻辑检测随后发送的写入命令，并响应该命令，向预定的特殊返回地址发送返回回显写命令。返回的回写写命令通过PCI总线系统验证写命令和数据的通过。预定的特殊终端位置地址是识别随后发送的写命令的关键。

3. 发明授权

US06530043B1 Write data error checking in a PCI Bus system 失效
标题翻译：在PCI总线系统中写入数据错误检查
公开(公告)号：US06530043B1
公开(公告)日：2003-03-04
申请号：US09522440
申请日：2000-03-09
申请人： Brent Cameron Beardsley , Michael Thomas Benhase , Gregg Steven Lucas , Juan Antonio Yanes
发明人： Brent Cameron Beardsley , Michael Thomas Benhase , Gregg Steven Lucas , Juan Antonio Yanes
IPC分类号： G06F1108
CPC分类号： H04L1/0061 , H04L1/0041 , H04L1/0045
摘要： In a PCI bus system, a method and system check for errors in rite data transferred from a PCI data source across a PCI bus to the PCI bus system, the data comprising a plurality of blocks. Redundancy calculation logic receives the write data across the PCI bus, calculates a check value for each block of the data transferred across the PCI bus, and updating any previously calculated check value with the calculated check value at a storage location of a storage memory. Data path logic is coupled to the PCI bus and to the storage memory, and responds to a unique identifier of a redundancy write command sent subsequent to completion of the transfer of the write data across the PCI interface. The data path logic responds to the write command unique identifier, detecting the updated calculated check value at the storage location of the storage memory. Error check logic coupled to the data path logic determines whether the detected updated calculated check value indicates an error, and upon the detected updated calculated check value indicating an error, signals the error.
摘要翻译：在PCI总线系统中，方法和系统检查从PCI数据源通过PCI总线传输到PCI总线系统的仪表数据中的错误，该数据包括多个块。冗余计算逻辑通过PCI总线接收写入数据，计算通过PCI总线传输的数据的每个块的校验值，并且在存储存储器的存储位置处用计算出的校验值更新任何先前计算的校验值。数据路径逻辑耦合到PCI总线和存储存储器，并且响应在完成跨PCI接口的写入数据传送之后发送的冗余写入命令的唯一标识符。数据路径逻辑响应写入命令唯一标识符，检测在存储存储器的存储位置处更新的计算的检查值。耦合到数据路径逻辑的错误检查逻辑确定检测到的更新的计算的检查值是否指示错误，并且在检测到的更新的指示错误的计算的检查值时，发信号通知错误。

4. 发明授权

US06286074B1 Method and system for reading prefetched data across a bridge system 失效
标题翻译：在桥系统上读取预取数据的方法和系统
公开(公告)号：US06286074B1
公开(公告)日：2001-09-04
申请号：US09275610
申请日：1999-03-24
申请人： Gary William Batchelor , Brent Cameron Beardsley , Matthew Joseph Kalos , Forrest Lee Wade
发明人： Gary William Batchelor , Brent Cameron Beardsley , Matthew Joseph Kalos , Forrest Lee Wade
IPC分类号： G06F1314
CPC分类号： G06F13/4059
摘要： Disclosed is a bridge system for processing read transactions over a bus in which in a preferred embodiment prefetched data stored in a buffer is not discarded if the address of the requested read does not match the beginning address of the prefetched data. Instead, the bridge system skips to the next address of the prefetched data stored in the buffer and compares that address to the address of the read request to determine if a match exists. If the requested read address does match the next prefetched data address, the prefetched data starting at that next address is read out and forwarded to the requesting agent. Alternatively, if there is not a match, the bridge skips again to the next address and continues checking for a match until either the prefetched data is exhausted or another predetermined limit has been reached. In this manner, many unnecessary data reads of data already prefetched in the buffer may be avoided.
摘要翻译：公开了一种用于通过总线处理读取事务的桥接系统，其中在优选实施例中，如果所请求的读取的地址与预取数据的起始地址不匹配，则不会丢弃存储在缓冲器中的预取数据。相反，桥接系统跳过存储在缓冲器中的预取数据的下一个地址，并将该地址与读取请求的地址进行比较，以确定是否存在匹配。如果所请求的读取地址与下一个预取数据地址匹配，则从该下一个地址开始的预取数据被读出并转发给请求代理。或者，如果不匹配，桥接器再次跳到下一个地址，并继续检查匹配，直到预取的数据被耗尽或达到了另一个预定的限制。以这种方式，可以避免在缓冲器中预取的数据的许多不必要的数据读取。

5. 发明授权

US06345295B1 Conducting traces in a computer system attachment network 失效
标题翻译：在计算机系统附件网络中进行跟踪
公开(公告)号：US06345295B1
公开(公告)日：2002-02-05
申请号：US09235303
申请日：1999-01-22
申请人： Brent Cameron Beardsley , Carl Evan Jones , William Griswold Sherman , Joe Edward Smothers
发明人： Brent Cameron Beardsley , Carl Evan Jones , William Griswold Sherman , Joe Edward Smothers
IPC分类号： G06F1338
CPC分类号： G06F11/3495 , G06F11/348 , H04L43/50
摘要： A trace facility for a computer system attachment network, a method for operating that network, and trace tools in the network. The network has a plurality of the trace tools, each connected to a communication path, the trace facility providing a system wide trace. The trace facility comprises at least one trace buffer at each trace tool. Each trace tool has an address filter selecting an address range of information on the bus, the information being communicated on the bus as events, and storing the selected event information in the trace buffers, thereby conducting a trace. A breakpoint connection is provided interconnecting each of the trace tools. A trace tool control at each trace tool responds to a trace stop command addressed to the trace tool, to stop the trace at its address filter and trace buffer, and to issue a breakpoint signal on the breakpoint connection to all the interconnected trace tools. The interconnected trace tools respond to the breakpoint signal to stop the trace thereat, so that the trace is saved at each trace tool. An elapse clock provides a time stamp for each traced event to allow determination of the timing of each event.
摘要翻译：用于计算机系统附件网络的跟踪功能，用于操作该网络的方法以及在网络中跟踪工具。网络具有多个跟踪工具，每个跟踪工具都连接到通信路径，跟踪设备提供系统范围的跟踪。跟踪设备包括每个跟踪工具上的至少一个跟踪缓冲区。每个跟踪工具具有地址过滤器，其选择总线上的信息的地址范围，作为事件在总线上传送的信息，以及将所选择的事件信息存储在跟踪缓冲器中，从而进行跟踪。提供连接每个跟踪工具的断点连接。每个跟踪工具上的跟踪工具控件会响应寻址到跟踪工具的跟踪停止命令，以停止其地址过滤器和跟踪缓冲区上的跟踪，并在断点连接上向所有互连的跟踪工具发出断点信号。互连的跟踪工具响应断点信号以停止其上的跟踪，以便在每个跟踪工具上保存跟踪。经过时钟为每个跟踪的事件提供时间戳，以允许确定每个事件的时间。

6. 发明授权

US6112311A Bridge failover system 失效
标题翻译：桥接故障转移系统
公开(公告)号：US6112311A
公开(公告)日：2000-08-29
申请号：US26620
申请日：1998-02-20
申请人： Brent Cameron Beardsley , Carl Evan Jones , Forrest Lee Wade
发明人： Brent Cameron Beardsley , Carl Evan Jones , Forrest Lee Wade
IPC分类号： G06F11/20 , G06F13/40 , H04L12/46 , G06F11/00
CPC分类号： G06F11/2005 , G06F13/4027 , H04L12/462 , G06F11/2007
摘要： Disclosed is a system for communication among a device, a first processor, and a second processor. One of a first data path and second data path is configured. The first data path comprises a bus, such as a local PCI bus, a first remote bridge, and a first local bridge. The bridges may be comprised of PCI to PCI bridges. After configuring the first data path, the device communicates to the first processor by communicating data through the bus to the first remote bridge. The first remote bridge transmits the data to the first local bridge and the first local bridge transmits the data to the first processor. The second data path comprises the bus, a second remote bridge, and a second local bridge. After configuring the second data path, the device communicates to the second processor by communicating data through the bus to the second remote bridge. The second remote bridge transmits the data to the second local bridge and the second local bridge transmits the data to the second processor.
摘要翻译：公开了一种用于设备，第一处理器和第二处理器之间的通信的系统。配置第一数据路径和第二数据路径之一。第一数据路径包括总线，例如本地PCI总线，第一远程桥和第一局部桥。桥可以由PCI到PCI桥组成。在配置第一数据路径之后，设备通过总线将数据传送到第一远程桥与第一处理器通信。第一个远程桥将数据发送到第一个本地网桥，第一个本地桥将数据传输到第一个处理器。第二数据路径包括总线，第二远程桥和第二局部桥。在配置第二数据路径之后，设备通过总线将数据传送到第二远程桥与第二处理器进行通信。第二远程桥将数据发送到第二本地网桥，而第二本地桥将数据传送到第二处理器。

7. 发明授权

US06785771B2 Method, system, and program for destaging data in cache 失效
标题翻译：用于在缓存中降级数据的方法，系统和程序
公开(公告)号：US06785771B2
公开(公告)日：2004-08-31
申请号：US10005003
申请日：2001-12-04
申请人： Kevin John Ash , Brent Cameron Beardsley , Michael Thomas Benhase , Joseph Smith Hyde, II , Thomas Charles Jarvis , Steven Robert Lowe , David Frank Mannenbach
发明人： Kevin John Ash , Brent Cameron Beardsley , Michael Thomas Benhase , Joseph Smith Hyde, II , Thomas Charles Jarvis , Steven Robert Lowe , David Frank Mannenbach
IPC分类号： G06F1200
CPC分类号： G06F12/0871 , G06F12/0804
摘要： Provided is a method, system, and program for destaging data from a first computer readable medium to a second computer readable medium. A list of entries indicating data blocks in the first computer readable medium is scanned. For each entry scanned, a determination is made as to whether the data block indicated in the scanned entry satisfies a criteria. If the data block indicated in the scanned entry satisfies the criteria, then a destage operation is called to destage the data block in the scanned entry from the first computer readable medium to the second computer readable medium. If the called destage operation is not initiated, then the scanned entry is removed from the cache list. The removed scanned entry is added to one destage wait list. During one destage operation, data blocks indicated in entries in the destage wait list are destaged.
摘要翻译：提供了一种用于将数据从第一计算机可读介质降级到第二计算机可读介质的方法，系统和程序。扫描第一计算机可读介质中指示数据块的条目列表。对于扫描的每个条目，确定扫描条目中指示的数据块是否满足标准。如果扫描条目中指示的数据块满足标准，则调度一个转移操作以将扫描条目中的数据块从第一计算机可读介质转移到第二计算机可读介质。如果未启动所呼叫的终止操作，则从缓存列表中删除扫描的条目。已删除的扫描条目将添加到一个目的地等待列表中。在一个运行期间，在目的地等待列表中的条目中指示的数据块已停止运行。

8. 发明授权

US06438661B1 Method, system, and program for managing meta data in a storage system and rebuilding lost meta data in cache 失效
标题翻译：用于管理存储系统中的元数据并在缓存中重建丢失的元数据的方法，系统和程序
公开(公告)号：US06438661B1
公开(公告)日：2002-08-20
申请号：US09261824
申请日：1999-03-03
申请人： Brent Cameron Beardsley , Michael Thomas Benhase , Douglas A. Martin , Robert Louis Morton , Kenneth Wayne Todd
发明人： Brent Cameron Beardsley , Michael Thomas Benhase , Douglas A. Martin , Robert Louis Morton , Kenneth Wayne Todd
IPC分类号： G06F1206
CPC分类号： G06F11/1435 , Y10S707/99953
摘要： Disclosed is a method, system, and article of manufacture for processing modified meta data for data recovery operations. The meta data provides information on user data maintained in a storage device. The system determines whether meta data tracks maintained in a cache were modified and indicates in a non-volatile memory that the determined meta data tracks were modified. Data recovery operations may be initiated as a result of a system failure, such as a warmstart or coldstart recovery. During such data recovery operations, the system processes the non-volatile memory and the indications of modified meta data tracks therein to rebuild lost meta data tracks in the cache.
摘要翻译：公开了用于处理用于数据恢复操作的修改的元数据的方法，系统和制品。元数据提供有关存储设备中维护的用户数据的信息。该系统确定在高速缓存中维护的元数据轨道是否被修改，并且在非易失性存储器中指示修改了所确定的元数据轨道。数据恢复操作可能由于系统故障（如热启动或冷启动恢复）而启动。在这种数据恢复操作期间，系统处理非易失性存储器及其中修改的元数据轨迹的指示，以重构高速缓存中的丢失的元数据轨道。

9. 发明授权

US06381677B1 Method and system for staging data into cache 失效
标题翻译：将数据分段到缓存中的方法和系统
公开(公告)号：US06381677B1
公开(公告)日：2002-04-30
申请号：US09136626
申请日：1998-08-19
申请人： Brent Cameron Beardsley , Michael Thomas Benhase , Joseph Smith Hyde , Thomas Charles Jarvis , Douglas A. Martin , Robert Louis Morton
发明人： Brent Cameron Beardsley , Michael Thomas Benhase , Joseph Smith Hyde , Thomas Charles Jarvis , Douglas A. Martin , Robert Louis Morton
IPC分类号： G06F1212
CPC分类号： G06F12/0862 , G06F12/0866 , G06F2212/312
摘要： Disclosed is a system for caching data. After determining a sequential access of a first memory area, such as a direct access storage device (DASD), a processing unit stages a group of data sets from the first memory area to a second memory, such as cache. The processing unit processes a data access request (DAR) for data sets in the first memory area that are included in the sequential access and reads the requested data sets from the second memory area. The processing unit determines trigger data set from a plurality of trigger data sets based on a trigger data set criteria. The processing unit then stages a next group of data sets from the first memory area to the second memory area in response to reading the determined trigger data set.
摘要翻译：公开了一种用于缓存数据的系统。在确定诸如直接存取存储设备（DASD）之类的第一存储区域的顺序存取之后，处理单元将来自第一存储器区域的一组数据集合到诸如高速缓存的第二存储器。处理单元处理包括在顺序访问中的第一存储器区域中的数据集的数据访问请求（DAR），并从第二存储器区域读取所请求的数据集。处理单元基于触发数据集标准从多个触发数据集确定触发数据集。响应于读取所确定的触发数据集，处理单元将下一组数据集从第一存储器区域转移到第二存储区域。

10. 发明授权

US5893918A System and method for rotational position sensing miss avoidance in direct access storage devices 失效
标题翻译：直接存取存储装置中旋转位置检测缺失避免的系统和方法
公开(公告)号：US5893918A
公开(公告)日：1999-04-13
申请号：US885099
申请日：1992-05-18
申请人： Brent Cameron Beardsley , Michael Thomas Benhase , Susan Marie Wethington
发明人： Brent Cameron Beardsley , Michael Thomas Benhase , Susan Marie Wethington
IPC分类号： G06F13/10 , G06F3/06 , G06F12/08 , G06F13/14 , G06F13/00
CPC分类号： G06F3/0601 , G06F12/0866 , G06F2003/0692
摘要： A method for operating a controller for a plurality of direct access storage devices to minimize rotational misses during data transfer operations. Transferred data is staged into a controller cache when a rotational position sensing miss avoidance reconnection is made. Circumstances are detailed for qualifying an operation pending on direct access storage devices for treatment as miss avoidance candidates. Adjustment of controller response depending upon foreknowledge that a channel command word chain includes a write operation is also accomplished utilizing the present method.
摘要翻译：一种用于操作用于多个直接存取存储设备的控制器以最小化数据传送操作期间的转移错误的方法。当进行旋转位置感测错过回避重新连接时，传送的数据被分段到控制器高速缓存中。对于直接访问存储设备进行等待处理的错误回避候选人的操作，情况是详细的。使用本方法也可以根据预先知道通道命令字链包括写入操作来调整控制器响应。

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