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1. 发明授权

US06469574B1 Selectable equalization system and method 有权
标题翻译：可选均衡系统和方法
公开(公告)号：US06469574B1
公开(公告)日：2002-10-22
申请号：US09771241
申请日：2001-01-26
申请人： Mehmet M. Eker , Wei Fu , Joseph J. Balardeta
发明人： Mehmet M. Eker , Wei Fu , Joseph J. Balardeta
IPC分类号： H03B100
CPC分类号： H03H21/0001
摘要： A system and method have been provided for selectably equalizing an input signal to an integrated circuit (IC), to compensate for degradation in the transmission process. The selectable equalization circuit includes parallel equalizing and non-equalizing sections. When the equalizing section is engaged a resonant element modifies the circuit impedance to add a zero to the circuit transfer function. When the non-equalizing function is engaged, the equalizing section is disengaged without degrading gate capacitance, and the input signals are processed without a zero in the transfer function.
摘要翻译：已经提供了一种用于可选择地将输入信号均衡到集成电路（IC）的系统和方法，以补偿传输过程中的劣化。可选择均衡电路包括并行均衡和非均衡部分。当均衡部分被接合时，谐振元件修改电路阻抗以向电路传递函数添加零。当非均衡功能被接合时，均衡部分脱离而不降低栅极电容，并且输入信号在传递函数中被处理而没有零。

2. 发明授权

US06642781B1 Selectable equalization system and method 有权
公开(公告)号：US06642781B1
公开(公告)日：2003-11-04
申请号：US10236761
申请日：2002-09-06
申请人： Mehmet M. Eker , Wei Fu , Joseph J. Balardeta
发明人： Mehmet M. Eker , Wei Fu , Joseph J. Balardeta
IPC分类号： H03B100
CPC分类号： H03H21/0001
摘要： A system and method have been provided for selectably equalizing an input signal to an integrated circuit (IC), to compensate for degradation in the transmission process. The selectable equalization circuit includes parallel equalizing and non-equalizing sections. When the equalizing section is engaged a resonant element modifies the circuit impedance to add a zero to the circuit transfer function. When the non-equalizing function is engaged, the equalizing section is disengaged without degrading gate capacitance, and the input signals are processed without a zero in the transfer function.

3. 发明授权

US06469584B1 Phase-locked loop system and method using an auto-ranging, frequency sweep window voltage controlled oscillator 有权
标题翻译：锁相环系统和方法采用自动量程，频率扫描窗口压控振荡器
公开(公告)号：US06469584B1
公开(公告)日：2002-10-22
申请号：US09708819
申请日：2000-11-08
申请人： Mehmet M. Eker , Joseph J. Balardeta
发明人： Mehmet M. Eker , Joseph J. Balardeta
IPC分类号： H03L700
CPC分类号： H03L7/113 , H03L7/087 , H03L7/095 , H03L7/14 , H03L2207/06 , Y10S331/02
摘要： A system and method have been provided for a phase-locked loop (PLL) circuit to use a selectable VCO frequency range during the acquisition of a signal, with a larger VCO frequency sweep window once the signal is being tracked. The circuit uses a frequency detector during acquisition, and the VCO is limited to operation is a plurality of discrete frequency bands. Each frequency band is sequentially searched using the low VCO gain. Upon acquisition, the frequency band is locked in, a phase detector is utilized, and the VCO sweep window is increased for tracking purposes.
摘要翻译：已经提供了一种用于锁相环（PLL）电路的系统和方法，以便在获取信号期间使用可选的VCO频率范围，一旦跟踪信号，则具有较大的VCO频率扫描窗口。该电路在采集期间使用频率检测器，并且VCO被限制为操作是多个离散频带。使用低VCO增益顺序地搜索每个频带。在获取时，锁定频带，利用相位检测器，并且为了跟踪目的而增加VCO扫描窗口。

4. 发明授权

US06683489B1 Methods and apparatus for generating a supply-independent and temperature-stable bias current 有权
标题翻译：用于产生独立于供电和温度稳定的偏置电流的方法和装置
公开(公告)号：US06683489B1
公开(公告)日：2004-01-27
申请号：US09965971
申请日：2001-09-27
申请人： Mehmet M. Eker
发明人： Mehmet M. Eker
IPC分类号： G05F110
CPC分类号： G05F3/262
摘要： A biasing circuit for producing a bias current which is supply-independent and temperature-stable includes a first voltage generating circuit which produces a first voltage V1 at an output; a second voltage generating circuit which produces a second voltage V2 different from the first voltage V1 at an output; a differential amplifier circuit having inputs coupled to the outputs of the first and the second voltage generating circuits and producing a reference voltage VREF based on a difference between the first voltage V1 and the second voltage V2; and a current generating circuit which produces a bias current IREF from the reference voltage VREF.
摘要翻译：用于产生与电源无关并且温度稳定的偏置电流的偏置电路包括在输出端产生第一电压V1的第一电压产生电路; 第二电压产生电路，其在输出端产生与所述第一电压V1不同的第二电压V2; 差分放大器电路，其具有耦合到第一和第二电压产生电路的输出的输入，并且基于第一电压V1和第二电压V2之间的差产生参考电压VREF; 以及电流产生电路，其从参考电压VREF产生偏置电流IREF。

5. 发明授权

US06570414B1 Methods and apparatus for reducing the crowbar current in a driver circuit 有权
标题翻译：用于减少驱动器电路中的撬棒电流的方法和装置
公开(公告)号：US06570414B1
公开(公告)日：2003-05-27
申请号：US09966013
申请日：2001-09-27
申请人： Mehmet M. Eker
发明人： Mehmet M. Eker
IPC分类号： H03K300
CPC分类号： H03K19/0013
摘要： A driver circuit which has a reduced or eliminated crowbar current includes a P-channel type transistor having a source coupled to a reference voltage; an N-channel type transistor having a source coupled to ground and a drain coupled to a drain of the P-channel type transistor; first logic gate circuitry (e.g., a NOR gate) having an input coupled to a reference clock signal and an output coupled to a gate of the P-channel type transistor; and second logic gate circuitry (e.g., a NAND gate) having an input coupled to the reference clock signal and an output coupled to a gate of the N-channel type transistor. The first logic gate circuitry is designed to have a first input voltage threshold value (e.g., ¼ VDD) that is different from a second input voltage threshold value (e.g., ¾ VDD) of the second logic gate circuitry. Thus, the output from the first logic gate circuitry provides off-to-on transitions which precede off-to-on transitions provided from the output of the second logic gate circuitry and on-to-off transitions which succeed on-to-off transitions provided by the second clock input signal.
摘要翻译：具有减少或消除的撬棒电流的驱动器电路包括具有耦合到参考电压的源极的P沟道型晶体管; 具有耦合到地的源极和耦合到P沟道型晶体管的漏极的漏极的N沟道型晶体管; 第一逻辑门电路（例如，或非门），其具有耦合到参考时钟信号的输入和耦合到P沟道型晶体管的栅极的输出; 以及具有耦合到参考时钟信号的输入的第二逻辑门电路（例如，NAND门）和耦合到N沟道型晶体管的栅极的输出。第一逻辑门电路被设计为具有与第二逻辑门电路的第二输入电压阈值（例如，¾VDD）不同的第一输入电压阈值（例如，¼VDD）。因此，来自第一逻辑门电路的输出提供在从第二逻辑门电路的输出提供的非接通转换之前的切换到转换，以及成对的切换转换由第二时钟输入信号提供。

6. 发明授权

US06686797B1 Temperature stable CMOS device 有权
标题翻译：温度稳定的CMOS器件
公开(公告)号：US06686797B1
公开(公告)日：2004-02-03
申请号：US10238245
申请日：2002-09-09
申请人： Mehmet M. Eker
发明人： Mehmet M. Eker
IPC分类号： G05F110
CPC分类号： G05F1/56 , G05F3/205 , G05F3/262
摘要： A CMOS field effect transistor (FET) is provided with predetermined temperature characteristics. More particularly, the relationship between the channel length, gate width, gate-to-source voltage, and drain current is exploited to create an FET that has relatively constant drain current across a relatively wide range of frequencies. Alternately, the above-mentioned relationship is exploited to create a drain current with a predetermined temperature coefficient across a wide temperature range.
摘要翻译： CMOS场效应晶体管（FET）具有预定的温度特性。更具体地，利用沟道长度，栅极宽度，栅极 - 源极电压和漏极电流之间的关系来产生在相对宽的频率范围内具有相对恒定的漏极电流的FET。或者，利用上述关系以在宽的温度范围内产生具有预定温度系数的漏极电流。

7. 发明授权

US06504441B1 Voltage controlled oscillator with selectable frequency range 有权
标题翻译：压控振荡器，频率范围可选
公开(公告)号：US06504441B1
公开(公告)日：2003-01-07
申请号：US09708915
申请日：2000-11-08
申请人： Mehmet M. Eker
发明人： Mehmet M. Eker
IPC分类号： H03B520
CPC分类号： H03B23/00
摘要： A frequency sweep voltage controlled oscillator (VCO), with a selectable range of output frequencies is provided. The VCO includes a frequency range circuit to accept an input signal, differentially delay the signal, and selectably sum the delayed signals to provide signals in discrete frequency ranges. A frequency sweep circuit accepts the signal output from the frequency range circuit, differentially delays the signal, and sums the delayed signal in such a way as to modify the previously selected frequency range. A method for generating a signal from a frequency sweep VCO is also provided.
摘要翻译：提供了具有可选择的输出频率范围的频率扫描压控振荡器（VCO）。 VCO包括接收输入信号的频率范围电路，差分地延迟信号，并且可选择地对延迟信号求和以提供离散频率范围内的信号。频率扫描电路接受从频率范围电路输出的信号，差分地延迟信号，并且以延迟的信号相加以修改先前选择的频率范围。还提供了用于从频率扫描VCO产生信号的方法。

8. 发明授权

US06466081B1 Temperature stable CMOS device 有权
标题翻译：温度稳定的CMOS器件
公开(公告)号：US06466081B1
公开(公告)日：2002-10-15
申请号：US09708761
申请日：2000-11-08
申请人： Mehmet M. Eker
发明人： Mehmet M. Eker
IPC分类号： G05F110
CPC分类号： G05F1/56 , G05F3/205 , G05F3/262
摘要： A CMOS field effect transistor (FET) is provided with predetermined temperature characteristics. More particularly, the relationship between the channel length, gate width, gate-to-source voltage, and drain current is exploited to create an FET that has relatively constant drain current across a relatively wide range of frequencies. Alternately, the above-mentioned relationship is exploited to create a drain current with a predetermined temperature coefficient across a wide temperature range.
摘要翻译： CMOS场效应晶体管（FET）具有预定的温度特性。更具体地，利用沟道长度，栅极宽度，栅极 - 源极电压和漏极电流之间的关系来产生在相对宽的频率范围内具有相对恒定的漏极电流的FET。或者，利用上述关系以在宽的温度范围内产生具有预定温度系数的漏极电流。

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