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1. 发明授权

US5295155A Multi-level digital data regeneration system 失效
标题翻译：多级数字数据再生系统
公开(公告)号：US5295155A
公开(公告)日：1994-03-15
申请号：US968716
申请日：1992-10-30
申请人： John E. Gersbach , Ilya I. Novof , Joseph K. Lee
发明人： John E. Gersbach , Ilya I. Novof , Joseph K. Lee
IPC分类号： H04L7/033 , H04L25/06 , H04L25/48 , H04L25/60
CPC分类号： H04L7/0338 , H04L25/062 , H04L25/066 , H04L7/0334
摘要： An adaptive regeneration system is provided for reconstructing a signal received in the form of a multi-level composite data and clock signal which has been degraded with respect to amplitude and timing. The system includes a local clock circuit for outputting a plurality of phase-delayed local clock signals, and a clock recovery circuit for receiving the received multi-level signal and the plurality of phase-delayed clock signals and extracting a phase-delayed local clock signal which most accurately represents the phase shift between the received multi-level signal and the local clock signal. A threshold level selection circuit receives the extracted phase-delayed local clock signal and the received multi-level signal and outputs in real time a data amplitude reading and a plurality of multi-level threshold levels corresponding to the amplitude levels of the received multi-level signal. A data regenerator receives the data amplitude reading, the plurality of multi-level threshold levels and the extracted phase-delayed signal and reconstructs and outputs the received multi-level signal essentially in its originally transmitted form.
摘要翻译：提供了一种自适应再生系统，用于重建以多级复合数据形式接收的信号和相对于幅度和定时已经劣化的时钟信号。该系统包括用于输出多个相位延迟的本地时钟信号的本地时钟电路，以及用于接收所接收的多电平信号和多个相位延迟的时钟信号的时钟恢复电路，并且提取相位延迟的本地时钟信号其最准确地表示接收的多电平信号和本地时钟信号之间的相移。阈值电平选择电路接收所提取的相位延迟的本地时钟信号和接收的多电平信号，并实时输出数据振幅读取和与所接收的多电平的幅度电平对应的多个多电平阈值电平信号。数据再生器接收数据幅度读取，多个多电平阈值电平和提取的相位延迟信号，并且以原始发送的形式重建并输出所接收的多电平信号。

2. 发明授权

US5293405A Adaptive equalization and regeneration system 失效
标题翻译：自适应均衡和再生系统
公开(公告)号：US5293405A
公开(公告)日：1994-03-08
申请号：US785488
申请日：1991-10-31
申请人： John E. Gersbach , Charles R. Hoffman , Ilya I. Novof
发明人： John E. Gersbach , Charles R. Hoffman , Ilya I. Novof
IPC分类号： H03H7/30 , H03H7/40 , H03K5/159
CPC分类号： H04L25/03885
摘要： An adaptive equalization and regeneration system is provided for accurately reconstructing a received data pulse train which has been degraded with respect to amplitude and instantaneous frequency. The system comprises an equalizer which responds to a control signal to provide a variable gain function for the received signal and output an equalized signal, digital phase lock logic for receiving and extracting timing information from the equalized signal, a regenerator for matching the timing information with the equalized signal to reconstruct the received data in its originally transmitted form, and control circuitry for providing the control signal to the equalizer. The control signal adjusts the slope of the equalizer gain function so as to minimize amplitude and instantaneous frequency degradation at the equalizer output. The system includes a mechanism to detect and calculate total signal degradation at the equalizer output. Control logic is used to identify the slope of the equalizer gain function at which total signal degradation is minimized. The control signal, which corresponds to this identified slope, is applied to the equalizer in real time to maintain minimum total signal degradation at the equalizer output.
摘要翻译：提供了一种自适应均衡和再生系统，用于精确地重构已经相对于振幅和瞬时频率退化的接收数据脉冲串。该系统包括均衡器，其响应于控制信号以为接收信号提供可变增益函数并输出均衡信号，用于从均衡信号接收和提取定时信息的数字锁相逻辑，用于将定时信息与用于以原始发送形式重建接收数据的均衡信号，以及用于向均衡器提供控制信号的控制电路。控制信号调整均衡器增益函数的斜率，以便最小化均衡器输出端的幅度和瞬时频率衰减。该系统包括一个检测和计算均衡器输出端总信号衰减的机制。控制逻辑用于识别总信号劣化最小化的均衡器增益函数的斜率。将对应于该识别的斜率的控制信号实时地施加到均衡器，以保持均衡器输出处的最小总信号劣化。

3. 发明授权

US5694087A Anti-latching mechanism for phase lock loops 失效
标题翻译：锁相环锁止机构
公开(公告)号：US5694087A
公开(公告)日：1997-12-02
申请号：US592902
申请日：1996-01-29
申请人： Frank D. Ferraiolo , John E. Gersbach , Masayuki Hayashi , Ilya I. Novof , Charles J. Masenas, Jr.
发明人： Frank D. Ferraiolo , John E. Gersbach , Masayuki Hayashi , Ilya I. Novof , Charles J. Masenas, Jr.
IPC分类号： H03L7/10 , H03L7/093
CPC分类号： H03L7/10
摘要： A protective circuit for a phase lock loop ensures that the VCO does not initiate a runaway condition when outputting a signal having a frequency higher than the feedback divider can respond to. During normal phase lock operation, a counter keeps track of the PLL input signal and is reset by the feedback divider. In the runaway condition the counter is not reset and triggers a control signal to the VCO. A second counter can be used to keep track of the feedback divider output and to reset the first counter. When the first counter far outruns the second counter the control signal is triggered.
摘要翻译：用于锁相环的保护电路确保当输出具有高于反馈分配器的频率的信号可以响应时，VCO不会发起失控状况。在正常锁相操作期间，计数器跟踪PLL输入信号，并由反馈分频器复位。在失控状态下，计数器不复位，并触发VCO的控制信号。第二个计数器可用于跟踪反馈分频器输出并复位第一个计数器。当第一个计数器远远超出第二个计数器时，触发控制信号。

4. 发明授权

US5491439A Method and apparatus for reducing jitter in a phase locked loop circuit 失效
标题翻译：减少锁相环电路抖动的方法和装置
公开(公告)号：US5491439A
公开(公告)日：1996-02-13
申请号：US298695
申请日：1994-08-31
申请人： Ram Kelkar , Ilya I Novof , Stephen D. Wyatt
发明人： Ram Kelkar , Ilya I Novof , Stephen D. Wyatt
IPC分类号： H03D13/00 , H03K3/0231 , H03L7/089 , H03L7/093 , H03L7/095 , H03L7/10 , H03L7/06
CPC分类号： H03L7/095 , H03K3/0231 , H03L7/0893 , H03D13/004 , H03L2207/06 , H03L7/0896 , H03L7/0898 , Y10S331/02
摘要： A phase locked loop circuit includes a phase/frequency detector which uses a divider circuit and feedback from a clock distribution tree to generate INC and DEC pulses which have no "dead zone". A pair of charge pumps receives the INC and DEC pulses. One charge pump is a differential pump and has voltage controlled common mode feedback circuit to maintain a common mode controlled voltage. A differential current is outputted to a loop filter capacitor by this charge pump. The other charge pump is a single-ended output pump which supplies current to a current controlled oscillator which also receives input from a voltage to current converter. The current controlled oscillator includes a variable resistance load which varies inversely with the magnitude of the input current. A jitter control circuit is provided which reduces jitter in the current controlled oscillator output in the locked phase. Also, a lock indicator is provided which is time independent, and provides a lock indication when the loop enters the locked condition.
摘要翻译：锁相环电路包括相位/频率检测器，该相位/频率检测器使用分频器电路和来自时钟分配树的反馈来产生没有“死区”的INC和DEC脉冲。一对电荷泵接收INC和DEC脉冲。一个电荷泵是差分泵，并具有电压控制的共模反馈电路，以保持共模控制电压。通过该电荷泵将差分电流输出到环路滤波电容器。另一个电荷泵是一个单端输出泵，它向电流控制振荡器提供电流，该电流控制振荡器也接收电压到电流转换器的输入。电流控制振荡器包括与输入电流的大小成反比变化的可变电阻负载。提供了一种抖动控制电路，可减少锁定相中当前受控振荡器输出的抖动。而且，提供了与时间无关的锁定指示器，并且当环路进入锁定状态时提供锁定指示。

5. 发明授权

US5371766A Clock extraction and data regeneration logic for multiple speed data communications systems 失效
标题翻译：用于多速数据通信系统的时钟提取和数据再生逻辑
公开(公告)号：US5371766A
公开(公告)日：1994-12-06
申请号：US979121
申请日：1992-11-20
申请人： John E. Gersbach , Ilya I. Novof , Joseph K. Lee
发明人： John E. Gersbach , Ilya I. Novof , Joseph K. Lee
IPC分类号： H04L7/033 , H04L12/42 , H03D3/24
CPC分类号： H04L7/0337 , H04L12/422
摘要： Clock extraction and data regeneration logic is provided for a multiple rate digital data communications system such as a local area network (LAN). The logic is implemented in adapters which connect stations in the LAN to other stations in the LAN via transmission media such as wire or fiber optic cable. The clock extraction and data regeneration logic is adapted to quickly recognize the speed at which the token ring is operating, thereby preventing a station on the ring from sending data onto the ring at a rate which does not match the operating frequency of the ring. The logic also performs, at multiple speeds of operation, clock extraction and data reconstruction of a signal received from another station in the ring.
摘要翻译：为诸如局域网（LAN）的多速率数字数据通信系统提供时钟提取和数据再生逻辑。逻辑是通过适配器实现的，这些适配器通过诸如有线或光纤电缆的传输介质将LAN中的站与LAN中的其他站连接。时钟提取和数据再生逻辑适于快速识别令牌环操作的速度，从而防止环上的站以与环的工作频率不匹配的速率将数据发送到环上。该逻辑还在多个操作速度下执行从环中的另一个站接收的信号的时钟提取和数据重建。

6. 发明授权

US5272729A Clock signal latency elimination network 失效
标题翻译：时钟信号延迟消除网络
公开(公告)号：US5272729A
公开(公告)日：1993-12-21
申请号：US763510
申请日：1991-09-20
申请人： Roland Bechade , Frank D. Ferraiolo , Bruce Kaufmann , Ilya I. Novof , Steven F. Oakland , Kenneth Shaw , Leon Skarshinski
发明人： Roland Bechade , Frank D. Ferraiolo , Bruce Kaufmann , Ilya I. Novof , Steven F. Oakland , Kenneth Shaw , Leon Skarshinski
IPC分类号： G06F1/10 , G11C11/407 , H03K5/00 , H03K5/135 , H03K5/15 , H04J3/06 , H04L7/033 , H04L7/00 , H04L25/36 , H04L25/40
CPC分类号： H03K5/1504 , G06F1/10
摘要： A process independent digital clock signal timing network is described for generating a chip clock substantially in phase with and offset by one cycle from an input clock signal. The timing network determines the delay experienced by a clock signal passing through a predetermined internal clock circuit on the chip and pregates the internal clock circuit by an amount equivalent to the determined delay such that the chip clock signal output from the internal clock circuitry lags the external clock signal input to the semiconductor chip by one cycle. Various timing network embodiments are described and claimed.
摘要翻译：描述了一种独立于过程的数字时钟信号定时网络，用于产生与输入时钟信号基本同相并偏移一个周期的芯片时钟。定时网络确定通过芯片上的预定内部时钟电路的时钟信号经历的延迟，并且将内部时钟电路预先相当于所确定的延迟量，使得从内部时钟电路输出的芯片时钟信号滞后于外部时钟信号输入到半导体芯片一个周期。描述和要求保护各种定时网络实施例。

7. 发明授权

US5495207A Differential current controlled oscillator with variable load 失效
标题翻译：具有可变负载的差分电流控制振荡器
公开(公告)号：US5495207A
公开(公告)日：1996-02-27
申请号：US298683
申请日：1994-08-31
申请人： Ilya I. Novof
发明人： Ilya I. Novof
IPC分类号： H03K3/0231 , H03K3/354 , H03L7/089 , H03L7/095 , H03L7/099 , H03B5/00
CPC分类号： H03L7/0995 , H03K3/0231 , H03K3/354 , H03L7/0893 , H03L7/0896 , H03L7/095 , Y10S331/02
摘要： A phase locked loop circuit includes a phase/frequency detector which uses a divider circuit and feedback from a clock distribution tree to generate INC and DEC pulses which have no "dead zone". A pair of charge pumps receives the INC and DEC pulses. One charge pump is a differential pump and has voltage controlled common mode feedback circuit to maintain a common mode controlled voltage. A differential current is outputted to a loop filter capacitor by this charge pump. The other charge pump is a single-ended output pump which supplies current to a current controlled oscillator which also receives input from a voltage to current converter. The current controlled oscillator includes a variable resistance load which varies inversely with the magnitude of the input current. A jitter control circuit is provided which reduces jitter in the current controlled oscillator output in the locked phase. Also, a lock indicator is provided which is time independent, and provides a lock indication when the loop enters the locked condition.
摘要翻译：锁相环电路包括相位/频率检测器，该相位/频率检测器使用分频器电路和来自时钟分配树的反馈来产生没有“死区”的INC和DEC脉冲。一对电荷泵接收INC和DEC脉冲。一个电荷泵是差分泵，并具有电压控制的共模反馈电路，以保持共模控制电压。通过该电荷泵将差分电流输出到环路滤波电容器。另一个电荷泵是一个单端输出泵，它向电流控制振荡器提供电流，该电流控制振荡器也接收电压到电流转换器的输入。电流控制振荡器包括与输入电流的大小成反比变化的可变电阻负载。提供了一种抖动控制电路，可减少锁定相中当前受控振荡器输出的抖动。而且，提供了与时间无关的锁定指示器，并且当环路进入锁定状态时提供锁定指示。

8. 发明授权

US5418789A Fast communication link bit error rate estimator 失效
标题翻译：快速通信链路误码率估计器
公开(公告)号：US5418789A
公开(公告)日：1995-05-23
申请号：US960971
申请日：1992-10-14
申请人： John E. Gersbach , Ilya I. Novof , Joseph K. Lee
发明人： John E. Gersbach , Ilya I. Novof , Joseph K. Lee
IPC分类号： H04L1/20 , G06F11/00 , H04B17/00
CPC分类号： H04L1/20
摘要： A system and method is provided for estimating the bit error rate of a data signal which has been reconstructed from a received data signal. The system comprises (i) logic for determining timing degradation and amplitude degradation of the received data signal; (ii) an actual bit error rate calculator for calculating the actual bit error rate of the reconstructed data signal; (iii) an instantaneous bit error rate calculator for estimating a bit error rate of the reconstructed signal using the timing degradation and the amplitude degradation; (iv) a first integrator for integrating the estimated bit error rate; (v) a comparator for comparing the integrated estimated bit error rate with the actual bit error rate and outputting an error signal which modifies the estimated bit error rate; and (vi) a second integrator for integrating the estimated bit error rate. The time constant associated with the second integrator is shorter than the time constant associated with the first integrator.
摘要翻译：提供了一种系统和方法，用于估计从接收的数据信号重构的数据信号的误码率。该系统包括（i）用于确定接收数据信号的定时劣化和幅度劣化的逻辑; （ii）实际误码率计算器，用于计算重构数据信号的实际误码率; （iii）瞬时误码率计算器，用于使用定时劣化和幅度劣化来估计重构信号的误码率; （iv）用于对估计的误码率进行积分的第一积分器; （v）比较器，用于将积分估计误码率与实际误码率进行比较，并输出修改估计误码率的误差信号; 和（vi）用于对估计的误码率进行积分的第二积分器。与第二积分器相关联的时间常数小于与第一积分器相关联的时间常数。

9. 发明授权

US5347234A Digital voltage controlled oscillator 失效
标题翻译：数字压控振荡器
公开(公告)号：US5347234A
公开(公告)日：1994-09-13
申请号：US37202
申请日：1993-03-26
申请人： John E. Gersbach , Ilya I. Novof
发明人： John E. Gersbach , Ilya I. Novof
IPC分类号： H03B5/20 , H03B27/00 , H03K3/03 , H03K3/354 , H03L7/06 , H03L7/099
CPC分类号： H03L7/0995 , H03K3/0315 , H03B27/00 , H03B5/20
摘要： A digital phase lock loop is provided, comprising a digital voltage controlled oscillator, a phase detector, and an up/down counter. The digital voltage controlled oscillator is responsive to a first set of control signals received from the up/down counter to provide an output signal. The phase detector receives and compares the frequency of the output signal with the frequency of a reference signal and, based on the comparison, outputs to the up/down counter a second control signal which determines the status of the first set of control signals. The digital voltage controlled oscillator comprises (i) an array of delay elements and (ii) a decoder for receiving the first set of the control signals from the up/down counter and for selectively activating one or more of the delay elements in response thereto. The decoder provides a separate output line for each of the delay elements which is to be selectively activated. The logic required to implement the decoder requires only a single AND gate and a single OR gate for each of the delay elements in the array.
摘要翻译：提供数字锁相环，包括数字压控振荡器，相位检测器和升/降计数器。数字压控振荡器响应于从上/下计数器接收的第一组控制信号以提供输出信号。相位检测器接收并比较输出信号的频率与参考信号的频率，并且基于该比较，向加/减计数器输出确定第一组控制信号的状态的第二控制信号。数字压控振荡器包括（i）延迟元件阵列和（ii）解码器，用于从上/下计数器接收第一组控制信号，并响应于此选择性地激活一个或多个延迟元件。解码器为要被选择性地激活的每个延迟元件提供单独的输出线。实现解码器所需的逻辑对于阵列中的每个延迟元件只需要一个AND门和一个OR门。

10. 发明授权

US5220581A Digital data link performance monitor 失效
标题翻译：数字数据链路性能监视器
公开(公告)号：US5220581A
公开(公告)日：1993-06-15
申请号：US676638
申请日：1991-03-28
申请人： Frank D. Ferraiolo , John E. Gersbach , Ilya I. Novof
发明人： Frank D. Ferraiolo , John E. Gersbach , Ilya I. Novof
IPC分类号： H04L7/00 , H04L1/24 , H04L7/02 , H04L7/033 , H04L12/26
CPC分类号： H04L43/00 , H04L1/24 , H04L12/2602 , H04L7/0334 , H04L7/0337 , H04L43/0817 , H04L43/087 , H04L43/16
摘要： A digital data link performance monitor technique for communication systems and information and data processing systems is disclosed. The technique is based on the integration and analysis of a plurality of sorted data edge transitions of a serial data stream received over the digital data link. The number of data edge sorts to each of n time intervals definitive of the edge histogram is compared with a predetermined threshold level and a monitor signal is generated with each comparison. The combination of monitor signals is then analyzed to determine the amount of data timing jitter, and therefore the quality of the link. Corresponding methods and circuits are described.
摘要翻译：公开了用于通信系统和信息和数据处理系统的数字数据链路性能监视技术。该技术基于通过数字数据链路接收的串行数据流的多个排序数据边缘转换的集成和分析。将边缘直方图的n个时间间隔确定的每一个的数据边缘排列次数与预定的阈值电平进行比较，并且通过每个比较生成监视信号。然后分析监视信号的组合以确定数据定时抖动的量，并因此确定链路的质量。描述相应的方法和电路。

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