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1. 发明授权

US5220581A Digital data link performance monitor 失效
标题翻译：数字数据链路性能监视器
公开(公告)号：US5220581A
公开(公告)日：1993-06-15
申请号：US676638
申请日：1991-03-28
申请人： Frank D. Ferraiolo , John E. Gersbach , Ilya I. Novof
发明人： Frank D. Ferraiolo , John E. Gersbach , Ilya I. Novof
IPC分类号： H04L7/00 , H04L1/24 , H04L7/02 , H04L7/033 , H04L12/26
CPC分类号： H04L43/00 , H04L1/24 , H04L12/2602 , H04L7/0334 , H04L7/0337 , H04L43/0817 , H04L43/087 , H04L43/16
摘要： A digital data link performance monitor technique for communication systems and information and data processing systems is disclosed. The technique is based on the integration and analysis of a plurality of sorted data edge transitions of a serial data stream received over the digital data link. The number of data edge sorts to each of n time intervals definitive of the edge histogram is compared with a predetermined threshold level and a monitor signal is generated with each comparison. The combination of monitor signals is then analyzed to determine the amount of data timing jitter, and therefore the quality of the link. Corresponding methods and circuits are described.
摘要翻译：公开了用于通信系统和信息和数据处理系统的数字数据链路性能监视技术。该技术基于通过数字数据链路接收的串行数据流的多个排序数据边缘转换的集成和分析。将边缘直方图的n个时间间隔确定的每一个的数据边缘排列次数与预定的阈值电平进行比较，并且通过每个比较生成监视信号。然后分析监视信号的组合以确定数据定时抖动的量，并因此确定链路的质量。描述相应的方法和电路。

2. 发明授权

US5694087A Anti-latching mechanism for phase lock loops 失效
标题翻译：锁相环锁止机构
公开(公告)号：US5694087A
公开(公告)日：1997-12-02
申请号：US592902
申请日：1996-01-29
申请人： Frank D. Ferraiolo , John E. Gersbach , Masayuki Hayashi , Ilya I. Novof , Charles J. Masenas, Jr.
发明人： Frank D. Ferraiolo , John E. Gersbach , Masayuki Hayashi , Ilya I. Novof , Charles J. Masenas, Jr.
IPC分类号： H03L7/10 , H03L7/093
CPC分类号： H03L7/10
摘要： A protective circuit for a phase lock loop ensures that the VCO does not initiate a runaway condition when outputting a signal having a frequency higher than the feedback divider can respond to. During normal phase lock operation, a counter keeps track of the PLL input signal and is reset by the feedback divider. In the runaway condition the counter is not reset and triggers a control signal to the VCO. A second counter can be used to keep track of the feedback divider output and to reset the first counter. When the first counter far outruns the second counter the control signal is triggered.
摘要翻译：用于锁相环的保护电路确保当输出具有高于反馈分配器的频率的信号可以响应时，VCO不会发起失控状况。在正常锁相操作期间，计数器跟踪PLL输入信号，并由反馈分频器复位。在失控状态下，计数器不复位，并触发VCO的控制信号。第二个计数器可用于跟踪反馈分频器输出并复位第一个计数器。当第一个计数器远远超出第二个计数器时，触发控制信号。

3. 发明授权

US5825226A Delay equalization apparatus and method 失效
标题翻译：延迟均衡装置及方法
公开(公告)号：US5825226A
公开(公告)日：1998-10-20
申请号：US529850
申请日：1995-09-18
申请人： Frank D. Ferraiolo , John E. Gersbach , Ilya I. Novof
发明人： Frank D. Ferraiolo , John E. Gersbach , Ilya I. Novof
IPC分类号： H03K5/13 , H03L7/081 , H03L7/089 , H03K5/00
CPC分类号： H03L7/0895 , H03K5/133 , H03L7/0812
摘要： A delay equalization circuit for minimizing the static phase error in a PLL is provided. The delay equalization circuit includes an external clock signal variable delay path, and an element for creating a pulse with a width proportional to the delay of the external clock signal variable delay path. The delay equalization circuit also includes a delay path in the feedback loop, and second element for creating a second pulse in proportion to the delay of the internal delay path. Finally, the circuit contains a comparison device. The comparison device compares the first and second pulses. The comparison device outputs a difference signal in proportion to the difference in the external and internal path delays. That difference signal is fed back and used to control the external path delay such that the external delay is driven to be substantially equal to the internal delay, minimizing the static phase error of the PLL device.
摘要翻译：提供了用于最小化PLL中的静态相位误差的延迟均衡电路。延迟均衡电路包括外部时钟信号可变延迟路径和用于产生具有与外部时钟信号可变延迟路径的延迟成比例的宽度的脉冲的元件。延迟均衡电路还包括反馈回路中的延迟路径，以及用于与内部延迟路径的延迟成比例地产生第二脉冲的第二元件。最后，该电路包含比较装置。比较装置比较第一和第二脉冲。比较装置与外部和内部路径延迟的差异成比例地输出差分信号。该差分信号被反馈并用于控制外部路径延迟，使得外部延迟被驱动为基本上等于内部延迟，从而最小化PLL器件的静态相位误差。

4. 发明授权

US5627456A All FET fully integrated current reference circuit 失效
标题翻译：所有FET全集成电流参考电路
公开(公告)号：US5627456A
公开(公告)日：1997-05-06
申请号：US477208
申请日：1995-06-07
申请人： Ilya I. Novof , John E. Gersbach , Frank D. Ferraiolo
发明人： Ilya I. Novof , John E. Gersbach , Frank D. Ferraiolo
IPC分类号： G05F3/26 , G05F3/20
CPC分类号： G05F3/262 , Y10S323/907
摘要： An integrated current reference circuit provides a current output with a predetermined temperature coefficient, suitably zero, to provide constant current over temperature variations. The circuit is formed of only Field Effect Transistors (FETs), allowing the circuit to be implemented using conventional CMOS fabrication techniques. A current mirror provides a reference current in both branches of the circuit. The output of the current mirror is coupled to a circuit providing an imbalance in resistance between the two branches, and an offsetting imbalance in voltages between the two branches, resulting in a reference current that has a predetermined temperature coefficient. An output current is provided which is proportional to the reference current and thus has the same temperature coefficient as the reference current.
摘要翻译：集成电流参考电路为电流输出提供预定的温度系数，适当地为零，以提供恒定电流超过温度变化。该电路仅由场效应晶体管（FET）形成，允许使用常规CMOS制造技术实现电路。电流镜在电路的两个分支中提供参考电流。电流镜的输出耦合到提供两个分支之间的电阻不平衡的电路和两个分支之间的电压的偏移不平衡，导致具有预定温度系数的参考电流。提供与参考电流成比例的输出电流，因此具有与参考电流相同的温度系数。

5. 发明授权

US5212716A Data edge phase sorting circuits 失效
标题翻译：数据边缘相位电路
公开(公告)号：US5212716A
公开(公告)日：1993-05-18
申请号：US650516
申请日：1991-02-05
申请人： Frank D. Ferraiolo , John E. Gersbach , Ilya I. Novof
发明人： Frank D. Ferraiolo , John E. Gersbach , Ilya I. Novof
IPC分类号： H03L7/06 , H03L7/081 , H04L7/033
CPC分类号： H04L7/0338 , H03L7/0814
摘要： Data edge phase sorting circuits for communication systems and information and data processing systems employing digital phase locked logic circuits. The sorting circuits phase sort edge transitions of a serial data stream relative to a local clock signal. The local clock signal is coupled to a delay line having a plurality of serially connected delay elements, each of which outputs a delay clock of different phase. The sorting circuit includes an extraction circuit coupled to receive the serial data stream for detecting edge transitions in the serial stream and outputting a pulse of predefined duration in response to each detected transition. Coupled to the extraction circuit output is a non-sequential logic circuit, which is also coupled to the local clock through the delay line. The non-sequential logic circuit combines the outputted extraction circuit pulse and the plurality of delay clocks for sorting the pulse relative to the delay clocks. Specific embodiments for the extraction circuit and non-sequential logic circuitry are depicted and described herein.

6. 发明授权

US5185768A Digital integrating clock extractor 失效
标题翻译：数字整合时钟提取器
公开(公告)号：US5185768A
公开(公告)日：1993-02-09
申请号：US594242
申请日：1990-10-09
申请人： Frank D. Ferraiolo , John E. Gersbach , Ilya I. Novof
发明人： Frank D. Ferraiolo , John E. Gersbach , Ilya I. Novof
IPC分类号： H04L7/02 , H04L7/033
CPC分类号： H04L7/0338
摘要： A digital integrating clock extraction technique for communication systems and information and data processing systems having high jitter and/or noise is disclosed. The technique is based on the integration and periodic analysis of a plurality of sorted data edge transitions of a received serial data stream. A retiming clock phase is selected from a plurality of locally generated clock signals of different phase. The retiming clock selection is preferably reevaluated after N data edge transition sorts. The resultant data edge histogram can be cumulative of all sorted transitions or merely cumulative of the last N sorted transitions. Corresponding methods and apparatus are described.

7. 发明授权

US5272729A Clock signal latency elimination network 失效
标题翻译：时钟信号延迟消除网络
公开(公告)号：US5272729A
公开(公告)日：1993-12-21
申请号：US763510
申请日：1991-09-20
申请人： Roland Bechade , Frank D. Ferraiolo , Bruce Kaufmann , Ilya I. Novof , Steven F. Oakland , Kenneth Shaw , Leon Skarshinski
发明人： Roland Bechade , Frank D. Ferraiolo , Bruce Kaufmann , Ilya I. Novof , Steven F. Oakland , Kenneth Shaw , Leon Skarshinski
IPC分类号： G06F1/10 , G11C11/407 , H03K5/00 , H03K5/135 , H03K5/15 , H04J3/06 , H04L7/033 , H04L7/00 , H04L25/36 , H04L25/40
CPC分类号： H03K5/1504 , G06F1/10
摘要： A process independent digital clock signal timing network is described for generating a chip clock substantially in phase with and offset by one cycle from an input clock signal. The timing network determines the delay experienced by a clock signal passing through a predetermined internal clock circuit on the chip and pregates the internal clock circuit by an amount equivalent to the determined delay such that the chip clock signal output from the internal clock circuitry lags the external clock signal input to the semiconductor chip by one cycle. Various timing network embodiments are described and claimed.
摘要翻译：描述了一种独立于过程的数字时钟信号定时网络，用于产生与输入时钟信号基本同相并偏移一个周期的芯片时钟。定时网络确定通过芯片上的预定内部时钟电路的时钟信号经历的延迟，并且将内部时钟电路预先相当于所确定的延迟量，使得从内部时钟电路输出的芯片时钟信号滞后于外部时钟信号输入到半导体芯片一个周期。描述和要求保护各种定时网络实施例。

8. 发明授权

US5870404A Self-timed circuit having critical path timing detection 失效
标题翻译：具有关键路径定时检测的自定时电路
公开(公告)号：US5870404A
公开(公告)日：1999-02-09
申请号：US694120
申请日：1996-08-08
申请人： Frank D. Ferraiolo , John E. Gersbach , Charles J. Masenas, Jr. , Norman J. Rohrer , Bruce W. Singer
发明人： Frank D. Ferraiolo , John E. Gersbach , Charles J. Masenas, Jr. , Norman J. Rohrer , Bruce W. Singer
IPC分类号： G06F1/08 , G06K5/04 , G11B5/00
CPC分类号： G06F1/08
摘要： A self-timed circuit for use a clocked logic system is disclosed that comprises a timing detection device for detecting a timing margin of a critical path, the critical path being a path that limits the speed of the system. The circuit further comprises increase logic for increasing the speed of the system clock if the timing margin allows it, and decrease logic for decreasing the speed of the system clock if the timing margin indicates such a need. The increase and decrease logic comprise threshold generator and reset logic, and clock control logic.
摘要翻译：公开了一种用于使用时钟逻辑系统的自定时电路，其包括用于检测关键路径的定时裕度的定时检测装置，该关键路径是限制系统速度的路径。该电路还包括用于增加系统时钟的速度的增加逻辑，如果定时裕度允许的话，并且如果定时裕度表示这样的需要，则降低用于降低系统时钟速度的逻辑。增加和减少逻辑包括阈值发生器和复位逻辑以及时钟控制逻辑。

9. 发明授权

US5635869A Current reference circuit 失效
标题翻译：电流参考电路
公开(公告)号：US5635869A
公开(公告)日：1997-06-03
申请号：US536222
申请日：1995-09-29
申请人： Frank D. Ferraiolo , John E. Gersbach , Ilya J. Novof , Edward J. Nowak
发明人： Frank D. Ferraiolo , John E. Gersbach , Ilya J. Novof , Edward J. Nowak
IPC分类号： G05F3/26 , G05F1/10
CPC分类号： G05F3/262
摘要： A constant-current generator circuit includes an output circuit and a control circuit, with the control circuit producing a control voltage to define a reference current through the output circuit. An important feature is that the control circuit uses a pair of transistors having different threshold voltages in generating the control voltage. The circuit is formed using CMOS technology, and the difference in threshold voltage may be produced by doping the polysilicon gate of an N-channel or P-channel field effect transistor. The step of doping to produce the change in threshold voltage is compatible with the standard processing for the CMOS device. In a preferred embodiment, the control circuit uses two pairs of control transistors, each pair having differing thresholds. One pair is P-channel and the other N-channel. These pairs are in parallel, the P-channel pair connected to the positive supply and the N-channel pair to the negative supply or ground. Each pair is connected in a cascode arrangement, producing two control voltages for two symmetrical output transistors in the output circuit, one N-channel and one P-channel.
摘要翻译：恒流发生器电路包括输出电路和控制电路，控制电路产生控制电压以限定通过输出电路的参考电流。一个重要的特征是控制电路在产生控制电压时使用具有不同阈值电压的一对晶体管。该电路使用CMOS技术形成，并且阈值电压的差异可以通过掺杂N沟道或P沟道场效应晶体管的多晶硅栅极产生。掺杂产生阈值电压变化的步骤与CMOS器件的标准处理兼容。在优选实施例中，控制电路使用两对控制晶体管，每对控制晶体管具有不同的阈值。一对是P通道和另一个N通道。这些对并联，P沟道对连接到正电源，N沟道对连接到负电源或地。每对以串联布置连接，为输出电路中的两个对称输出晶体管产生两个控制电压，一个N沟道和一个P沟道。

10. 发明授权

US08018837B2 Self-healing chip-to-chip interface 失效
标题翻译：自愈芯片到芯片的接口
公开(公告)号：US08018837B2
公开(公告)日：2011-09-13
申请号：US12635121
申请日：2009-12-10
申请人： Wiren D. Becker , Daniel M. Dreps , Frank D. Ferraiolo , Anand Haridass , Robert J. Reese
发明人： Wiren D. Becker , Daniel M. Dreps , Frank D. Ferraiolo , Anand Haridass , Robert J. Reese
IPC分类号： G01R31/08
CPC分类号： H01L22/22 , H01L2924/0002 , H01L2924/00
摘要： A method, apparatus, and computer instructions for managing a set of signal paths for a chip. A defective signal path within the set of signal paths for the chip is detected. Signals are re-routed through the set of signal paths such that the defective signal path is removed from the set of signal paths and sending signals using remaining data signal paths in the set of signal paths and using an extra signal path in response to detecting the defective signal path.
摘要翻译：一种用于管理用于芯片的一组信号路径的方法，装置和计算机指令。检测用于芯片的信号路径集合内的有缺陷的信号路径。信号通过一组信号路径重新路由，使得有缺陷的信号路径从信号路径集合中移除，并使用信号路径组中的剩余数据信号路径发送信号，并且响应于检测到的信号路径有缺陷的信号路径。

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