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1. 发明授权

US06198339B1 CVF current reference with standby mode 失效
标题翻译： CVF电流参考与待机模式
公开(公告)号：US06198339B1
公开(公告)日：2001-03-06
申请号：US08716503
申请日：1996-09-17
申请人： John E. Gersbach , Charles J. Masenas
发明人： John E. Gersbach , Charles J. Masenas
IPC分类号： G05F302
CPC分类号： G05F3/242
摘要： A switched capacitor current reference circuit with improved tolerance. Additional optional devices maintain an output in the absence or loss of an input frequency.
摘要翻译：开关电容电流参考电路，具有改进的公差。附加的可选设备在输入频率不存在或不存在的情况下保持输出。

2. 发明授权

US5870404A Self-timed circuit having critical path timing detection 失效
标题翻译：具有关键路径定时检测的自定时电路
公开(公告)号：US5870404A
公开(公告)日：1999-02-09
申请号：US694120
申请日：1996-08-08
申请人： Frank D. Ferraiolo , John E. Gersbach , Charles J. Masenas, Jr. , Norman J. Rohrer , Bruce W. Singer
发明人： Frank D. Ferraiolo , John E. Gersbach , Charles J. Masenas, Jr. , Norman J. Rohrer , Bruce W. Singer
IPC分类号： G06F1/08 , G06K5/04 , G11B5/00
CPC分类号： G06F1/08
摘要： A self-timed circuit for use a clocked logic system is disclosed that comprises a timing detection device for detecting a timing margin of a critical path, the critical path being a path that limits the speed of the system. The circuit further comprises increase logic for increasing the speed of the system clock if the timing margin allows it, and decrease logic for decreasing the speed of the system clock if the timing margin indicates such a need. The increase and decrease logic comprise threshold generator and reset logic, and clock control logic.
摘要翻译：公开了一种用于使用时钟逻辑系统的自定时电路，其包括用于检测关键路径的定时裕度的定时检测装置，该关键路径是限制系统速度的路径。该电路还包括用于增加系统时钟的速度的增加逻辑，如果定时裕度允许的话，并且如果定时裕度表示这样的需要，则降低用于降低系统时钟速度的逻辑。增加和减少逻辑包括阈值发生器和复位逻辑以及时钟控制逻辑。

3. 发明授权

US5694087A Anti-latching mechanism for phase lock loops 失效
标题翻译：锁相环锁止机构
公开(公告)号：US5694087A
公开(公告)日：1997-12-02
申请号：US592902
申请日：1996-01-29
申请人： Frank D. Ferraiolo , John E. Gersbach , Masayuki Hayashi , Ilya I. Novof , Charles J. Masenas, Jr.
发明人： Frank D. Ferraiolo , John E. Gersbach , Masayuki Hayashi , Ilya I. Novof , Charles J. Masenas, Jr.
IPC分类号： H03L7/10 , H03L7/093
CPC分类号： H03L7/10
摘要： A protective circuit for a phase lock loop ensures that the VCO does not initiate a runaway condition when outputting a signal having a frequency higher than the feedback divider can respond to. During normal phase lock operation, a counter keeps track of the PLL input signal and is reset by the feedback divider. In the runaway condition the counter is not reset and triggers a control signal to the VCO. A second counter can be used to keep track of the feedback divider output and to reset the first counter. When the first counter far outruns the second counter the control signal is triggered.
摘要翻译：用于锁相环的保护电路确保当输出具有高于反馈分配器的频率的信号可以响应时，VCO不会发起失控状况。在正常锁相操作期间，计数器跟踪PLL输入信号，并由反馈分频器复位。在失控状态下，计数器不复位，并触发VCO的控制信号。第二个计数器可用于跟踪反馈分频器输出并复位第一个计数器。当第一个计数器远远超出第二个计数器时，触发控制信号。

4. 发明授权

US5371766A Clock extraction and data regeneration logic for multiple speed data communications systems 失效
标题翻译：用于多速数据通信系统的时钟提取和数据再生逻辑
公开(公告)号：US5371766A
公开(公告)日：1994-12-06
申请号：US979121
申请日：1992-11-20
申请人： John E. Gersbach , Ilya I. Novof , Joseph K. Lee
发明人： John E. Gersbach , Ilya I. Novof , Joseph K. Lee
IPC分类号： H04L7/033 , H04L12/42 , H03D3/24
CPC分类号： H04L7/0337 , H04L12/422
摘要： Clock extraction and data regeneration logic is provided for a multiple rate digital data communications system such as a local area network (LAN). The logic is implemented in adapters which connect stations in the LAN to other stations in the LAN via transmission media such as wire or fiber optic cable. The clock extraction and data regeneration logic is adapted to quickly recognize the speed at which the token ring is operating, thereby preventing a station on the ring from sending data onto the ring at a rate which does not match the operating frequency of the ring. The logic also performs, at multiple speeds of operation, clock extraction and data reconstruction of a signal received from another station in the ring.
摘要翻译：为诸如局域网（LAN）的多速率数字数据通信系统提供时钟提取和数据再生逻辑。逻辑是通过适配器实现的，这些适配器通过诸如有线或光纤电缆的传输介质将LAN中的站与LAN中的其他站连接。时钟提取和数据再生逻辑适于快速识别令牌环操作的速度，从而防止环上的站以与环的工作频率不匹配的速率将数据发送到环上。该逻辑还在多个操作速度下执行从环中的另一个站接收的信号的时钟提取和数据重建。

5. 发明授权

US5873053A On-chip thermometry for control of chip operating temperature 失效
标题翻译：用于芯片工作温度的片上测温
公开(公告)号：US5873053A
公开(公告)日：1999-02-16
申请号：US841967
申请日：1997-04-08
申请人： Wilbur D. Pricer , Wendell P. Noble , John A. Fifield , John E. Gersbach
发明人： Wilbur D. Pricer , Wendell P. Noble , John A. Fifield , John E. Gersbach
IPC分类号： G01K7/01
CPC分类号： G01K7/01 , Y10S323/907
摘要： Temperatures on a chip, including particular regions of a chip are monitored by sensing changes in sub-threshold conduction of a field effect transistor (FET) integrated on the chip due to changes in charge carrier population distribution with temperature therein. Such changes in sub-threshold current with temperature are preferably detected using a current mirror and two FETs with different channel geometry and slightly different gate voltages such that the currents are equal at a specific design temperature. The slightly different gate voltages are conveniently provided by a low current voltage divider with or without on-chip voltage regulation in which resistor ratios can be accurately and repeatably obtained. Variations from that temperature thus yield large current differences and substantial signal swing which improve noise immunity. Hysteresis can be applied to the output (or amplified output) of the current mirror to obtain bistable thermostat-like action. Variant applications provide sensing at plural chip locations (e.g. for sensing temperature gradients and temperatures of autonomously operating portions of the chip) and a plurality of temperatures on the chip. Temperatures thus monitored control implementation of performance enhancing algorithms in regard to the chip.
摘要翻译：通过感测集成在芯片上的场效应晶体管（FET）的亚阈值传导的变化，由于载流子群体分布随温度的变化而监测芯片上包括芯片的特定区域的温度。亚阈值电流随温度的这种变化优选使用电流镜和具有不同通道几何形状和略微不同的栅极电压的两个FET来检测，使得电流在特定设计温度下是相等的。通过具有或不具有片内电压调节的低电流分压器可以方便地提供略微不同的栅极电压，其中可以精确和重复地获得电阻器比率。因此，该温度的变化产生大的电流差异和显着的信号摆动，这提高了抗噪声性。迟滞可应用于电流镜的输出（或放大输出），以获得双稳态恒温器状作用。变体应用提供在多个芯片位置处的感测（例如用于感测芯片的自主操作部分的温度梯度和温度）以及芯片上的多个温度。因此监控的温度控制了关于芯片的性能增强算法的实现。

6. 发明授权

US5635869A Current reference circuit 失效
标题翻译：电流参考电路
公开(公告)号：US5635869A
公开(公告)日：1997-06-03
申请号：US536222
申请日：1995-09-29
申请人： Frank D. Ferraiolo , John E. Gersbach , Ilya J. Novof , Edward J. Nowak
发明人： Frank D. Ferraiolo , John E. Gersbach , Ilya J. Novof , Edward J. Nowak
IPC分类号： G05F3/26 , G05F1/10
CPC分类号： G05F3/262
摘要： A constant-current generator circuit includes an output circuit and a control circuit, with the control circuit producing a control voltage to define a reference current through the output circuit. An important feature is that the control circuit uses a pair of transistors having different threshold voltages in generating the control voltage. The circuit is formed using CMOS technology, and the difference in threshold voltage may be produced by doping the polysilicon gate of an N-channel or P-channel field effect transistor. The step of doping to produce the change in threshold voltage is compatible with the standard processing for the CMOS device. In a preferred embodiment, the control circuit uses two pairs of control transistors, each pair having differing thresholds. One pair is P-channel and the other N-channel. These pairs are in parallel, the P-channel pair connected to the positive supply and the N-channel pair to the negative supply or ground. Each pair is connected in a cascode arrangement, producing two control voltages for two symmetrical output transistors in the output circuit, one N-channel and one P-channel.
摘要翻译：恒流发生器电路包括输出电路和控制电路，控制电路产生控制电压以限定通过输出电路的参考电流。一个重要的特征是控制电路在产生控制电压时使用具有不同阈值电压的一对晶体管。该电路使用CMOS技术形成，并且阈值电压的差异可以通过掺杂N沟道或P沟道场效应晶体管的多晶硅栅极产生。掺杂产生阈值电压变化的步骤与CMOS器件的标准处理兼容。在优选实施例中，控制电路使用两对控制晶体管，每对控制晶体管具有不同的阈值。一对是P通道和另一个N通道。这些对并联，P沟道对连接到正电源，N沟道对连接到负电源或地。每对以串联布置连接，为输出电路中的两个对称输出晶体管产生两个控制电压，一个N沟道和一个P沟道。

7. 发明授权

US5418484A Line fault detection system with a differential driver 失效
标题翻译：线路故障检测系统带差分驱动器
公开(公告)号：US5418484A
公开(公告)日：1995-05-23
申请号：US87825
申请日：1993-07-01
申请人： David W. Blum , John E. Gersbach
发明人： David W. Blum , John E. Gersbach
IPC分类号： H03K17/66 , H04L25/02 , H03K3/00 , H03K17/56 , H03K17/60
CPC分类号： H04L25/0272 , H03K17/661 , H04L25/028 , H04L25/0278 , H04L25/0292
摘要： This is a detector system comprised of a differential driver circuit, a driver output stage and splitter circuit and a multiplexor. The driver circuit employs a bridge circuit that converts input logic voltages to lower voltage differential outputs by utilizing a pair of current switch transistors coupled to the bridge circuit. The bridge circuit is comprised of cross coupled transistors whose inputs are coupled to matched true and complement input logic voltages that swing between zero volts and the power supply voltage. The bridge transistors convert the differential logic input voltage swings to smaller values that are compatible with driving the splitter and multiplexor circuits coupled thereto. The driver circuit and the splitter circuit share the driver output transistors which are arranged in parallel pairs. These pairs are coupled to respective output lines whose physical state is to be determined and to the multiplexor which is an emitter coupled switch coupled to emitter follower transistors which are, in turn, connected to respective output lines so that the output voltage of the output transistors can be used to determine if the output lines are open.
摘要翻译：这是由差分驱动器电路，驱动器输出级和分离器电路和多路复用器组成的检测器系统。驱动器电路采用桥式电路，其通过利用耦合到桥式电路的一对电流开关晶体管将输入逻辑电压转换为较低电压差分输出。桥式电路由交叉耦合晶体管组成，其输入耦合到在零伏特和电源电压之间摆动的匹配的真和补输入逻辑电压。桥式晶体管将差分逻辑输入电压摆幅转换为与驱动与其耦合的分路器和多路复用器电路兼容的较小值。驱动器电路和分离器电路共享并联布置的驱动器输出晶体管。这些对耦合到要确定其物理状态的相应输出线，并耦合到耦合到射极跟随器晶体管的发射极耦合开关的多路复用器，该发射极耦合开关又连接到相应的输出线，使得输出晶体管的输出电压可以用来确定输出线是否打开。

8. 发明授权

US5391935A Assertive latching flip-flop 失效
标题翻译：自信锁定触发器
公开(公告)号：US5391935A
公开(公告)日：1995-02-21
申请号：US96102
申请日：1993-07-22
申请人： John E. Gersbach , Paul W. Chung
发明人： John E. Gersbach , Paul W. Chung
IPC分类号： H03K3/02 , H03K3/037 , H03K3/286 , H03K3/2885 , H03K3/356 , H03K3/29
CPC分类号： H03K3/2885 , H03K3/0375
摘要： An assertive latching flip-flop circuit is provided which prevents the occurrence of metastable outputs. The circuit comprises a single flip-flop which is comprised of standard switching transistors which are switched by a clocking mechanism having no additionally introduced delay. The circuit includes an imbalancing element which is coupled to a latching portion of the circuit. The latching portion of the circuit comprises a pair of cross-coupled transistors, in current mode embodiments of the invention, or a pair of cross-coupled inverters, in voltage mode embodiments of the invention. The imbalancing element introduces an electrical disturbance on the input line to one of the latching transistors or inverters. The imbalancing element is a capacitor in voltage mode embodiments of the invention and an additional transistor in current mode embodiments.
摘要翻译：提供了一种断言闩锁触发器电路，其防止亚稳输出的发生。该电路包括单个触发器，该触发器由标准开关晶体管组成，该标准开关晶体管由没有额外引入的延迟的时钟机构切换。电路包括耦合到电路的锁存部分的不平衡元件。在本发明的电压模式实施例中，电路的锁存部分包括在本发明的电流模式实施例中的一对交叉耦合晶体管或一对交叉耦合的反相器。不平衡元件将输入线上的电气干扰引入到一个锁存晶体管或反相器。不平衡元件是本发明的电压模式实施例中的电容器和当前模式实施例中的附加晶体管。

9. 发明授权

US5245637A Phase and frequency adjustable digital phase lock logic system 失效
标题翻译：相位和频率可调数字锁相逻辑系统
公开(公告)号：US5245637A
公开(公告)日：1993-09-14
申请号：US815810
申请日：1991-12-30
申请人： John E. Gersbach , Ilya I. Novof
发明人： John E. Gersbach , Ilya I. Novof
IPC分类号： H03L7/081 , H04L7/033
CPC分类号： H04L7/0338 , H03L7/0814
摘要： A phase lock logic system is provided for (i) determining differences in phase and frequency of a received composite clock and data signal with respect to a local clock signal and (ii) providing control signals to enable accurate sampling and reconstruction of the received data. The system includes a delay element which outputs a plurality of phase-delayed signals each being incrementally shifted in phase from the local clock signal. A sorting circuit receives the phase-delayed local clock signals and the incoming composite signal, defines a number of time intervals in each cycle of the local clock signal equal to the number of phase-delayed local clock signals, and sorts positive and negative going transitions in the received composite signal into the defined time intervals. Counters indicate the number of transitions occurring during a selected time interval. A logic circuit reads the counters, determines the differences in frequency and phase of the received composite signal with respect to the local clock signal, and outputs first and second control signals. A barrel shifter responsive to the first control signal selects which of the counters counts the number of transitions occurring in a given time interval. A multiplexer responsive to the first and second control signals extracts the phase-delayed local clock signal which most closely approximates the phase and frequency of the received composite signal. A regenerator compares the extracted signal to the received composite signal and outputs regenerated data.
摘要翻译：提供了一种锁相逻辑系统，用于（i）确定接收到的复合时钟和数据信号相对于本地时钟信号的相位和频率的差异，以及（ii）提供控制信号以使接收数据的精确采样和重构。该系统包括延迟元件，该延迟元件输出多个相位延迟的信号，每个相位延迟的信号各自相对于本地时钟信号递增地移位。分类电路接收相位延迟的本地时钟信号和输入的复合信号，定义本地时钟信号的每个周期中的等于相位延迟的本地时钟信号的数量的时间间隔，并且对正和负的过渡转换在接收的复合信号中进入定义的时间间隔。计数器指示在所选时间间隔内发生的转换次数。逻辑电路读取计数器，确定接收到的复合信号相对于本地时钟信号的频率和相位差，并输出第一和第二控制信号。响应于第一控制信号的桶形移位器选择哪个计数器计数在给定时间间隔内发生的转换次数。响应于第一和第二控制信号的多路复用器提取最接近接收的复合信号的相位和频率的相位延迟本地时钟信号。再生器将所提取的信号与接收到的复合信号进行比较，并输出再生数据。

10. 发明授权

US5101203A Digital data regeneration and deserialization circuits 失效
标题翻译：数字数据再生和设计电路
公开(公告)号：US5101203A
公开(公告)日：1992-03-31
申请号：US546192
申请日：1990-06-29
申请人： John E. Gersbach , Ilya I. Novof
发明人： John E. Gersbach , Ilya I. Novof
IPC分类号： H03L7/06 , H03M9/00 , H04L7/00 , H04L29/00
CPC分类号： H03M9/00
摘要： A substantially simultaneous digital data regeneration and deserialization technique for communication systems and information and data processing systems is disclosed. A digital phase lock logic circuit (DPLL) receives the serial stream of clock and data bits at its input and outputs a plurality of clock signals with different phase. A plurality of latches are coupled to receive a respective one of the clock output signals from the DPLL. Each latch receives the serial stream of clock and data bits through a second input such that the latches are sequentially set by substantially simultaneously received clock and data information at the two inputs and the serial data bits within the stream appear as parallel data bits at the latch outputs. Enhanced versions of this circuit are also described, along with an alternate embodiment which uses an analog phase locked loop circuit.

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