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1. 发明授权

US06802945B2 Method of metal sputtering for integrated circuit metal routing 失效
标题翻译：金属溅射方法用于集成电路金属布线
公开(公告)号：US06802945B2
公开(公告)日：2004-10-12
申请号：US10336871
申请日：2003-01-06
申请人： Hsien-Tsung Liu , Chien-Kang Chou , Ching-San Lin
发明人： Hsien-Tsung Liu , Chien-Kang Chou , Ching-San Lin
IPC分类号： C23C1434
CPC分类号： C23C14/564 , C23C14/022 , H01L21/0206 , H01L21/2855 , H01L21/316 , H01L21/32051 , H01L24/11 , H01L2224/02126 , H01L2224/0231 , H01L2224/0401 , H01L2224/05166 , H01L2224/05644 , H01L2224/05647 , H01L2224/1147 , H01L2224/13099 , H01L2924/01005 , H01L2924/01013 , H01L2924/01018 , H01L2924/01022 , H01L2924/01024 , H01L2924/01025 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2924/00014 , H01L2924/013
摘要： A method of forming a device, comprising the following steps. A wafer holder and inner walls of a chamber are coated with a seasoning layer The wafer is placed upon the wafer holder and is cleaned wherein a portion of the seasoning layer is re-deposited upon the wafer over and between adjacent wafer conductive structures. The wafer is removed from the chamber and at least two adjacent upper metal structures are formed over at least one portion of a metal barrier layer. The exposed portions of the metal barrier layer are etched and removed, exposing portions of the re-deposited seasoning layer portions using the metal barrier layer etch process which also removes any exposed portions of the re-deposited seasoning layer portions that are comprised of a material etchable in the metal barrier layer etch process.
摘要翻译：一种形成装置的方法，包括以下步骤。晶片保持器和腔室的内壁涂覆有调味剂层。晶片被放置在晶片保持器上并且被清洁，其中一部分调味剂层被重新沉积在晶片上并在相邻的晶片导电结构之间。将晶片从腔室中取出，并且至少两个相邻的上部金属结构形成在金属阻挡层的至少一部分上。蚀刻和去除金属阻挡层的暴露部分，使用金属阻挡层蚀刻工艺暴露重新沉积的调节层部分的部分，其还去除由材料构成的再沉积调理层部分的任何暴露部分可在金属阻挡层蚀刻工艺中蚀刻。

2. 发明授权

US08723322B2 Method of metal sputtering for integrated circuit metal routing 有权
标题翻译：金属溅射方法用于集成电路金属布线
公开(公告)号：US08723322B2
公开(公告)日：2014-05-13
申请号：US11364375
申请日：2006-02-28
申请人： Hsien-Tsung Liu , Chien-Kang Chou , Ching-San Lin
发明人： Hsien-Tsung Liu , Chien-Kang Chou , Ching-San Lin
IPC分类号： H01L23/48
CPC分类号： C23C14/564 , C23C14/022 , H01L21/0206 , H01L21/2855 , H01L21/316 , H01L21/32051 , H01L24/11 , H01L2224/02126 , H01L2224/0231 , H01L2224/0401 , H01L2224/05166 , H01L2224/05644 , H01L2224/05647 , H01L2224/1147 , H01L2224/13099 , H01L2924/01005 , H01L2924/01013 , H01L2924/01018 , H01L2924/01022 , H01L2924/01024 , H01L2924/01025 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2924/00014 , H01L2924/013
摘要： A method of metal sputtering, comprising the following steps. A wafer holder and inner walls of a chamber are coated with a seasoning layer comprised of: a) a material etchable in a metal barrier layer etch process; or b) an insulating or non-conductive material. A wafer having two or more wafer conductive structures is placed upon the seasoning layer coated wafer holder. The wafer is cleaned wherein a portion of the seasoning layer is re-deposited upon the wafer over and between adjacent wafer conductive structures. A metal barrier layer is formed over the wafer. The wafer is removed from the chamber and at least two adjacent upper metal structures are formed over at least one portion of the metal barrier layer. The portions of the metal barrier layer not under the at least two adjacent upper metal structures are etched and removed from over the wafer exposing portions of the re-deposited seasoning layer portions using the metal barrier layer etch process which also removes any exposed portions of the re-deposited seasoning layer portions that are comprised of a material etchable in the metal barrier layer etch process.
摘要翻译：一种金属溅射方法，包括以下步骤。晶片保持器和室的内壁涂覆有调味层，调味层包括：a）可在金属阻挡层蚀刻工艺中蚀刻的材料; 或b）绝缘或非导电材料。将具有两个或更多个晶片导电结构的晶片放置在调味层涂覆的晶片保持器上。清洁晶片，其中一部分调味层在相邻的晶片导电结构之上和相邻的晶片导电结构之间重新沉积在晶片上。在晶片上形成金属阻挡层。将晶片从腔室中取出，并且在金属阻挡层的至少一部分上形成至少两个相邻的上部金属结构。金属阻挡层不在至少两个相邻的上部金属结构之下的部分被蚀刻并从晶片的上方移除，使用金属阻挡层蚀刻工艺暴露部分再沉积的调节层部分，其也去除了由金属阻挡层蚀刻工艺中可蚀刻的材料组成的再沉积的调味层部分。

3. 发明授权

US06583039B2 Method of forming a bump on a copper pad 有权
标题翻译：在铜垫上形成凸点的方法
公开(公告)号：US06583039B2
公开(公告)日：2003-06-24
申请号：US09978422
申请日：2001-10-15
申请人： Yen-Ming Chen , Kuo-Wei Lin , Cheng-Yu Chu , Yang-Tung Fan , Fu-Jier Fan , Shih-Jane Lin , Chiou-Shian Peng , Hsien-Tsung Liu
发明人： Yen-Ming Chen , Kuo-Wei Lin , Cheng-Yu Chu , Yang-Tung Fan , Fu-Jier Fan , Shih-Jane Lin , Chiou-Shian Peng , Hsien-Tsung Liu
IPC分类号： H01L2144
CPC分类号： H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/03019 , H01L2224/03912 , H01L2224/0401 , H01L2224/05558 , H01L2224/05572 , H01L2224/1147 , H01L2224/11849 , H01L2224/11912 , H01L2224/13099 , H01L2224/131 , H01L2924/0001 , H01L2924/0002 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/30105 , H01L2924/30107 , H01L2924/00014 , H01L2224/05552
摘要： A method of forming a bump overlying the copper based contact pad to prevent oxidation of the copper based contact pad. A passivation blanket is deposited over a semiconductor device having a copper based contact pad, the passivation blanket includes a first layer overlying the top surface; a second layer overlying the first layer; a portion of the second layer overlying the copper based contact pad is removed leaving the first layer in place; depositing an under bump metallurgy over the semiconductor device, a portion of the first layer overlying the copper based contact pad is removed so that the copper based contact pad has limited exposure to oxygen; depositing an under bump metallurgy over the semiconductor device; removing excess under bump metallurgy; depositing an electrically conductive material over the under bump metallurgy; reflowing electrically conductive material to form a bump overlying the copper based contact pad.
摘要翻译：一种形成覆盖铜基接触垫的凸起以防止铜基接触垫氧化的方法。钝化覆盖层沉积在具有铜基接触焊盘的半导体器件上，钝化层包括覆盖在顶表面上的第一层; 覆盖第一层的第二层; 去除覆盖铜基接触垫的第二层的一部分，留下第一层就位; 在半导体器件上沉积凸块下的冶金，去除覆盖在铜基接触焊盘上的第一层的一部分，使得铜基接触焊盘具有有限的暴露于氧气; 在所述半导体器件上沉积凸块下的冶金; 去除多余的突起冶金; 在凸块下冶金上沉积导电材料; 回流导电材料以形成覆盖铜基接触垫的凸块。

4. 发明授权

US5180689A Tapered opening sidewall with multi-step etching process 失效
标题翻译：锥形开口侧壁采用多步蚀刻工艺
公开(公告)号：US5180689A
公开(公告)日：1993-01-19
申请号：US757135
申请日：1991-09-10
申请人： Hsien-Tsung Liu , Jin-Yuan Lee , Jiann-Kwang Wang , Chue-San Yoo , Pei-Jan Wang
发明人： Hsien-Tsung Liu , Jin-Yuan Lee , Jiann-Kwang Wang , Chue-San Yoo , Pei-Jan Wang
IPC分类号： H01L21/768
CPC分类号： H01L21/76804
摘要： A method is described for making a tapered opening for an integrated circuit having a feature size of about one micrometer or less which will in due course be filled with a metallurgy conductor. An integrated circuit structure is provided having device elements within a semiconductor substrate and multilayer insulating layers thereover. A resist masking layer is formed over the said multilayer insulating layer having openings therein in the areas where the said openings are desired. The multilayer insulating layer is anisotropically etched through a first thickness to form a first opening using the resist masking layer as a mask. A second thickness portion of the multilayer insulating layer is isotropically etched to substantially uniformly enlarge and taper the first opening while using the unchanged resist layer. The remaining thickness of the multilayer insulating layer is anisotropically etched through to the semiconductor substrate to form the desirable tapered opening with a metal step coverage improvement over the state of the art between about 20 to 60%. Metal step coverage is defined as the ratio of thickness of the thinnest metal in the contact hole to the metal thickness on the horizontal area. The resist layer mask is removed.
摘要翻译：描述了一种用于制造具有约1微米或更小的特征尺寸的集成电路的锥形开口的方法，其将在适当的时候被冶金导体填充。提供了一种集成电路结构，其具有半导体衬底内的器件元件及其上的多层绝缘层。在需要所述开口的区域中，在其上具有开口的所述多层绝缘层上形成抗蚀剂掩模层。多层绝缘层通过第一厚度进行各向异性蚀刻，以形成使用抗蚀剂掩模层作为掩模的第一开口。多层绝缘层的第二厚度部分被各向同性地蚀刻，以在使用未改变的抗蚀剂层的同时大致均匀地放大和渐缩第一开口。将多层绝缘层的剩余厚度各向异性地蚀刻到半导体衬底上以形成期望的锥形开口，其中的现有技术的金属级覆盖改善在约20％至60％之间。金属台阶覆盖率定义为接触孔中最薄金属的厚度与水平面上的金属厚度之比。去除抗蚀剂层掩模。

5. 发明授权

US06083790A Method for making y-shaped multi-fin stacked capacitors for dynamic random access memory cells 有权
标题翻译：制造用于动态随机存取存储器单元的y形多片堆叠电容器的方法
公开(公告)号：US06083790A
公开(公告)日：2000-07-04
申请号：US248728
申请日：1999-02-11
申请人： Yo-Sheng Lin , Hsien-Tsung Liu
发明人： Yo-Sheng Lin , Hsien-Tsung Liu
IPC分类号： H01L21/02 , H01L21/8242 , H01L21/70
CPC分类号： H01L27/10855 , H01L28/87 , H01L27/10885
摘要： An array of DRAM cells having Y-shaped multi-fin stacked capacitors with increased capacitance is achieved. A planar first insulating layer is formed over the semi-conductor devices on the substrate. Polycide bit lines are formed on the first insulating layer, and a second insulating layer and a silicon nitride (Si.sub.3 N.sub.4) etch-stop layer are conformally deposited. A multilayer, composed of a alternating insulating and polysilicon layers, is conformally deposited over the bit lines. Capacitor node contact openings are etched in the multilayer and in the underlying layers to the substrate. A fourth polysilicon layer is deposited sufficiently thick to fill the node contact openings and to form the node contacts. The multilayer is then patterned to leave portions over the node contacts, and an isotropic etch is used to remove the insulating layers exposed in the sidewalls of the patterned multilayer to provide Y-shaped multi-fin capacitor bottom electrodes over the bit lines. These Y-shaped multi-fin capacitors increase the capacitance by 37% over T-shaped multi-fin capacitors. The DRAM capacitors are then completed by forming an interelectrode dielectric layer on the bottom electrodes and by depositing a fifth polysilicon layer to form the capacitor top electrodes.
摘要翻译：实现了具有增加的电容的具有Y形多翅片叠层电容器的DRAM单元的阵列。平面的第一绝缘层形成在衬底上的半导体器件上。多晶硅位线形成在第一绝缘层上，第二绝缘层和氮化硅（Si 3 N 4）蚀刻停止层共形沉积。由交替的绝缘和多晶硅层组成的多层共形沉积在位线上。电容器节点接触开口在多层中并在下层中蚀刻到衬底上。沉积足够厚的第四多晶硅层以填充节点接触开口并形成节点接触。然后将多层图案化以在节点接触件上留下部分，并且使用各向同性蚀刻来去除暴露在图案化多层的侧壁中的绝缘层，以在位线上提供Y形多鳍电容器底部电极。这些Y形多片式电容器比T形多片式电容器增加了37％的电容。然后通过在底部电极上形成电极间电介质层并通过沉积第五多晶硅层以形成电容器顶部电极来完成DRAM电容器。

6. 发明申请

US20050186690A1 Method for improving semiconductor wafer test accuracy 审中-公开
标题翻译：提高半导体晶圆测试精度的方法
公开(公告)号：US20050186690A1
公开(公告)日：2005-08-25
申请号：US10786807
申请日：2004-02-25
申请人： Hui-Mei Chen , Chien-Kang Chou , Jin-Yuan Lee , Hsien-Tsung Liu
发明人： Hui-Mei Chen , Chien-Kang Chou , Jin-Yuan Lee , Hsien-Tsung Liu
IPC分类号： G01R3/00 , H01L21/66
CPC分类号： G01R3/00
摘要： A method for improving the accuracy of electrical test results of semiconductor wafers is described. The method introduces a non-contacting physical cleaning process prior to testing. The cleaning process removes micro-contamination on circuit contact pads that has been introduced during semiconductor wafer processing. This results in more accurate electrical probing of the semiconductor wafers.
摘要翻译：描述了一种用于提高半导体晶片的电气测试结果精度的方法。该方法在测试之前引入了非接触式物理清洁过程。清洁过程消除了在半导体晶片处理期间引入的电路接触焊盘上的微污染。这导致半导体晶片的更准确的电探测。

7. 发明申请

US20060148247A1 Method of metal sputtering for integrated circuit metal routing 有权
标题翻译：金属溅射方法用于集成电路金属布线
公开(公告)号：US20060148247A1
公开(公告)日：2006-07-06
申请号：US11364375
申请日：2006-02-28
申请人： Hsien-Tsung Liu , Chien-Kang Chou , Ching-San Lin
发明人： Hsien-Tsung Liu , Chien-Kang Chou , Ching-San Lin
IPC分类号： H01L21/4763
CPC分类号： C23C14/564 , C23C14/022 , H01L21/0206 , H01L21/2855 , H01L21/316 , H01L21/32051 , H01L24/11 , H01L2224/02126 , H01L2224/0231 , H01L2224/0401 , H01L2224/05166 , H01L2224/05644 , H01L2224/05647 , H01L2224/1147 , H01L2224/13099 , H01L2924/01005 , H01L2924/01013 , H01L2924/01018 , H01L2924/01022 , H01L2924/01024 , H01L2924/01025 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2924/00014 , H01L2924/013
摘要： A method of metal sputtering, comprising the following steps. A wafer holder and inner walls of a chamber are coated with a seasoning layer comprised of: a) a material etchable in a metal barrier layer etch process; or b) an insulating or non-conductive material. A wafer having two or more wafer conductive structures is placed upon the seasoning layer coated wafer holder. The wafer is cleaned wherein a portion of the seasoning layer is re-deposited upon the wafer over and between adjacent wafer conductive structures. A metal barrier layer is formed over the wafer. The wafer is removed from the chamber and at least two adjacent upper metal structures are formed over at least one portion of the metal barrier layer. The portions of the metal barrier layer not under the at least two adjacent upper metal structures are etched and removed from over the wafer exposing portions of the re-deposited seasoning layer portions using the metal barrier layer etch process which also removes any exposed portions of the re-deposited seasoning layer portions that are comprised of a material etchable in the metal barrier layer etch process.
摘要翻译：一种金属溅射方法，包括以下步骤。晶片保持器和室的内壁涂覆有调味层，调味层包括：a）可在金属阻挡层蚀刻工艺中蚀刻的材料; 或b）绝缘或非导电材料。将具有两个或更多个晶片导电结构的晶片放置在调味层涂覆的晶片保持器上。清洁晶片，其中一部分调味层在相邻的晶片导电结构之上和相邻的晶片导电结构之间重新沉积在晶片上。在晶片上形成金属阻挡层。将晶片从腔室中取出，并且在金属阻挡层的至少一部分上形成至少两个相邻的上部金属结构。金属阻挡层不在至少两个相邻的上部金属结构之下的部分被蚀刻并从晶片的上方移除，使用金属阻挡层蚀刻工艺暴露部分再沉积的调节层部分，其也去除了由金属阻挡层蚀刻工艺中可蚀刻的材料组成的再沉积的调味层部分。

8. 发明申请

US20050040033A1 Method of metal sputtering for integrated circuit metal routing 审中-公开
标题翻译：金属溅射方法用于集成电路金属布线
公开(公告)号：US20050040033A1
公开(公告)日：2005-02-24
申请号：US10954781
申请日：2004-09-30
申请人： Hsien-Tsung Liu , Chien-Kang Chou , Ching-San Lin
发明人： Hsien-Tsung Liu , Chien-Kang Chou , Ching-San Lin
IPC分类号： C23C14/02 , C23C14/56 , H01L21/316 , H01L21/3205 , H01L21/60 , C23C14/32
CPC分类号： C23C14/564 , C23C14/022 , H01L21/0206 , H01L21/2855 , H01L21/316 , H01L21/32051 , H01L24/11 , H01L2224/02126 , H01L2224/0231 , H01L2224/0401 , H01L2224/05166 , H01L2224/05644 , H01L2224/05647 , H01L2224/1147 , H01L2224/13099 , H01L2924/01005 , H01L2924/01013 , H01L2924/01018 , H01L2924/01022 , H01L2924/01024 , H01L2924/01025 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2924/00014 , H01L2924/013
摘要： A method of metal sputtering, comprising the following steps. A wafer holder and inner walls of a chamber are coated with a seasoning layer comprised of: a) a material etchable in a metal barrier layer etch process; or b) an insulating or non-conductive material. A wafer having two or more wafer conductive structures is placed upon the seasoning layer coated wafer holder. The wafer is cleaned wherein a portion of the seasoning layer is re-deposited upon the wafer over and between adjacent wafer conductive structures. A metal barrier layer is formed over the wafer. The wafer is removed from the chamber and at least two adjacent upper metal structures are formed over at least one portion of the metal barrier layer. The portions of the metal barrier layer not under the at least two adjacent upper metal structures are etched and removed from over the wafer exposing portions of the re-deposited seasoning layer portions using the metal barrier layer etch process which also removes any exposed portions of the re-deposited seasoning layer portions that are comprised of a material etchable in the metal barrier layer etch process.
摘要翻译：一种金属溅射方法，包括以下步骤。晶片保持器和室的内壁涂覆有调味层，调味层包括：a）可在金属阻挡层蚀刻工艺中蚀刻的材料; 或b）绝缘或非导电材料。将具有两个或更多个晶片导电结构的晶片放置在调味层涂覆的晶片保持器上。清洁晶片，其中一部分调味层在相邻的晶片导电结构之上和相邻的晶片导电结构之间重新沉积在晶片上。在晶片上形成金属阻挡层。将晶片从腔室中取出，并且在金属阻挡层的至少一部分上形成至少两个相邻的上部金属结构。金属阻挡层不在至少两个相邻的上部金属结构之下的部分被蚀刻并从晶片的上方移除，使用金属阻挡层蚀刻工艺暴露部分再沉积的调节层部分，其也去除了由金属阻挡层蚀刻工艺中可蚀刻的材料组成的再沉积的调味层部分。

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