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1. 发明授权

US08742580B2 Method of wire bonding over active area of a semiconductor circuit 有权
标题翻译：在半导体电路的有源区上引线键合的方法
公开(公告)号：US08742580B2
公开(公告)日：2014-06-03
申请号：US11678600
申请日：2007-02-25
申请人： Jin-Yuan Lee , Ying-Chih Chen , Mou-Shiung Lin
发明人： Jin-Yuan Lee , Ying-Chih Chen , Mou-Shiung Lin
IPC分类号： H01L23/48
CPC分类号： H01L24/48 , H01L24/03 , H01L24/05 , H01L2224/02166 , H01L2224/04042 , H01L2224/05073 , H01L2224/05166 , H01L2224/05171 , H01L2224/05187 , H01L2224/05548 , H01L2224/05556 , H01L2224/05558 , H01L2224/05624 , H01L2224/05644 , H01L2224/45144 , H01L2224/4807 , H01L2224/48453 , H01L2224/48463 , H01L2224/48599 , H01L2224/48624 , H01L2224/48644 , H01L2224/48647 , H01L2224/854 , H01L2224/85424 , H01L2224/85444 , H01L2224/85447 , H01L2924/00014 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/05042 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/04953 , H01L2224/45099 , H01L2924/00 , H01L2924/00012
摘要： A method and structure are provided to enable wire bond connections over active and/or passive devices and/or low-k dielectrics, formed on an Integrated Circuit die. A semiconductor substrate having active and/or passive devices is provided, with interconnect metallization formed over the active and/or passive devices. A passivation layer formed over the interconnect metallization is provided, wherein openings are formed in the passivation layer to an upper metal layer of the interconnect metallization. Compliant metal bond pads are formed over the passivation layer, wherein the compliant metal bond pads are connected through the openings to the upper metal layer, and wherein the compliant metal bond pads are formed substantially over the active and/or passive devices. The compliant metal bond pads may be formed of a composite metal structure.
摘要翻译：提供了一种方法和结构，以在集成电路管芯上形成的有源和/或无源器件和/或低k电介质上实现引线接合连接。提供了具有有源和/或无源器件的半导体衬底，其中在有源和/或无源器件上形成互连金属化。提供了形成在互连金属化之上的钝化层，其中在钝化层中形成开口以形成互连金属化的上金属层。柔性金属焊盘形成在钝化层上方，其中柔性金属接合焊盘通过开口连接到上金属层，并且其中柔性金属接合焊盘基本上形成在有源和/或无源器件的上方。顺应性金属接合焊盘可以由复合金属结构形成。

2. 发明授权

US08492900B2 Post passivation interconnection schemes on top of IC chip 有权
公开(公告)号：US08492900B2
公开(公告)日：2013-07-23
申请号：US11856074
申请日：2007-09-17
申请人： Mou-Shiung Lin , Jin-Yuan Lee
发明人： Mou-Shiung Lin , Jin-Yuan Lee
IPC分类号： H01L23/48
CPC分类号： H01L23/60 , H01L21/768 , H01L21/76801 , H01L21/76838 , H01L23/5222 , H01L23/5223 , H01L23/5227 , H01L23/5283 , H01L23/5286 , H01L23/5329 , H01L23/53295 , H01L23/62 , H01L24/05 , H01L27/0248 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/3011 , H01L2924/00
摘要： A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.

3. 发明授权

US08482127B2 Post passivation interconnection schemes on top of IC chip 有权
公开(公告)号：US08482127B2
公开(公告)日：2013-07-09
申请号：US11856073
申请日：2007-09-17
申请人： Mou-Shiung Lin , Jin-Yuan Lee
发明人： Mou-Shiung Lin , Jin-Yuan Lee
IPC分类号： H01L23/48
CPC分类号： H01L23/60 , H01L21/768 , H01L21/76801 , H01L21/76838 , H01L23/5222 , H01L23/5223 , H01L23/5227 , H01L23/5283 , H01L23/5286 , H01L23/5329 , H01L23/53295 , H01L23/62 , H01L24/05 , H01L27/0248 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/3011 , H01L2924/00
摘要： A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.

4. 发明授权

US08471388B2 Integrated circuit and method for fabricating the same 有权
标题翻译：集成电路及其制造方法
公开(公告)号：US08471388B2
公开(公告)日：2013-06-25
申请号：US13197630
申请日：2011-08-03
申请人： Mou-Shiung Lin , Jin-Yuan Lee
发明人： Mou-Shiung Lin , Jin-Yuan Lee
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L23/3192 , H01L24/11 , H01L2224/05001 , H01L2224/05008 , H01L2224/05022 , H01L2224/05024 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05164 , H01L2224/05166 , H01L2224/05169 , H01L2224/05171 , H01L2224/05181 , H01L2224/05184 , H01L2224/05186 , H01L2224/05572 , H01L2224/05647 , H01L2224/05655 , H01L2924/09701 , H01L2924/1305 , H01L2924/14 , H01L2924/15787 , H01L2924/15788 , H01L2924/19041 , H01L2924/00 , H01L2924/00014 , H01L2924/013 , H01L2924/04953
摘要： A method for fabricating an integrated circuit (IC) chip includes forming a metal trace having a thickness of between 5 μm and 27 μm over a semiconductor substrate, and forming a passivation layer on the metal trace, wherein the passivation layer includes a layer of silicon nitride on the metal trace and a layer of silicon oxide on the layer of silicon nitride, or includes a layer of silicon oxynitride on the metal trace and a layer of silicon oxide on the layer of silicon oxynitride.
摘要翻译：一种用于制造集成电路（IC）芯片的方法，包括在半导体衬底上形成厚度在5μm和27μm之间的金属迹线，并在金属迹线上形成钝化层，其中该钝化层包括一层硅金属迹线上的氮化物和氮化硅层上的氧化硅层，或者在金属迹线上包括氮氧化硅层和氮氧化硅层上的氧化硅层。

5. 发明授权

US08426982B2 Structure and manufacturing method of chip scale package 有权
公开(公告)号：US08426982B2
公开(公告)日：2013-04-23
申请号：US12512073
申请日：2009-07-30
申请人： Jin-Yuan Lee , Ching-Cheng Huang , Mou-Shiung Lin
发明人： Jin-Yuan Lee , Ching-Cheng Huang , Mou-Shiung Lin
IPC分类号： H01L23/02 , H01L23/48
CPC分类号： H01L23/293 , H01L23/3114 , H01L23/49827 , H01L24/10 , H01L24/13 , H01L24/48 , H01L24/81 , H01L2224/05124 , H01L2224/05155 , H01L2224/05599 , H01L2224/05647 , H01L2224/13 , H01L2224/13099 , H01L2224/13111 , H01L2224/45099 , H01L2224/48091 , H01L2224/48227 , H01L2224/81801 , H01L2224/85399 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01075 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2924/00012
摘要： A Chip Scale Package (CSP) and a method of forming the same are disclosed. Single chips without the conventional ball mountings, are first attached to an adhesive-substrate (adsubstrate) composite having openings that correspond to the input/output (I/O) pads on the single chips to form a composite chip package. Ball mounting is then performed over the openings, thus connecting the I/O pads at the chip sites to the next level of packaging directly. In another embodiment, the adhesive layer is formed on the wafer side first to form an adwafer, which is then die sawed in CSPs. Then the CSPs with the adhesive already on them are bonded to a substrate. The composite chip package may optionally be encapsulated with a molding material. The CSPs provide integrated and shorter chip connections especially suited for high frequency circuit applications, and can leverage the currently existing test infrastructure.

6. 发明授权

US08373202B2 Integrated circuit chips with fine-line metal and over-passivation metal 有权
标题翻译：集成电路芯片与细线金属和过钝化金属
公开(公告)号：US08373202B2
公开(公告)日：2013-02-12
申请号：US11864931
申请日：2007-09-29
申请人： Mou-Shiung Lin , Jin-Yuan Lee , Chien-Kang Chou
发明人： Mou-Shiung Lin , Jin-Yuan Lee , Chien-Kang Chou
IPC分类号： H01L23/52 , H01L23/528 , H01L21/70
CPC分类号： H01L23/552 , H01L21/76816 , H01L21/76873 , H01L23/5283 , H01L23/5286 , H01L23/53238 , H01L23/5329 , H01L24/05 , H01L24/11 , H01L24/45 , H01L24/48 , H01L24/73 , H01L27/0251 , H01L2224/02166 , H01L2224/0231 , H01L2224/0401 , H01L2224/04042 , H01L2224/05572 , H01L2224/05624 , H01L2224/05647 , H01L2224/05664 , H01L2224/1148 , H01L2224/13022 , H01L2224/13099 , H01L2224/16145 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/48463 , H01L2224/48624 , H01L2224/48647 , H01L2224/48664 , H01L2224/48724 , H01L2224/48747 , H01L2224/48764 , H01L2224/48824 , H01L2224/48847 , H01L2224/48864 , H01L2224/73257 , H01L2224/73265 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01011 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01044 , H01L2924/01045 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01083 , H01L2924/01322 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/09701 , H01L2924/10253 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/15311 , H01L2924/15787 , H01L2924/15788 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/01039 , H01L2924/00 , H01L2224/05552
摘要： An integrated circuit chip includes a silicon substrate, a first circuit in or over said silicon substrate, a second circuit device in or over said silicon substrate, a dielectric structure over said silicon substrate, a first interconnecting structure in said dielectric structure, a first pad connected to said first node of said voltage regulator through said first interconnecting structure, a second interconnecting structure in said dielectric structure, a second pad connected to said first node of said internal circuit through said second interconnecting structure, a passivation layer over said dielectric structure, wherein multiple opening in said passivation layer exposes said first and second pads, and a third interconnecting structure over said passivation layer and over said first and second pads.
摘要翻译：集成电路芯片包括硅衬底，位于所述硅衬底中或之上的第一电路，位于所述硅衬底中或之上的第二电路器件，所述硅衬底上的电介质结构，所述电介质结构中的第一互连结构，第一衬垫通过所述第一互连结构连接到所述电压调节器的所述第一节点，所述电介质结构中的第二互连结构，通过所述第二互连结构连接到所述内部电路的所述第一节点的第二焊盘，所述电介质结构上的钝化层，其中所述钝化层中的多个开口暴露所述第一和第二焊盘，以及在所述钝化层上方以及所述第一和第二焊盘之上的第三互连结构。

7. 发明授权

US08211791B2 Method for fabricating circuitry component 有权
标题翻译：电路元件制造方法
公开(公告)号：US08211791B2
公开(公告)日：2012-07-03
申请号：US10382699
申请日：2003-03-05
申请人： Mou-Shiung Lin , Jin-Yuan Lee , Ching-Cheng Huang
发明人： Mou-Shiung Lin , Jin-Yuan Lee , Ching-Cheng Huang
IPC分类号： H01L21/4763 , H01L21/44
CPC分类号： H01L21/76838 , H01L21/768 , H01L21/76807 , H01L23/5286 , H01L23/5329 , H01L23/60 , H01L2924/0002 , H01L2924/00
摘要： A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the first dielectric body and is electrically connected to the electric devices. The first interconnection scheme is constructed from first metal layers and plugs, wherein the neighboring first metal layers are electrically connected through the plugs. The passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the passivation layer. The second built-up layer is provided with a second dielectric body and a second interconnection scheme, wherein the second interconnection scheme interlaces inside the second dielectric body and is electrically connected to the first interconnection scheme. The second interconnection scheme is constructed from at least one second metal layer and at least one via metal filler, wherein the second metal layer is electrically connected to the via metal filler. The thickness, width, and cross-sectional area of the traces of the second metal layer are respectively larger than those of the first metal layers.
摘要翻译：芯片结构包括基板，第一堆叠层，钝化层和第二堆积层。基板包括放置在基板的表面上的许多电气装置。第一组合层位于基底上。第一组合层设置有第一电介质体和第一互连方案，其中第一互连方案与第一介电体内部交错并电连接到电气装置。第一互连方案由第一金属层和插塞构成，其中相邻的第一金属层通过插塞电连接。钝化层设置在第一堆叠层上并且设有暴露第一互连方案的开口。第二堆叠层形成在钝化层上。第二组合层设置有第二电介质体和第二互连方案，其中第二互连方案在第二介电体内部交织并与第一互连方案电连接。第二互连方案由至少一个第二金属层和至少一个通孔金属填料构成，其中第二金属层电连接到通孔金属填料。第二金属层的迹线的厚度，宽度和横截面积分别大于第一金属层的厚度，宽度和横截面面积。

8. 发明授权

US08193555B2 Image and light sensor chip packages 有权
标题翻译：图像和光传感器芯片封装
公开(公告)号：US08193555B2
公开(公告)日：2012-06-05
申请号：US12703139
申请日：2010-02-09
申请人： Mou-Shiung Lin , Jin-Yuan Lee
发明人： Mou-Shiung Lin , Jin-Yuan Lee
IPC分类号： H01L33/00
CPC分类号： H01L31/0203 , H01L24/45 , H01L27/14618 , H01L27/14621 , H01L27/14627 , H01L27/14632 , H01L2224/32245 , H01L2224/45015 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/73265 , H01L2224/8592 , H01L2924/01015 , H01L2924/01047 , H01L2924/12042 , H01L2924/13091 , H01L2924/1461 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/20751 , H01L2924/00012
摘要： An image or light sensor chip package includes an image or light sensor chip having a non-photosensitive area and a photosensitive area surrounded by the non-photosensitive area. In the photosensitive area, there are light sensors, a layer of optical or color filter array over the light sensors and microlenses over the layer of optical or color filter array. In the non-photosensitive area, there are an adhesive polymer layer and multiple metal structures having a portion in the adhesive polymer layer. A transparent substrate is formed on a top surface of the adhesive polymer layer and over the microlenses. The image or light sensor chip package also includes wirebonded wires or a flexible substrate bonded with the metal structures of the image or light sensor chip.
摘要翻译：图像或光传感器芯片封装包括具有非感光区域和由非感光区域包围的感光区域的图像或光传感器芯片。在感光区域中有光传感器，光学或彩色滤光片阵列在光传感器和光学或彩色滤光片阵列上的微透镜之上。在非感光区域中，粘合聚合物层和粘合聚合物层中具有一部分的多个金属结构体。在粘合聚合物层的顶表面上并在微透镜上形成透明基底。图像或光传感器芯片封装还包括引线键合线或与图像或光传感器芯片的金属结构接合的柔性基板。

9. 发明授权

US08164171B2 System-in packages 有权
标题翻译：系统包装
公开(公告)号：US08164171B2
公开(公告)日：2012-04-24
申请号：US12779863
申请日：2010-05-13
申请人： Mou-Shiung Lin , Jin-Yuan Lee
发明人： Mou-Shiung Lin , Jin-Yuan Lee
IPC分类号： H01L23/02
CPC分类号： H01L25/0657 , H01L23/49816 , H01L23/5383 , H01L23/5384 , H01L23/5385 , H01L23/5389 , H01L24/24 , H01L24/45 , H01L24/82 , H01L24/96 , H01L25/0652 , H01L25/0655 , H01L25/50 , H01L2224/04105 , H01L2224/12105 , H01L2224/24137 , H01L2224/24145 , H01L2224/24226 , H01L2224/32225 , H01L2224/32245 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48465 , H01L2224/73204 , H01L2224/73267 , H01L2224/8203 , H01L2224/92244 , H01L2225/06513 , H01L2225/06517 , H01L2225/06524 , H01L2225/06541 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01023 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01044 , H01L2924/01045 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/09701 , H01L2924/10253 , H01L2924/10329 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/15311 , H01L2924/15787 , H01L2924/15788 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19107 , H01L2924/20751 , H01L2924/20752 , H01L2924/20753 , H01L2924/20754 , H01L2924/30105 , H01L2924/3025 , H01L2924/00
摘要： System-in packages, or multichip modules, are described which can include multi-layer chips in a multi-layer polymer structure, on-chip metal bumps on the multi-layer chips, intra-chip metal bumps in the multi-layer polymer structure, and patterned metal layers in the multi-layer polymer structure. The multi-layer chips in the multi-layer polymer structure can be connected to each other or to an external circuit through the on-chip metal bumps, the intra-chip metal bumps and the patterned metal layers. The system-in packages can be connected to external circuits through solder bumps, meal bumps or wirebonded wires.
摘要翻译：描述了系统包装或多芯片模块，其可以包括多层聚合物结构中的多层芯片，多层芯片上的片上金属凸块，多层聚合物结构中的片内金属凸块，以及多层聚合物结构中的图案化金属层。多层聚合物结构中的多层芯片可以通过片上金属凸块，片内金属凸块和图案化金属层彼此连接或连接到外部电路。系统包装可以通过焊料凸块，餐具凸点或引线键合线连接到外部电路。

10. 发明授权

US08035227B2 Top layers of metal for high performance IC's 有权
标题翻译：高性能IC的金属顶层
公开(公告)号：US08035227B2
公开(公告)日：2011-10-11
申请号：US12138455
申请日：2008-06-13
申请人： Mou-Shiung Lin , Jin-Yuan Lee
发明人： Mou-Shiung Lin , Jin-Yuan Lee
IPC分类号： H01L23/522
CPC分类号： H01L21/768 , H01L21/76804 , H01L21/76807 , H01L21/76838 , H01L23/522 , H01L23/5222 , H01L23/5223 , H01L23/5225 , H01L23/5227 , H01L23/5228 , H01L23/525 , H01L23/5283 , H01L23/5286 , H01L23/5329 , H01L23/53295 , H01L23/60 , H01L24/11 , H01L24/12 , H01L27/0676 , H01L27/08 , H01L28/10 , H01L28/20 , H01L2224/0231 , H01L2224/02311 , H01L2224/02313 , H01L2224/0401 , H01L2224/1148 , H01L2224/13099 , H01L2224/16225 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01018 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/12044 , H01L2924/14 , H01L2924/15174 , H01L2924/15184 , H01L2924/15192 , H01L2924/15311 , H01L2924/15787 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H01L2924/3025 , H01L2924/351 , H01L2924/00
摘要： The present invention adds one or more thick layers of polymer dielectric and one or more layers of thick, wide metal lines on top of a finished semiconductor wafer, post-passivation. The thick, wide metal lines may be used for long signal paths and can also be used for power buses or power planes, clock distribution networks, critical signal, and re-distribution of I/O pads for flip chip applications. Photoresist defined electroplating, sputter/etch, or dual and triple damascene techniques are used for forming the metal lines and via fill.
摘要翻译：本发明在完成的半导体晶片的顶部上添加一层或多层厚的聚合物电介质和一层或多层厚的宽金属线，后钝化。厚的宽金属线路可用于长信号路径，也可用于电源总线或电源平面，时钟分配网络，关键信号和用于倒装芯片应用的I / O焊盘的重新分配。光刻胶定义的电镀，溅射/蚀刻或双重和三重镶嵌技术用于形成金属线和通孔填充。

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