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1. 发明申请

US20070233959A1 Data processor having cache memory 审中-公开
公开(公告)号：US20070233959A1
公开(公告)日：2007-10-04
申请号：US11802944
申请日：2007-05-29
申请人： Takashi Hotta , Toshihiko Kurihara , Shigeya Tanaka , Hideo Sawamoto , Akiyoshi Osumi , Koji Saito , Kotaro Shimamura
发明人： Takashi Hotta , Toshihiko Kurihara , Shigeya Tanaka , Hideo Sawamoto , Akiyoshi Osumi , Koji Saito , Kotaro Shimamura
IPC分类号： G06F12/00
CPC分类号： G06F12/0897 , G06F12/0846 , G06F12/0862 , G06F12/0864 , G06F2212/6028
摘要： A data processor has a first cache memory with a large capacity and one port and a second cache memory with a small capacity and two ports disposed between a main memory and an instruction processing section. Data which is frequently used is stored in the first cache memory and data which is less frequently used is stored in the second cache memory under control of a controller responsive to prefetch instructions. One of the cache memories may be a set associative cache memory composed of a plurality of memory chips each having at least two memory banks and an output part to gain access to data sets consecutively and one at a time within the memory banks. On the basis of an address sent from the instruction processing section, a memory bank is selected, and a data set from the selected memory bank is supplied to the processing section.

2. 发明申请

US20050102472A1 Data processor having cache memory 失效
公开(公告)号：US20050102472A1
公开(公告)日：2005-05-12
申请号：US11014885
申请日：2004-12-20
申请人： Takashi Hotta , Toshihiko Kurihara , Shigeya Tanaka , Hideo Sawamoto , Akiyoshi Osumi , Koji Saito , Kotaro Shimamura
发明人： Takashi Hotta , Toshihiko Kurihara , Shigeya Tanaka , Hideo Sawamoto , Akiyoshi Osumi , Koji Saito , Kotaro Shimamura
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0897 , G06F12/0846 , G06F12/0862 , G06F12/0864 , G06F2212/6028
摘要： A data processor has a first cache memory with a large capacity and one port and a second cache memory with a small capacity and two ports disposed between a main memory and an instruction processing section. Data which is frequently used is stored in the first cache memory and data which is less frequently used is stored in the second cache memory under control of a controller responsive to prefetch instructions. One of the cache memories may be a set associative cache memory composed of a plurality of memory chips each having at least two memory banks and an output part to gain access to data sets consecutively and one at a time within the memory banks. On the basis of an address sent from the instruction processing section, a memory bank is selected, and a data set from the selected memory bank is supplied to the processing section.

3. 发明授权

US5426751A Information processing apparatus with address extension function 失效
标题翻译：具有地址扩展功能的信息处理设备
公开(公告)号：US5426751A
公开(公告)日：1995-06-20
申请号：US153612
申请日：1993-11-17
申请人： Hideo Sawamoto
发明人： Hideo Sawamoto
IPC分类号： G06F9/34 , G06F12/02 , G06F12/06 , G06F12/10 , G06F12/00
CPC分类号： G06F12/1036 , G06F12/0292
摘要： An information processing apparatus with an address extension function includes a set of address adders for performing address addition with respect to a first fraction of an address for an instruction and/or a data, which fraction corresponds to the not extended bit portion of the address, and a set of domain registers for storing a second fraction of the address for an instruction or an operand, which fraction corresponds to the extended bit portion of the address. If address extension is not made, address translation into a real address is performed using a virtual address obtained through addition operation by the address adder and in accordance with a conventional not address extended program. If address extension is made, address translation into a real address is performed using a virtual address obtained by concatinating the addition result by the address adder with the content of the domain register.
摘要翻译：具有地址扩展功能的信息处理装置包括一组地址加法器，用于相对于指令的地址的第一部分和/或数据执行地址相加，该部分对应于地址的未扩展位部分，以及用于存储用于指令或操作数的地址的第二部分的一组域寄存器，该部分对应于地址的扩展位部分。如果不进行地址扩展，则使用通过地址加法器的加法运算获得的虚拟地址，并根据常规的非地址扩展程序来执行地址转换为实际地址。如果进行地址扩展，则使用通过地址加法器将相加结果与域寄存器的内容相加而获得的虚拟地址来执行地址转换为实际地址。

4. 发明授权

US5392409A I/O execution method for a virtual machine system and system therefor 失效
标题翻译：用于虚拟机系统及其系统的I / O执行方法
公开(公告)号：US5392409A
公开(公告)日：1995-02-21
申请号：US851629
申请日：1992-03-16
申请人： Hidenori Umeno , Takashige Kubo , Nobutaka Hagiwara , Hiroaki Sato , Hideo Sawamoto , Taro Inoue , Shunji Tanaka
发明人： Hidenori Umeno , Takashige Kubo , Nobutaka Hagiwara , Hiroaki Sato , Hideo Sawamoto , Taro Inoue , Shunji Tanaka
IPC分类号： G06F9/455 , G06F13/10 , G06F12/00
CPC分类号： G06F13/10 , G06F9/45558 , G06F2009/45579 , G06F2009/45583
摘要： In a computer system having a central processing unit, a main storage and at least one I/O device, a plurality of operating systems (OS) can simultaneously run under the control of a control program. For executing an I/O instruction using a central processing unit, a plurality of resident areas of said main storage which do not overlap one another are assigned, under the control of the control program, to the plurality of OSs as main memories therefore, respectively. In responding to an I/O instruction issued by a running one of said plural OSs, an address of said main memory assigned to said running OS which participates in an I/Oo operation requested by said I/O instruction is determined without intervention of the control program, and the address is translated into an address of the main storage of the computer system without intervention of said control program. The I/O operation is then executed by using the address resulting from said address translation.
摘要翻译：在具有中央处理单元，主存储器和至少一个I / O设备的计算机系统中，多个操作系统（OS）可以在控制程序的控制下同时运行。为了使用中央处理单元执行I / O指令，在控制程序的控制下，分别将不相互重叠的所述主存储器的多个驻留区域分别作为主存储器分配给作为主存储器的多个OS 。在响应由所述多个OS中运行的一个OS发出的I / O指令时，确定分配给所述运行OS的所述主存储器的参与I / O指令请求的I / Oo操作的地址，控制程序，并且该地址被转换成计算机系统的主存储器的地址，而不需要所述控制程序的干预。然后通过使用由所述地址转换产生的地址来执行I / O操作。

5. 发明授权

US5317710A Invalidation of entries in a translation table by providing the machine a unique identification thereby disallowing a match and rendering the entries invalid 失效
标题翻译：通过为机器提供唯一的标识，从而不允许匹配并使条目无效，使转换表中条目无效
公开(公告)号：US5317710A
公开(公告)日：1994-05-31
申请号：US681446
申请日：1991-04-03
申请人： Mari Ara , Hideo Sawamoto , Ryo Yamagata
发明人： Mari Ara , Hideo Sawamoto , Ryo Yamagata
IPC分类号： G06F9/46 , G06F12/10 , G06F12/02 , G06F7/04
CPC分类号： G06F12/1036
摘要： A virtual computer system having a translation lookaside buffer which converts a virtual address to a real address comprises a register (VMNR) for storing the identification number (VMID) of a currently running virtual machine, the translation lookaside buffer having a bit for holding the VMID and a comparison circuit which compares the VMID held in the bit with the VMID provided by the VMNR and predicates the success of conversion from a virtual address to a real address on the basis of a matching result of comparison, a management table for holding data indicative of VMIDs used to define virtual machines which have run up to the current time point, and a control circuit which, when an invalidation command for the translation lookaside buffer is issued during a run of a virtual machine, selects an unused VMID as first information for defining the running virtual machine on the basis of the contents of the management table and sets the selected VMID in the VMNR.
摘要翻译：具有将虚拟地址转换为实际地址的翻译后备缓冲器的虚拟计算机系统包括用于存储当前正在运行的虚拟机的标识号（VMID）的寄存器（VMNR），具有用于保存VMID的位的转换后备缓冲器以及比较电路，其将保持在该比特中的VMID与由VMNR提供的VMID进行比较，并且基于比较的匹配结果来确定从虚拟地址到真实地址的转换的成功;用于保存数据的管理表用于定义已经运行到当前时间点的虚拟机的VMID;以及控制电路，当在虚拟机的运行期间发出用于翻译后备缓冲器的无效命令时，选择未使用的VMID作为第一信息，根据管理表的内容定义正在运行的虚拟机，并在VMNR中设置选定的VMID。

6. 发明授权

US5291445A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US5291445A
公开(公告)日：1994-03-01
申请号：US589515
申请日：1990-09-28
申请人： Shuuichi Miyaoka , Kazuhisa Miyamoto , Masanori Odaka , Hideo Sawamoto , Michiaki Nakayama , Mitsugu Kusunoki , Masato Ikeda , Takashi Ogata , Kouji Kobayashi , Masao Kato , Tsutomu Sumimoto
发明人： Shuuichi Miyaoka , Kazuhisa Miyamoto , Masanori Odaka , Hideo Sawamoto , Michiaki Nakayama , Mitsugu Kusunoki , Masato Ikeda , Takashi Ogata , Kouji Kobayashi , Masao Kato , Tsutomu Sumimoto
IPC分类号： H03K19/0175 , H03K19/0944 , G11C7/00
CPC分类号： H03K19/017527 , H03K19/017518 , H03K19/09448
摘要： A semiconductor integrated circuit device such as a memory device with logic function comprises a plurality of RAM macrocells and gate arrays. The RAM macrocells are constituted by bipolar CMOS RAMs having a total memory capacity of at least 100 kilobits, and the gate arrays contain at least 4000 gates. The logic circuits in the memory device with logic function or the like are constructed by selectively combining CMOS, bipolar CMOS or ECL gate circuits depending on the output load capacity, transmission characteristic requirement, power dissipation and required layout area. The level of signals at various circuits is set to the ECL level or MOS level depending on the local circuit configuration and other factors. The memory device further incorporates sequence control circuits required to be installed downstream of buffer storages of computers.
摘要翻译：诸如具有逻辑功能的存储器件的半导体集成电路器件包括多个RAM宏单元和门阵列。 RAM宏单元由具有至少100千位的总存储器容量的双极性CMOS RAM构成，并且门阵列包含至少4000个栅极。具有逻辑功能等的存储器件中的逻辑电路通过根据输出负载能力，传输特性要求，功耗和所需布局面积选择性地组合CMOS，双极CMOS或ECL门电路而构成。各种电路的信号电平根据本地电路配置和其他因素设置为ECL电平或MOS电平。存储器装置还包括需要安装在计算机的缓冲存储器下游的顺序控制电路。

7. 发明授权

US5023777A Information processing system using domain table address extension for address translation without software modification 失效
标题翻译：信息处理系统使用域表地址扩展进行地址转换，无需软件修改
公开(公告)号：US5023777A
公开(公告)日：1991-06-11
申请号：US252815
申请日：1988-10-03
申请人： Hideo Sawamoto
发明人： Hideo Sawamoto
IPC分类号： G06F9/34 , G06F12/02 , G06F12/06 , G06F12/10
CPC分类号： G06F12/1036 , G06F12/0292
摘要： An information processing apparatus with an address extension function includes a set of address adders for performing address addition with respect to a first fraction of an address for an instruction and/or a data, which fraction corresponds to the not extended bit portion of the address, and a set of domain registers for storing a second fraction of the address for an instruction or an operand, which fraction corresponds to the extended bit portion of the address. If address extension is not made, address translation into a real address is performed using a virtual address obtained through addition operation by the address adder and in accordance with a conventional not address extended program. If address extension is made, address translation into a real address is performed using a virtual address obtained by concatinating the addition result by the address adder with the content of the domain register.
摘要翻译：具有地址扩展功能的信息处理装置包括一组地址加法器，用于相对于指令的地址的第一部分和/或数据执行地址相加，该部分对应于地址的未扩展位部分，以及用于存储用于指令或操作数的地址的第二部分的一组域寄存器，该部分对应于地址的扩展位部分。如果不进行地址扩展，则使用通过地址加法器的加法运算获得的虚拟地址，并根据常规的非地址扩展程序来执行地址转换为实际地址。如果进行地址扩展，则使用通过地址加法器将相加结果与域寄存器的内容相加而获得的虚拟地址来执行地址转换为实际地址。

8. 发明授权

US4999770A Command controlled multi-storage space protection key pretesting system permitting access regardless of test result if selected key is predetermined value 失效
标题翻译：命令控制的多存储空间保护密钥预测试系统允许访问，不管测试结果如果选择的密钥是预定值
公开(公告)号：US4999770A
公开(公告)日：1991-03-12
申请号：US84092
申请日：1987-08-11
申请人： Mari Ara , Hideo Sawamoto , Kaname Imai
发明人： Mari Ara , Hideo Sawamoto , Kaname Imai
IPC分类号： G06F12/10 , G06F12/14
CPC分类号： G06F12/1475
摘要： A multi-address space control for use in a information processing system includes accessing a plurality of address spaces produced by different address translation table based on a selection command for a plurality of first address registers, and comparing a program status word key with a main storage key in a main storage to protect the main storage. The multi-address space control between different address spaces includes a PSW key register for holding the program status word key, a work access key register capable of arbitrarily designating an access key in accordance with a data transfer instruction, access apparatus for allowing an access to the main storage irrespective of the value of a main storage key when the value of the key selected by a selector as an access key from the work access key register and the PSW key register is a predetermined value, and setting apparatus for accessing the different address spaces by changing-over the plurality of leading address registers and the work access key register and PSW register, detecting an access exception, and setting the predetermined value in the work access key register to judge the work access key as an access key if an access exception is not detected.
摘要翻译：用于信息处理系统的多地址空间控制包括基于多个第一地址寄存器的选择命令访问由不同的地址转换表产生的多个地址空间，以及将程序状态字键与主存储器键入主存储以保护主存储。不同地址空间之间的多地址空间控制包括用于保存程序状态字键的PSW密钥寄存器，能够根据数据传送指令任意指定访问密钥的工作访问密钥寄存器，用于允许访问当从由工作访问键寄存器和PSW密钥寄存器作为访问键的选择器选择的密钥的值是预定值时，与主存储密钥的值无关的主存储器，以及用于访问不同地址的设置设备通过切换多个前导地址寄存器和工作访问密钥寄存器和PSW寄存器，检测访问异常，并且将工作访问密钥寄存器中的预定值设置为将访问密钥判断为访问密钥，如果访问未检测到异常。

9. 发明授权

US5384738A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US5384738A
公开(公告)日：1995-01-24
申请号：US189636
申请日：1994-02-01
申请人： Shuuichi Miyaoka , Kazuhisa Miyamoto , Masanori Odaka , Hideo Sawamoto , Michiaki Nakayama , Mitsugu Kusunoki , Masato Ikeda , Takashi Ogata , Kouji Kobayashi , Masao Kato , Tsutomu Sumimoto
发明人： Shuuichi Miyaoka , Kazuhisa Miyamoto , Masanori Odaka , Hideo Sawamoto , Michiaki Nakayama , Mitsugu Kusunoki , Masato Ikeda , Takashi Ogata , Kouji Kobayashi , Masao Kato , Tsutomu Sumimoto
IPC分类号： H03K19/0175 , H03K19/0944 , G11C7/00
CPC分类号： H03K19/017527 , H03K19/017518 , H03K19/09448
摘要： A semiconductor integrated circuit device such as a memory device with logic function comprises a plurality of RAM macrocells and gate arrays. The RAM macrocells are constituted by bipolar CMOS RAMs having a total memory capacity of at least 100 kilobits, and the gate arrays contain at least 4000 gates. The logic circuits in the memory device with logic function or the like are constructed by selectively combining CMOS, bipolar CMOS or ECL gate circuits depending on the output load capacity, transmission characteristic requirement, power dissipation and required layout area. The level of signals at various circuits is set to the ECL level or MOS level depending on the local circuit configuration and other factors. The memory device further incorporates sequence control circuits required to be installed downstream of buffer storages of computers.
摘要翻译：诸如具有逻辑功能的存储器件的半导体集成电路器件包括多个RAM宏单元和门阵列。 RAM宏单元由具有至少100千位的总存储器容量的双极性CMOS RAM构成，并且门阵列包含至少4000个栅极。具有逻辑功能等的存储器件中的逻辑电路通过根据输出负载能力，传输特性要求，功耗和所需布局面积选择性地组合CMOS，双极CMOS或ECL门电路而构成。各种电路的信号电平根据本地电路配置和其他因素设置为ECL电平或MOS电平。存储器装置还包括需要安装在计算机的缓冲存储器下游的顺序控制电路。

10. 发明授权

US5305458A Multiple virtual storage system and address control apparatus having a designation table holding device and translation buffer 失效
标题翻译：多个虚拟存储系统和地址控制装置具有指定表保持装置和转换缓冲器
公开(公告)号：US5305458A
公开(公告)日：1994-04-19
申请号：US518411
申请日：1990-05-02
申请人： Yukihiro Motomura , Hideki Takeuchi , Hideo Sawamoto , Mari Ara
发明人： Yukihiro Motomura , Hideki Takeuchi , Hideo Sawamoto , Mari Ara
IPC分类号： G06F12/10 , G06F12/02 , G06F12/00
CPC分类号： G06F12/0292
摘要： In a multiple virtual storage system and more particularly in an address control apparatus, there are provided two kinds of holding devices a designation holding device for holding a segment table designations in association with access registers and a translation buffer for holding translation pairs of the access register and segment table designation. With this arrangement, the segment table designation designating the virtual address space possessing an operand of an instruction can be supplied quickly and efficiently.
摘要翻译：在多虚拟存储系统中，特别是在地址控制装置中，提供了两种保持装置：用于保存与访问寄存器相关联的分段表名称的指定保存装置和用于保存访问寄存器的转换对的转换缓冲器和分段表指定。通过这种布置，可以快速有效地提供指定具有指令的操作数的虚拟地址空间的段表指定。

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