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1. 发明授权

US5317710A Invalidation of entries in a translation table by providing the machine a unique identification thereby disallowing a match and rendering the entries invalid 失效
标题翻译：通过为机器提供唯一的标识，从而不允许匹配并使条目无效，使转换表中条目无效
公开(公告)号：US5317710A
公开(公告)日：1994-05-31
申请号：US681446
申请日：1991-04-03
申请人： Mari Ara , Hideo Sawamoto , Ryo Yamagata
发明人： Mari Ara , Hideo Sawamoto , Ryo Yamagata
IPC分类号： G06F9/46 , G06F12/10 , G06F12/02 , G06F7/04
CPC分类号： G06F12/1036
摘要： A virtual computer system having a translation lookaside buffer which converts a virtual address to a real address comprises a register (VMNR) for storing the identification number (VMID) of a currently running virtual machine, the translation lookaside buffer having a bit for holding the VMID and a comparison circuit which compares the VMID held in the bit with the VMID provided by the VMNR and predicates the success of conversion from a virtual address to a real address on the basis of a matching result of comparison, a management table for holding data indicative of VMIDs used to define virtual machines which have run up to the current time point, and a control circuit which, when an invalidation command for the translation lookaside buffer is issued during a run of a virtual machine, selects an unused VMID as first information for defining the running virtual machine on the basis of the contents of the management table and sets the selected VMID in the VMNR.
摘要翻译：具有将虚拟地址转换为实际地址的翻译后备缓冲器的虚拟计算机系统包括用于存储当前正在运行的虚拟机的标识号（VMID）的寄存器（VMNR），具有用于保存VMID的位的转换后备缓冲器以及比较电路，其将保持在该比特中的VMID与由VMNR提供的VMID进行比较，并且基于比较的匹配结果来确定从虚拟地址到真实地址的转换的成功;用于保存数据的管理表用于定义已经运行到当前时间点的虚拟机的VMID;以及控制电路，当在虚拟机的运行期间发出用于翻译后备缓冲器的无效命令时，选择未使用的VMID作为第一信息，根据管理表的内容定义正在运行的虚拟机，并在VMNR中设置选定的VMID。

2. 发明授权

US5305458A Multiple virtual storage system and address control apparatus having a designation table holding device and translation buffer 失效
标题翻译：多个虚拟存储系统和地址控制装置具有指定表保持装置和转换缓冲器
公开(公告)号：US5305458A
公开(公告)日：1994-04-19
申请号：US518411
申请日：1990-05-02
申请人： Yukihiro Motomura , Hideki Takeuchi , Hideo Sawamoto , Mari Ara
发明人： Yukihiro Motomura , Hideki Takeuchi , Hideo Sawamoto , Mari Ara
IPC分类号： G06F12/10 , G06F12/02 , G06F12/00
CPC分类号： G06F12/0292
摘要： In a multiple virtual storage system and more particularly in an address control apparatus, there are provided two kinds of holding devices a designation holding device for holding a segment table designations in association with access registers and a translation buffer for holding translation pairs of the access register and segment table designation. With this arrangement, the segment table designation designating the virtual address space possessing an operand of an instruction can be supplied quickly and efficiently.
摘要翻译：在多虚拟存储系统中，特别是在地址控制装置中，提供了两种保持装置：用于保存与访问寄存器相关联的分段表名称的指定保存装置和用于保存访问寄存器的转换对的转换缓冲器和分段表指定。通过这种布置，可以快速有效地提供指定具有指令的操作数的虚拟地址空间的段表指定。

3. 发明授权

US4999770A Command controlled multi-storage space protection key pretesting system permitting access regardless of test result if selected key is predetermined value 失效
标题翻译：命令控制的多存储空间保护密钥预测试系统允许访问，不管测试结果如果选择的密钥是预定值
公开(公告)号：US4999770A
公开(公告)日：1991-03-12
申请号：US84092
申请日：1987-08-11
申请人： Mari Ara , Hideo Sawamoto , Kaname Imai
发明人： Mari Ara , Hideo Sawamoto , Kaname Imai
IPC分类号： G06F12/10 , G06F12/14
CPC分类号： G06F12/1475
摘要： A multi-address space control for use in a information processing system includes accessing a plurality of address spaces produced by different address translation table based on a selection command for a plurality of first address registers, and comparing a program status word key with a main storage key in a main storage to protect the main storage. The multi-address space control between different address spaces includes a PSW key register for holding the program status word key, a work access key register capable of arbitrarily designating an access key in accordance with a data transfer instruction, access apparatus for allowing an access to the main storage irrespective of the value of a main storage key when the value of the key selected by a selector as an access key from the work access key register and the PSW key register is a predetermined value, and setting apparatus for accessing the different address spaces by changing-over the plurality of leading address registers and the work access key register and PSW register, detecting an access exception, and setting the predetermined value in the work access key register to judge the work access key as an access key if an access exception is not detected.
摘要翻译：用于信息处理系统的多地址空间控制包括基于多个第一地址寄存器的选择命令访问由不同的地址转换表产生的多个地址空间，以及将程序状态字键与主存储器键入主存储以保护主存储。不同地址空间之间的多地址空间控制包括用于保存程序状态字键的PSW密钥寄存器，能够根据数据传送指令任意指定访问密钥的工作访问密钥寄存器，用于允许访问当从由工作访问键寄存器和PSW密钥寄存器作为访问键的选择器选择的密钥的值是预定值时，与主存储密钥的值无关的主存储器，以及用于访问不同地址的设置设备通过切换多个前导地址寄存器和工作访问密钥寄存器和PSW寄存器，检测访问异常，并且将工作访问密钥寄存器中的预定值设置为将访问密钥判断为访问密钥，如果访问未检测到异常。

4. 发明授权

US5499379A Input/output execution apparatus for a plural-OS run system 失效
标题翻译：多OS运行系统的输入输出执行装置
公开(公告)号：US5499379A
公开(公告)日：1996-03-12
申请号：US8842
申请日：1993-01-25
申请人： Shunji Tanaka , Toru Ohtsuki , Hiroaki Sato , Hideo Sawamoto , Ryo Yamagata , Masaya Watanabe , Hidenori Umeno , Masatoshi Haraguchi
发明人： Shunji Tanaka , Toru Ohtsuki , Hiroaki Sato , Hideo Sawamoto , Ryo Yamagata , Masaya Watanabe , Hidenori Umeno , Masatoshi Haraguchi
IPC分类号： G06F13/10 , G06F9/318 , G06F9/455 , G06F9/46 , G06F9/48 , G06F9/00
CPC分类号： G06F9/3017 , G06F9/45558 , G06F9/4812 , G06F2009/45579
摘要： A plural-OS run system in which a plurality of operating systems (OSs) capable of operating on machines of different architectures, respectively, are allowed to run on one bare machine under the control of one control program (CP) or one control means. The input/output instruction and input/output interrupt of the operating system capable of running on a machine of the same architecture as that of the bare machine are directly executed on the bare machine without need for translation of the format. The input/output instruction and the input/output interrupt of the operating system adapted to run on a machine of the architecture differing from that of the bare machine are allowed to be directly executed while translating the format.
摘要翻译：一种多操作系统运行系统，其中可以在一个控制程序（CP）或一个控制装置的控制下，分别在不同架构的机器上操作的多个操作系统（OS）在一个裸机上运行。能够在与裸机相同架构的机器上运行的操作系统的输入/输出指令和输入/输出中断在裸机上直接执行，无需转换格式。允许在转换格式的同时直接执行适用于与裸机机架不同的架构的机器上运行的操作系统的输入/输出指令和输入/输出中断。

5. 发明授权

US5129071A Address translation apparatus in virtual machine system using a space identifier field for discriminating DATOFF (dynamic address translation off) virtual machines 失效
标题翻译：虚拟机系统中的地址转换装置，使用空间识别器字段来区分DATOFF（动态地址转换关闭）虚拟机
公开(公告)号：US5129071A
公开(公告)日：1992-07-07
申请号：US331756
申请日：1989-04-03
申请人： Ryo Yamagata , Hideo Sawamoto , Hidenori Umeno
发明人： Ryo Yamagata , Hideo Sawamoto , Hidenori Umeno
IPC分类号： G06F9/46 , G06F12/10
CPC分类号： G06F12/1036
摘要： An address translation apparatus is provided which has an address translation look-aside buffer with an entry composed of a real address field, virtual machine identifier field and space identifier field. For the translation look-aside buffer entry to be used by a general virtual machine which uses a plurality of address spaces, a virtual machine identifier for discrimination of a general virtual machine is stored in the virtual machine identifier field, and information used in discriminating an address space is stored in the space identifier field. For the translation look-aside buffer entry to be used by a dynamic address translation off (DATOFF virtual) machine which uses a single address space, an identifier commonly assigned to a group of DATOFF virtual machines is stored in the virtual machine identifier field, and a control block address used in discriminating a DATOFF virtual machine is stored in the space identifier field.
摘要翻译：提供了一种地址转换装置，其具有地址转换后备缓冲器，其具有由实际地址字段，虚拟机标识符字段和空格标识符字段组成的条目。对于由使用多个地址空间的通用虚拟机使用的翻译后备缓冲器条目，用于识别一般虚拟机的虚拟机标识符存储在虚拟机标识符字段中，并且用于区分地址空间存储在空间标识符字段中。对于使用单个地址空间的动态地址转换（DATOFF virtual）机器使用的翻译后备缓冲器条目，通常分配给一组DATOFF虚拟机的标识符存储在虚拟机标识符字段中，并且用于区分DATOFF虚拟机的控制块地址被存储在空间标识符字段中。

6. 发明授权

US06275902B1 Data processor with variable types of cache memories and a controller for selecting a cache memory to be access 失效
标题翻译：具有可变类型的高速缓存存储器的数据处理器和用于选择要访问的高速缓冲存储器的控制器
公开(公告)号：US06275902B1
公开(公告)日：2001-08-14
申请号：US09188693
申请日：1998-11-10
申请人： Takashi Hotta , Toshihiko Kurihara , Shigeya Tanaka , Hideo Sawamoto , Akiyoshi Osumi , Koji Saito , Kotaro Shimamura
发明人： Takashi Hotta , Toshihiko Kurihara , Shigeya Tanaka , Hideo Sawamoto , Akiyoshi Osumi , Koji Saito , Kotaro Shimamura
IPC分类号： G06F1208
CPC分类号： G06F12/0897 , G06F12/0846 , G06F12/0862 , G06F12/0864 , G06F2212/6028
摘要： A data processor has a first cache memory with a large capacity and one port and a second cache memory with a small capacity and two ports disposed between a main memory and an instruction processing section. Data which is frequently used is stored in the first cache memory and data which is less frequently used is stored in the second cache memory under control of a controller responsive to prefetch instructions. One of the cache memories may be a set associative cache memory composed of a plurality of memory chips each having at least two memory banks and an output part to gain access to data sets consecutively and one at a time within the memory banks. On the basis of an address sent from the instruction processing section, a memory bank is selected, and a data set from the selected memory bank is supplied to the processing section.
摘要翻译：数据处理器具有大容量的第一高速缓冲存储器和一个端口，具有小容量的第二缓存存储器和设置在主存储器和指令处理部件之间的两个端口。经常使用的数据被存储在第一高速缓冲存储器中，并且在响应于预取指令的控制器的控制下，较不频繁使用的数据被存储在第二高速缓冲存储器中。高速缓存存储器中的一个可以是由多个存储器芯片构成的组合的相关高速缓冲存储器，每个存储器芯片具有至少两个存储器组，以及输出部分，以连续地访问数据集，并且一个在存储器组内一次。基于从指令处理部分发送的地址，选择存储体，并且将从所选择的存储体组中提取的数据提供给处理部分。

7. 发明授权

US6101596A Information processor for performing processing without register conflicts 失效
标题翻译：用于执行无注册冲突的处理的信息处理器
公开(公告)号：US6101596A
公开(公告)日：2000-08-08
申请号：US894924
申请日：1997-09-03
申请人： Shigeya Tanaka , Kotaro Shimamura , Tetsuya Shimomura , Takashi Hotta , Hideo Sawamoto
发明人： Shigeya Tanaka , Kotaro Shimamura , Tetsuya Shimomura , Takashi Hotta , Hideo Sawamoto
IPC分类号： G06F9/38 , G06F9/00
CPC分类号： G06F9/3838 , G06F9/3824 , G06F9/3836 , G06F9/3857 , G06F9/3859
摘要： An information processor is capable of eliminating register conflict in short and long latency processes and for attaining high-speed pipeline processing through efficient use of registers. The scale of the necessary hardware is reduced by the processor using a register conflict detector and a scoreboard. The register conflict detector detects register conflict over a period of short latency processing, and the scoreboard checks for register conflict beyond the short latency process period and into a period of long latency processing. The processor controls the issue of instructions based on the detected register conflict status.
摘要翻译： PCT No.PCT / JP95 / 00356 Sec。 371日期：1997年9月3日 102（e）日期1997年9月3日PCT Filed Mar. 6，1995 PCT Pub。公开号WO96 / 27833 日期1996年9月12日信息处理器能够消除短延时和长延迟过程中的寄存器冲突，并通过有效使用寄存器实现高速流水线处理。处理器使用寄存器冲突检测器和记分板来减少所需硬件的规模。寄存器冲突检测器在短时延处理期间检测寄存器冲突，并且记分板检查超出短延迟处理周期的寄存器冲突并进入长延迟处理期间。处理器根据检测到的寄存器冲突状态控制指令的问题。

8. 发明授权

US5684729A Floating-point addition/substraction processing apparatus and method thereof 失效
标题翻译：浮点加法/减法处理装置及其方法
公开(公告)号：US5684729A
公开(公告)日：1997-11-04
申请号：US530471
申请日：1995-09-19
申请人： Hiromichi Yamada , Fumio Murabayashi , Tatsumi Yamauchi , Takashi Hotta , Hideo Sawamoto , Takahiro Nishiyama , Yoshikazu Kiyoshige , Noriyasu Ido
发明人： Hiromichi Yamada , Fumio Murabayashi , Tatsumi Yamauchi , Takashi Hotta , Hideo Sawamoto , Takahiro Nishiyama , Yoshikazu Kiyoshige , Noriyasu Ido
IPC分类号： G06F7/50 , G06F7/74
CPC分类号： G06F7/74 , G06F7/485 , G06F7/49947 , G06F7/49994
摘要： To offer a floating-point addition/subtraction processing apparatus and a method thereof, capable of shortening the computation time, the floating-point calculation processing apparatus includes an approximate shift mount predicting unit for predicting a shift amount for normalization by using the input floating-point data to be addition/subtraction processed within an error of 1 bit, a shift error detecting unit for detecting a difference between the predicted shift amount and a correct shift amount, and an bit shifter for correcting a result, obtained by normalization using the predicted shift amount, by the detected difference of the two shift amounts, wherein a round-off determination and a shift amount calculation are processed in parallel before a normalization shift processing is executed.
摘要翻译：为了提供能够缩短计算时间的浮点加法/减法处理装置及其方法，浮点计算处理装置包括：近似移位预测单元，用于通过使用输入浮点运算处理装置预测用于归一化的移位量，点数据在1比特的误差内进行加法/减法处理;移位误差检测单元，用于检测预测偏移量和正确移位量之间的差;以及位移移位器，用于校正结果，移位量乘以检测到的两个移动量的差异，其中在执行归一化移位处理之前并行处理舍入确定和移位量计算。

9. 发明授权

US5384738A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US5384738A
公开(公告)日：1995-01-24
申请号：US189636
申请日：1994-02-01
申请人： Shuuichi Miyaoka , Kazuhisa Miyamoto , Masanori Odaka , Hideo Sawamoto , Michiaki Nakayama , Mitsugu Kusunoki , Masato Ikeda , Takashi Ogata , Kouji Kobayashi , Masao Kato , Tsutomu Sumimoto
发明人： Shuuichi Miyaoka , Kazuhisa Miyamoto , Masanori Odaka , Hideo Sawamoto , Michiaki Nakayama , Mitsugu Kusunoki , Masato Ikeda , Takashi Ogata , Kouji Kobayashi , Masao Kato , Tsutomu Sumimoto
IPC分类号： H03K19/0175 , H03K19/0944 , G11C7/00
CPC分类号： H03K19/017527 , H03K19/017518 , H03K19/09448
摘要： A semiconductor integrated circuit device such as a memory device with logic function comprises a plurality of RAM macrocells and gate arrays. The RAM macrocells are constituted by bipolar CMOS RAMs having a total memory capacity of at least 100 kilobits, and the gate arrays contain at least 4000 gates. The logic circuits in the memory device with logic function or the like are constructed by selectively combining CMOS, bipolar CMOS or ECL gate circuits depending on the output load capacity, transmission characteristic requirement, power dissipation and required layout area. The level of signals at various circuits is set to the ECL level or MOS level depending on the local circuit configuration and other factors. The memory device further incorporates sequence control circuits required to be installed downstream of buffer storages of computers.
摘要翻译：诸如具有逻辑功能的存储器件的半导体集成电路器件包括多个RAM宏单元和门阵列。 RAM宏单元由具有至少100千位的总存储器容量的双极性CMOS RAM构成，并且门阵列包含至少4000个栅极。具有逻辑功能等的存储器件中的逻辑电路通过根据输出负载能力，传输特性要求，功耗和所需布局面积选择性地组合CMOS，双极CMOS或ECL门电路而构成。各种电路的信号电平根据本地电路配置和其他因素设置为ECL电平或MOS电平。存储器装置还包括需要安装在计算机的缓冲存储器下游的顺序控制电路。

10. 发明授权

US4985828A Method and apparatus for generating a real address multiple virtual address spaces of a storage 失效
标题翻译：用于生成存储器的真实地址多个虚拟地址空间的方法和装置
公开(公告)号：US4985828A
公开(公告)日：1991-01-15
申请号：US156454
申请日：1988-02-16
申请人： Naohiko Shimizu , Hideo Sawamoto
发明人： Naohiko Shimizu , Hideo Sawamoto
IPC分类号： G06F12/10
CPC分类号： G06F12/1036
摘要： A multiple virtual space control in a multiple virtual storage system having an address translation table used to translate a logical address to a real address, a control register for holding a start address of the address translation table or a space identifier (hereinafter represented by address translation table start address) and an address translation buffer containing a pair of logical address and real address and an address translation table start address for translating a logical address to a real address, in order to update the content of the control register to switch the virtual space. A group identifier comprising a plurality of bits for identifying an area common to a group of virtual spaces is added to an entry of the address translation table, an entry of the address translation buffer and the control register. When a logical address is to be translated to a real address, if there is an entry having a logical address and an address translation table start address equal to the memory request logical address and the address translation table start address of the control register, or an entry having a logical address and a group identifier equal to the memory request logical address and the group identifier of the control register, in the address translation buffer, the real address of the entry is rendered valid and used for memory access.
摘要翻译：具有用于将逻辑地址转换为实际地址的地址转换表的多虚拟存储系统中的多虚拟空间控制，用于保存地址转换表的起始地址的控制寄存器或空间标识符（以下由地址转换表起始地址）和包含一对逻辑地址和实地址的地址转换缓冲器和用于将逻辑地址转换为实地址的地址转换表起始地址，以便更新控制寄存器的内容以切换虚拟空间。包括用于识别一组虚拟空间的区域的多个位的组标识符被添加到地址转换表的条目，地址转换缓冲器和控制寄存器的条目。当将逻辑地址转换为实际地址时，如果存在具有等于存储器请求逻辑地址和控制寄存器的地址转换表开始地址的逻辑地址和地址转换表开始地址的条目，或具有等于存储器请求逻辑地址的逻辑地址和组标识符的条目和控制寄存器的组标识符在地址转换缓冲器中，条目的实际地址被呈现为有效并用于存储器访问。

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