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1. 发明授权

US5384738A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US5384738A
公开(公告)日：1995-01-24
申请号：US189636
申请日：1994-02-01
申请人： Shuuichi Miyaoka , Kazuhisa Miyamoto , Masanori Odaka , Hideo Sawamoto , Michiaki Nakayama , Mitsugu Kusunoki , Masato Ikeda , Takashi Ogata , Kouji Kobayashi , Masao Kato , Tsutomu Sumimoto
发明人： Shuuichi Miyaoka , Kazuhisa Miyamoto , Masanori Odaka , Hideo Sawamoto , Michiaki Nakayama , Mitsugu Kusunoki , Masato Ikeda , Takashi Ogata , Kouji Kobayashi , Masao Kato , Tsutomu Sumimoto
IPC分类号： H03K19/0175 , H03K19/0944 , G11C7/00
CPC分类号： H03K19/017527 , H03K19/017518 , H03K19/09448
摘要： A semiconductor integrated circuit device such as a memory device with logic function comprises a plurality of RAM macrocells and gate arrays. The RAM macrocells are constituted by bipolar CMOS RAMs having a total memory capacity of at least 100 kilobits, and the gate arrays contain at least 4000 gates. The logic circuits in the memory device with logic function or the like are constructed by selectively combining CMOS, bipolar CMOS or ECL gate circuits depending on the output load capacity, transmission characteristic requirement, power dissipation and required layout area. The level of signals at various circuits is set to the ECL level or MOS level depending on the local circuit configuration and other factors. The memory device further incorporates sequence control circuits required to be installed downstream of buffer storages of computers.
摘要翻译：诸如具有逻辑功能的存储器件的半导体集成电路器件包括多个RAM宏单元和门阵列。 RAM宏单元由具有至少100千位的总存储器容量的双极性CMOS RAM构成，并且门阵列包含至少4000个栅极。具有逻辑功能等的存储器件中的逻辑电路通过根据输出负载能力，传输特性要求，功耗和所需布局面积选择性地组合CMOS，双极CMOS或ECL门电路而构成。各种电路的信号电平根据本地电路配置和其他因素设置为ECL电平或MOS电平。存储器装置还包括需要安装在计算机的缓冲存储器下游的顺序控制电路。

2. 发明授权

US5291445A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US5291445A
公开(公告)日：1994-03-01
申请号：US589515
申请日：1990-09-28
申请人： Shuuichi Miyaoka , Kazuhisa Miyamoto , Masanori Odaka , Hideo Sawamoto , Michiaki Nakayama , Mitsugu Kusunoki , Masato Ikeda , Takashi Ogata , Kouji Kobayashi , Masao Kato , Tsutomu Sumimoto
发明人： Shuuichi Miyaoka , Kazuhisa Miyamoto , Masanori Odaka , Hideo Sawamoto , Michiaki Nakayama , Mitsugu Kusunoki , Masato Ikeda , Takashi Ogata , Kouji Kobayashi , Masao Kato , Tsutomu Sumimoto
IPC分类号： H03K19/0175 , H03K19/0944 , G11C7/00
CPC分类号： H03K19/017527 , H03K19/017518 , H03K19/09448
摘要： A semiconductor integrated circuit device such as a memory device with logic function comprises a plurality of RAM macrocells and gate arrays. The RAM macrocells are constituted by bipolar CMOS RAMs having a total memory capacity of at least 100 kilobits, and the gate arrays contain at least 4000 gates. The logic circuits in the memory device with logic function or the like are constructed by selectively combining CMOS, bipolar CMOS or ECL gate circuits depending on the output load capacity, transmission characteristic requirement, power dissipation and required layout area. The level of signals at various circuits is set to the ECL level or MOS level depending on the local circuit configuration and other factors. The memory device further incorporates sequence control circuits required to be installed downstream of buffer storages of computers.
摘要翻译：诸如具有逻辑功能的存储器件的半导体集成电路器件包括多个RAM宏单元和门阵列。 RAM宏单元由具有至少100千位的总存储器容量的双极性CMOS RAM构成，并且门阵列包含至少4000个栅极。具有逻辑功能等的存储器件中的逻辑电路通过根据输出负载能力，传输特性要求，功耗和所需布局面积选择性地组合CMOS，双极CMOS或ECL门电路而构成。各种电路的信号电平根据本地电路配置和其他因素设置为ECL电平或MOS电平。存储器装置还包括需要安装在计算机的缓冲存储器下游的顺序控制电路。

3. 发明授权

US06714477B2 Semiconductor integrated circuit device with memory blocks and a write buffer capable of storing write data from an external interface 失效
标题翻译：具有存储块的半导体集成电路器件和能够存储来自外部接口的写入数据的写入缓冲器
公开(公告)号：US06714477B2
公开(公告)日：2004-03-30
申请号：US10187947
申请日：2002-07-03
申请人： Michiaki Nakayama , Hideki Sakakibara , Toru Kobayashi , Shuichi Miyaoka , Yuji Yokoyama , Hideo Sawamoto , Masaji Kume
发明人： Michiaki Nakayama , Hideki Sakakibara , Toru Kobayashi , Shuichi Miyaoka , Yuji Yokoyama , Hideo Sawamoto , Masaji Kume
IPC分类号： G11C800
CPC分类号： G11C7/106 , G11C7/1006 , G11C7/1051 , G11C11/4093
摘要： Read buffers (RB0-RB3) are capable of holding data read out from a plurality of memory blocks (BNK0-BNK7) that are capable of parallel operation in response to a state in which the read data cannot be externally outputted from an external interface means; and, selection means (40, 41, 42) are provided for selecting data read out from one of the memory blocks, or data read out from one of the read buffers, and for feeding it to the external interface means, while the external-output-incapable state is not present. In this way, when there is a possibility that an output of read data will cause a resource competition, this read data is stored in a read buffer, and when there is no such possibility, then the read data can be externally outputted directly, thereby improving the throughput of read data output operations.
摘要翻译：读取缓冲器（RB0-RB3）能够保持从能够并行操作的多个存储器块（BNK0-BNK7）中读出的数据，以响应于从外部接口装置不能从外部输出读取的数据的状态 ; 并且提供选择装置（40,41,42），用于选择从一个存储块读出的数据，或从读取缓冲器之一读出的数据，并将其馈送到外部接口装置，输出无能力状态不存在。这样，当读取数据的输出有可能导致资源竞争时，该读取数据被存储在读取缓冲器中，并且当不存在这种可能性时，可以直接从外部输出读取的数据，由此提高读取数据输出操作的吞吐量。

4. 发明授权

US06430103B2 Semiconductor integrated circuit device with memory banks and read buffer capable of storing data read out from one memory bank when data of another memory bank is outputting 失效
标题翻译：具有存储体的半导体集成电路装置和能够在另一存储体的数据输出时存储从一个存储体读出的数据的读取缓冲器
公开(公告)号：US06430103B2
公开(公告)日：2002-08-06
申请号：US09775544
申请日：2001-02-05
申请人： Michiaki Nakayama , Hideki Sakakibara , Toru Kobayashi , Shuichi Miyaoka , Yuji Yokoyama , Hideo Sawamoto , Masaji Kume
发明人： Michiaki Nakayama , Hideki Sakakibara , Toru Kobayashi , Shuichi Miyaoka , Yuji Yokoyama , Hideo Sawamoto , Masaji Kume
IPC分类号： G11C800
CPC分类号： G11C7/106 , G11C7/1006 , G11C7/1051 , G11C11/4093
摘要： Read buffers (RB0-RB3) are capable of holding data read out from a plurality of memory blocks (BNK0-BNK7) that are capable of parallel operation in response to a state in which the read data cannot be externally outputted from an external interface means; and, selection means (40, 41, 42) are provided for selecting data read out from one of the memory blocks, or data read out from one of the read buffers, and for feeding it to the external interface means, while the external-output-incapable state is not present. In this way, when there is a possibility that an output of read data will cause a resource competition, this read data is stored in a read buffer, and when there is no such possibility, then the read data can be externally outputted directly, thereby improving the throughput of read data output operations.
摘要翻译：读取缓冲器（RB0-RB3）能够保持从能够并行操作的多个存储器块（BNK0-BNK7）中读出的数据，以响应于从外部接口装置不能从外部输出读取的数据的状态 ; 并且提供选择装置（40,41,42），用于选择从一个存储块读出的数据，或从读取缓冲器之一读出的数据，并将其馈送到外部接口装置，输出无能力状态不存在。这样，当读取数据的输出有可能导致资源竞争时，该读取数据被存储在读取缓冲器中，并且当不存在这种可能性时，可以直接从外部输出读取的数据，由此提高读取数据输出操作的吞吐量。

5. 发明授权

US06275902B1 Data processor with variable types of cache memories and a controller for selecting a cache memory to be access 失效
标题翻译：具有可变类型的高速缓存存储器的数据处理器和用于选择要访问的高速缓冲存储器的控制器
公开(公告)号：US06275902B1
公开(公告)日：2001-08-14
申请号：US09188693
申请日：1998-11-10
申请人： Takashi Hotta , Toshihiko Kurihara , Shigeya Tanaka , Hideo Sawamoto , Akiyoshi Osumi , Koji Saito , Kotaro Shimamura
发明人： Takashi Hotta , Toshihiko Kurihara , Shigeya Tanaka , Hideo Sawamoto , Akiyoshi Osumi , Koji Saito , Kotaro Shimamura
IPC分类号： G06F1208
CPC分类号： G06F12/0897 , G06F12/0846 , G06F12/0862 , G06F12/0864 , G06F2212/6028
摘要： A data processor has a first cache memory with a large capacity and one port and a second cache memory with a small capacity and two ports disposed between a main memory and an instruction processing section. Data which is frequently used is stored in the first cache memory and data which is less frequently used is stored in the second cache memory under control of a controller responsive to prefetch instructions. One of the cache memories may be a set associative cache memory composed of a plurality of memory chips each having at least two memory banks and an output part to gain access to data sets consecutively and one at a time within the memory banks. On the basis of an address sent from the instruction processing section, a memory bank is selected, and a data set from the selected memory bank is supplied to the processing section.
摘要翻译：数据处理器具有大容量的第一高速缓冲存储器和一个端口，具有小容量的第二缓存存储器和设置在主存储器和指令处理部件之间的两个端口。经常使用的数据被存储在第一高速缓冲存储器中，并且在响应于预取指令的控制器的控制下，较不频繁使用的数据被存储在第二高速缓冲存储器中。高速缓存存储器中的一个可以是由多个存储器芯片构成的组合的相关高速缓冲存储器，每个存储器芯片具有至少两个存储器组，以及输出部分，以连续地访问数据集，并且一个在存储器组内一次。基于从指令处理部分发送的地址，选择存储体，并且将从所选择的存储体组中提取的数据提供给处理部分。

6. 发明授权

US6101596A Information processor for performing processing without register conflicts 失效
标题翻译：用于执行无注册冲突的处理的信息处理器
公开(公告)号：US6101596A
公开(公告)日：2000-08-08
申请号：US894924
申请日：1997-09-03
申请人： Shigeya Tanaka , Kotaro Shimamura , Tetsuya Shimomura , Takashi Hotta , Hideo Sawamoto
发明人： Shigeya Tanaka , Kotaro Shimamura , Tetsuya Shimomura , Takashi Hotta , Hideo Sawamoto
IPC分类号： G06F9/38 , G06F9/00
CPC分类号： G06F9/3838 , G06F9/3824 , G06F9/3836 , G06F9/3857 , G06F9/3859
摘要： An information processor is capable of eliminating register conflict in short and long latency processes and for attaining high-speed pipeline processing through efficient use of registers. The scale of the necessary hardware is reduced by the processor using a register conflict detector and a scoreboard. The register conflict detector detects register conflict over a period of short latency processing, and the scoreboard checks for register conflict beyond the short latency process period and into a period of long latency processing. The processor controls the issue of instructions based on the detected register conflict status.
摘要翻译： PCT No.PCT / JP95 / 00356 Sec。 371日期：1997年9月3日 102（e）日期1997年9月3日PCT Filed Mar. 6，1995 PCT Pub。公开号WO96 / 27833 日期1996年9月12日信息处理器能够消除短延时和长延迟过程中的寄存器冲突，并通过有效使用寄存器实现高速流水线处理。处理器使用寄存器冲突检测器和记分板来减少所需硬件的规模。寄存器冲突检测器在短时延处理期间检测寄存器冲突，并且记分板检查超出短延迟处理周期的寄存器冲突并进入长延迟处理期间。处理器根据检测到的寄存器冲突状态控制指令的问题。

7. 发明授权

US5684729A Floating-point addition/substraction processing apparatus and method thereof 失效
标题翻译：浮点加法/减法处理装置及其方法
公开(公告)号：US5684729A
公开(公告)日：1997-11-04
申请号：US530471
申请日：1995-09-19
申请人： Hiromichi Yamada , Fumio Murabayashi , Tatsumi Yamauchi , Takashi Hotta , Hideo Sawamoto , Takahiro Nishiyama , Yoshikazu Kiyoshige , Noriyasu Ido
发明人： Hiromichi Yamada , Fumio Murabayashi , Tatsumi Yamauchi , Takashi Hotta , Hideo Sawamoto , Takahiro Nishiyama , Yoshikazu Kiyoshige , Noriyasu Ido
IPC分类号： G06F7/50 , G06F7/74
CPC分类号： G06F7/74 , G06F7/485 , G06F7/49947 , G06F7/49994
摘要： To offer a floating-point addition/subtraction processing apparatus and a method thereof, capable of shortening the computation time, the floating-point calculation processing apparatus includes an approximate shift mount predicting unit for predicting a shift amount for normalization by using the input floating-point data to be addition/subtraction processed within an error of 1 bit, a shift error detecting unit for detecting a difference between the predicted shift amount and a correct shift amount, and an bit shifter for correcting a result, obtained by normalization using the predicted shift amount, by the detected difference of the two shift amounts, wherein a round-off determination and a shift amount calculation are processed in parallel before a normalization shift processing is executed.
摘要翻译：为了提供能够缩短计算时间的浮点加法/减法处理装置及其方法，浮点计算处理装置包括：近似移位预测单元，用于通过使用输入浮点运算处理装置预测用于归一化的移位量，点数据在1比特的误差内进行加法/减法处理;移位误差检测单元，用于检测预测偏移量和正确移位量之间的差;以及位移移位器，用于校正结果，移位量乘以检测到的两个移动量的差异，其中在执行归一化移位处理之前并行处理舍入确定和移位量计算。

8. 发明授权

US5305458A Multiple virtual storage system and address control apparatus having a designation table holding device and translation buffer 失效
标题翻译：多个虚拟存储系统和地址控制装置具有指定表保持装置和转换缓冲器
公开(公告)号：US5305458A
公开(公告)日：1994-04-19
申请号：US518411
申请日：1990-05-02
申请人： Yukihiro Motomura , Hideki Takeuchi , Hideo Sawamoto , Mari Ara
发明人： Yukihiro Motomura , Hideki Takeuchi , Hideo Sawamoto , Mari Ara
IPC分类号： G06F12/10 , G06F12/02 , G06F12/00
CPC分类号： G06F12/0292
摘要： In a multiple virtual storage system and more particularly in an address control apparatus, there are provided two kinds of holding devices a designation holding device for holding a segment table designations in association with access registers and a translation buffer for holding translation pairs of the access register and segment table designation. With this arrangement, the segment table designation designating the virtual address space possessing an operand of an instruction can be supplied quickly and efficiently.
摘要翻译：在多虚拟存储系统中，特别是在地址控制装置中，提供了两种保持装置：用于保存与访问寄存器相关联的分段表名称的指定保存装置和用于保存访问寄存器的转换对的转换缓冲器和分段表指定。通过这种布置，可以快速有效地提供指定具有指令的操作数的虚拟地址空间的段表指定。

9. 发明授权

US4985828A Method and apparatus for generating a real address multiple virtual address spaces of a storage 失效
标题翻译：用于生成存储器的真实地址多个虚拟地址空间的方法和装置
公开(公告)号：US4985828A
公开(公告)日：1991-01-15
申请号：US156454
申请日：1988-02-16
申请人： Naohiko Shimizu , Hideo Sawamoto
发明人： Naohiko Shimizu , Hideo Sawamoto
IPC分类号： G06F12/10
CPC分类号： G06F12/1036
摘要： A multiple virtual space control in a multiple virtual storage system having an address translation table used to translate a logical address to a real address, a control register for holding a start address of the address translation table or a space identifier (hereinafter represented by address translation table start address) and an address translation buffer containing a pair of logical address and real address and an address translation table start address for translating a logical address to a real address, in order to update the content of the control register to switch the virtual space. A group identifier comprising a plurality of bits for identifying an area common to a group of virtual spaces is added to an entry of the address translation table, an entry of the address translation buffer and the control register. When a logical address is to be translated to a real address, if there is an entry having a logical address and an address translation table start address equal to the memory request logical address and the address translation table start address of the control register, or an entry having a logical address and a group identifier equal to the memory request logical address and the group identifier of the control register, in the address translation buffer, the real address of the entry is rendered valid and used for memory access.
摘要翻译：具有用于将逻辑地址转换为实际地址的地址转换表的多虚拟存储系统中的多虚拟空间控制，用于保存地址转换表的起始地址的控制寄存器或空间标识符（以下由地址转换表起始地址）和包含一对逻辑地址和实地址的地址转换缓冲器和用于将逻辑地址转换为实地址的地址转换表起始地址，以便更新控制寄存器的内容以切换虚拟空间。包括用于识别一组虚拟空间的区域的多个位的组标识符被添加到地址转换表的条目，地址转换缓冲器和控制寄存器的条目。当将逻辑地址转换为实际地址时，如果存在具有等于存储器请求逻辑地址和控制寄存器的地址转换表开始地址的逻辑地址和地址转换表开始地址的条目，或具有等于存储器请求逻辑地址的逻辑地址和组标识符的条目和控制寄存器的组标识符在地址转换缓冲器中，条目的实际地址被呈现为有效并用于存储器访问。

10. 发明授权

US4885681A I/O Execution method for a virtual machine system and system therefor 失效
标题翻译： I / O虚拟机系统及其系统的执行方法
公开(公告)号：US4885681A
公开(公告)日：1989-12-05
申请号：US691909
申请日：1985-01-16
申请人： Hidenori Umeno , Takashige Kubo , Nobutaka Hagiwara , Hiroaki Sato , Hideo Sawamoto
发明人： Hidenori Umeno , Takashige Kubo , Nobutaka Hagiwara , Hiroaki Sato , Hideo Sawamoto
IPC分类号： G06F9/455 , G06F9/46 , G06F12/08 , G06F12/10 , G06F13/10
CPC分类号： G06F13/10 , G06F9/45558 , G06F2009/45579
摘要： In a virtual machine system (VMS) capable of concurrently running at least one operating system (OS) under one real computer system and a control program (VMCP) for controlling the VMS, the object is to reduce the overhead produced for simulating VM I/Os by direct I/O execution. A VM information area of a real sub-channel control block has a status field in which a flag indicating that the sub-channel is dedicated or not is contained. When the flag is "0", it means that the sub-channel is dedicated to the VM and the sub-channel scheduling by the VMCP is not necessary. As a real interruption priority order is dedicated to a VM, only I/O interruption requests of the VM are queued into the real interruption request queue of that dedicated priority order, and the mixing of VMs in that real interruption priority order is avoided. When an interruption control mask of an interruption priority order of the OS on the VM is "0" indicating that the interruption is not acceptable by the VM, the interruption control mask of the corresponding dedicated real interruption priority order is also "0" and the hardware interruption does not take place. Accordingly, the interruption is retained by the hardware and the I/O interruption retention for the VM by the VMCP is avoided.
摘要翻译：在能够在一个实际计算机系统下同时运行至少一个操作系统（OS）的虚拟机系统（VMS）和用于控制VMS的控制程序（VMCP）的情况下，目的是减少模拟VM I / Os通过直接I / O执行。实际子信道控制块的VM信息区域具有包含表示子信道为专用的标志的状态字段。当标志为“0”时，这意味着该子信道专用于该VM，并且该VMCP的子信道调度是不必要的。由于真正的中断优先级顺序专用于VM，因此只有VM的I / O中断请求被排队到该专用优先级顺序的实际中断请求队列中，并且避免了该实际中断优先级顺序的VM的混合。当VM上的OS的中断优先级顺序的中断控制掩码为“0”，表示VM不能接受中断时，相应的专用实际中断优先级顺序的中断控制掩码也为“0”，并且硬件中断不会发生。因此，中断由硬件保留，并且避免VMCP对VM的I / O中断保持。

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