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1. 发明授权

US5235688A Memory access control unit for allowing maximum throughput of an I/O processor and an I/O request buffer full state 失效
标题翻译：用于允许I / O处理器和I / O请求缓冲器的最大吞吐量的存储器访问控制单元
公开(公告)号：US5235688A
公开(公告)日：1993-08-10
申请号：US532446
申请日：1990-06-04
申请人： Toshihisa Taniguchi , Tsutomu Sumimoto
发明人： Toshihisa Taniguchi , Tsutomu Sumimoto
IPC分类号： G06F9/50 , G06F9/52 , G06F12/00 , G06F12/08 , G06F15/16 , G06F15/177
CPC分类号： G06F9/5016 , G06F12/084
摘要： When an IOP is transferring data at the maximal throughput because of the fact that the input-output processor (IOP) has issued a next request under a state when the request buffers are full of requests from the IOP at least a part of the requests from the instruction processor (IP) is inhibited. Inhibition of the requests from the IP is released when the pitch of the requests from the IOP reaches a predetermined period or more. When the IOP is transferring data at the maximal throughput in a system having a cache memory, access to the main memory by the IP is inhibited in case requested data does not exist in the cache memory.
摘要翻译：当IOP以最大吞吐量传输数据时，由于输入输出处理器（IOP）在请求缓冲器满足来自IOP的请求的状态下发出下一个请求的事实，至少一部分请求来自指令处理器（IP）被禁止。当来自IOP的请求的音调达到预定时间段或更长时间时，释放来自IP的请求的抑制。当IOP在具有高速缓存存储器的系统中以最大吞吐量传送数据时，在高速缓冲存储器中不存在所请求的数据的情况下，禁止由IP访问主存储器。

2. 发明授权

US5384738A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US5384738A
公开(公告)日：1995-01-24
申请号：US189636
申请日：1994-02-01
申请人： Shuuichi Miyaoka , Kazuhisa Miyamoto , Masanori Odaka , Hideo Sawamoto , Michiaki Nakayama , Mitsugu Kusunoki , Masato Ikeda , Takashi Ogata , Kouji Kobayashi , Masao Kato , Tsutomu Sumimoto
发明人： Shuuichi Miyaoka , Kazuhisa Miyamoto , Masanori Odaka , Hideo Sawamoto , Michiaki Nakayama , Mitsugu Kusunoki , Masato Ikeda , Takashi Ogata , Kouji Kobayashi , Masao Kato , Tsutomu Sumimoto
IPC分类号： H03K19/0175 , H03K19/0944 , G11C7/00
CPC分类号： H03K19/017527 , H03K19/017518 , H03K19/09448
摘要： A semiconductor integrated circuit device such as a memory device with logic function comprises a plurality of RAM macrocells and gate arrays. The RAM macrocells are constituted by bipolar CMOS RAMs having a total memory capacity of at least 100 kilobits, and the gate arrays contain at least 4000 gates. The logic circuits in the memory device with logic function or the like are constructed by selectively combining CMOS, bipolar CMOS or ECL gate circuits depending on the output load capacity, transmission characteristic requirement, power dissipation and required layout area. The level of signals at various circuits is set to the ECL level or MOS level depending on the local circuit configuration and other factors. The memory device further incorporates sequence control circuits required to be installed downstream of buffer storages of computers.
摘要翻译：诸如具有逻辑功能的存储器件的半导体集成电路器件包括多个RAM宏单元和门阵列。 RAM宏单元由具有至少100千位的总存储器容量的双极性CMOS RAM构成，并且门阵列包含至少4000个栅极。具有逻辑功能等的存储器件中的逻辑电路通过根据输出负载能力，传输特性要求，功耗和所需布局面积选择性地组合CMOS，双极CMOS或ECL门电路而构成。各种电路的信号电平根据本地电路配置和其他因素设置为ECL电平或MOS电平。存储器装置还包括需要安装在计算机的缓冲存储器下游的顺序控制电路。

3. 发明申请

US20050031267A1 Branch optical wave-guide 审中-公开
标题翻译：分支光波导
公开(公告)号：US20050031267A1
公开(公告)日：2005-02-10
申请号：US10898165
申请日：2004-07-26
申请人： Tsutomu Sumimoto
发明人： Tsutomu Sumimoto
IPC分类号： G02B6/122 , G02B6/12 , G02B6/125 , G02B6/28 , G02B6/26
CPC分类号： G02B6/2804 , G02B6/125
摘要： When the longitudinal central axis line of a first linear wave-guide 2 that receives light is set to be a reference line, open portions of circular arcs of first curved wave-guides 4a, 4b that are coupled to a tapered wave-guide 3 face outward when viewed from the reference line. On the other hand, open portions of circular arcs of second curved wave-guides 5a, 5b that are coupled to the first curved wave-guides 4a, 4b face inward when viewed from the reference line. Furthermore, second linear wave-guides 6a, 6b, which are coupled to the first linear wave-guide through the first and second curved wave-guides, and the reference line X are outwardly coupled to form an angle, which is set to be greater than 0 degree. According to the present invention, there can be provided a branch optical wave-guide that can make its entire length short with polarization property of respective output ports equalized.
摘要翻译：当接收光的第一线性波导2的纵向中心轴线被设定为基准线时，第一弯曲波导4a，4b的圆弧的开口部分与锥形波导3面从参考线观察时向外。另一方面，当从基准线观察时，耦合到第一弯曲波导4a，4b的第二弯曲波导5a，5b的圆弧的开口部分向内。此外，通过第一和第二弯曲波导耦合到第一线性波导管的第二线性波导6a和6b以及参考线X被外连接以形成一个角度，其被设定为更大 0度以上。根据本发明，可以提供一种分支光波导，其可以使其整个长度短，各个输出端口的偏振特性相等。

4. 发明授权

US5291445A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US5291445A
公开(公告)日：1994-03-01
申请号：US589515
申请日：1990-09-28
申请人： Shuuichi Miyaoka , Kazuhisa Miyamoto , Masanori Odaka , Hideo Sawamoto , Michiaki Nakayama , Mitsugu Kusunoki , Masato Ikeda , Takashi Ogata , Kouji Kobayashi , Masao Kato , Tsutomu Sumimoto
发明人： Shuuichi Miyaoka , Kazuhisa Miyamoto , Masanori Odaka , Hideo Sawamoto , Michiaki Nakayama , Mitsugu Kusunoki , Masato Ikeda , Takashi Ogata , Kouji Kobayashi , Masao Kato , Tsutomu Sumimoto
IPC分类号： H03K19/0175 , H03K19/0944 , G11C7/00
CPC分类号： H03K19/017527 , H03K19/017518 , H03K19/09448
摘要： A semiconductor integrated circuit device such as a memory device with logic function comprises a plurality of RAM macrocells and gate arrays. The RAM macrocells are constituted by bipolar CMOS RAMs having a total memory capacity of at least 100 kilobits, and the gate arrays contain at least 4000 gates. The logic circuits in the memory device with logic function or the like are constructed by selectively combining CMOS, bipolar CMOS or ECL gate circuits depending on the output load capacity, transmission characteristic requirement, power dissipation and required layout area. The level of signals at various circuits is set to the ECL level or MOS level depending on the local circuit configuration and other factors. The memory device further incorporates sequence control circuits required to be installed downstream of buffer storages of computers.
摘要翻译：诸如具有逻辑功能的存储器件的半导体集成电路器件包括多个RAM宏单元和门阵列。 RAM宏单元由具有至少100千位的总存储器容量的双极性CMOS RAM构成，并且门阵列包含至少4000个栅极。具有逻辑功能等的存储器件中的逻辑电路通过根据输出负载能力，传输特性要求，功耗和所需布局面积选择性地组合CMOS，双极CMOS或ECL门电路而构成。各种电路的信号电平根据本地电路配置和其他因素设置为ECL电平或MOS电平。存储器装置还包括需要安装在计算机的缓冲存储器下游的顺序控制电路。

5. 发明授权

US4774687A Advanced store-in system for a hierarchy memory device 失效
标题翻译：用于分层存储器设备的高级存储系统
公开(公告)号：US4774687A
公开(公告)日：1988-09-27
申请号：US748945
申请日：1985-06-26
申请人： Toshihisa Taniguchi , Tsutomu Sumimoto , Takashi Kumagai
发明人： Toshihisa Taniguchi , Tsutomu Sumimoto , Takashi Kumagai
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/0859
摘要： A memory access control system for an information processing apparatus having a buffer memory and a main memory wherein when a store or access request is generated, in the case where the data block in the address to be accessed does not exist in the buffer memory, the store requested data from a data register is written into the buffer memory before the first data in the data block read out from the main memory is written into the buffer memory, and the data register is released to receive the next request.
摘要翻译：一种用于具有缓冲存储器和主存储器的信息处理装置的存储器访问控制系统，其中当存储或访问请求被生成时，在要访问的地址中的数据块不存在于缓冲存储器中的情况下，在将从主存储器读出的数据块中的第一数据写入缓冲存储器之前，将来自数据寄存器的请求数据存储器写入缓冲存储器，并且释放数据寄存器以接收下一个请求。

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