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1. 发明授权

US5392409A I/O execution method for a virtual machine system and system therefor 失效
标题翻译：用于虚拟机系统及其系统的I / O执行方法
公开(公告)号：US5392409A
公开(公告)日：1995-02-21
申请号：US851629
申请日：1992-03-16
申请人： Hidenori Umeno , Takashige Kubo , Nobutaka Hagiwara , Hiroaki Sato , Hideo Sawamoto , Taro Inoue , Shunji Tanaka
发明人： Hidenori Umeno , Takashige Kubo , Nobutaka Hagiwara , Hiroaki Sato , Hideo Sawamoto , Taro Inoue , Shunji Tanaka
IPC分类号： G06F9/455 , G06F13/10 , G06F12/00
CPC分类号： G06F13/10 , G06F9/45558 , G06F2009/45579 , G06F2009/45583
摘要： In a computer system having a central processing unit, a main storage and at least one I/O device, a plurality of operating systems (OS) can simultaneously run under the control of a control program. For executing an I/O instruction using a central processing unit, a plurality of resident areas of said main storage which do not overlap one another are assigned, under the control of the control program, to the plurality of OSs as main memories therefore, respectively. In responding to an I/O instruction issued by a running one of said plural OSs, an address of said main memory assigned to said running OS which participates in an I/Oo operation requested by said I/O instruction is determined without intervention of the control program, and the address is translated into an address of the main storage of the computer system without intervention of said control program. The I/O operation is then executed by using the address resulting from said address translation.
摘要翻译：在具有中央处理单元，主存储器和至少一个I / O设备的计算机系统中，多个操作系统（OS）可以在控制程序的控制下同时运行。为了使用中央处理单元执行I / O指令，在控制程序的控制下，分别将不相互重叠的所述主存储器的多个驻留区域分别作为主存储器分配给作为主存储器的多个OS 。在响应由所述多个OS中运行的一个OS发出的I / O指令时，确定分配给所述运行OS的所述主存储器的参与I / O指令请求的I / Oo操作的地址，控制程序，并且该地址被转换成计算机系统的主存储器的地址，而不需要所述控制程序的干预。然后通过使用由所述地址转换产生的地址来执行I / O操作。

2. 发明授权

US4885681A I/O Execution method for a virtual machine system and system therefor 失效
标题翻译： I / O虚拟机系统及其系统的执行方法
公开(公告)号：US4885681A
公开(公告)日：1989-12-05
申请号：US691909
申请日：1985-01-16
申请人： Hidenori Umeno , Takashige Kubo , Nobutaka Hagiwara , Hiroaki Sato , Hideo Sawamoto
发明人： Hidenori Umeno , Takashige Kubo , Nobutaka Hagiwara , Hiroaki Sato , Hideo Sawamoto
IPC分类号： G06F9/455 , G06F9/46 , G06F12/08 , G06F12/10 , G06F13/10
CPC分类号： G06F13/10 , G06F9/45558 , G06F2009/45579
摘要： In a virtual machine system (VMS) capable of concurrently running at least one operating system (OS) under one real computer system and a control program (VMCP) for controlling the VMS, the object is to reduce the overhead produced for simulating VM I/Os by direct I/O execution. A VM information area of a real sub-channel control block has a status field in which a flag indicating that the sub-channel is dedicated or not is contained. When the flag is "0", it means that the sub-channel is dedicated to the VM and the sub-channel scheduling by the VMCP is not necessary. As a real interruption priority order is dedicated to a VM, only I/O interruption requests of the VM are queued into the real interruption request queue of that dedicated priority order, and the mixing of VMs in that real interruption priority order is avoided. When an interruption control mask of an interruption priority order of the OS on the VM is "0" indicating that the interruption is not acceptable by the VM, the interruption control mask of the corresponding dedicated real interruption priority order is also "0" and the hardware interruption does not take place. Accordingly, the interruption is retained by the hardware and the I/O interruption retention for the VM by the VMCP is avoided.
摘要翻译：在能够在一个实际计算机系统下同时运行至少一个操作系统（OS）的虚拟机系统（VMS）和用于控制VMS的控制程序（VMCP）的情况下，目的是减少模拟VM I / Os通过直接I / O执行。实际子信道控制块的VM信息区域具有包含表示子信道为专用的标志的状态字段。当标志为“0”时，这意味着该子信道专用于该VM，并且该VMCP的子信道调度是不必要的。由于真正的中断优先级顺序专用于VM，因此只有VM的I / O中断请求被排队到该专用优先级顺序的实际中断请求队列中，并且避免了该实际中断优先级顺序的VM的混合。当VM上的OS的中断优先级顺序的中断控制掩码为“0”，表示VM不能接受中断时，相应的专用实际中断优先级顺序的中断控制掩码也为“0”，并且硬件中断不会发生。因此，中断由硬件保留，并且避免VMCP对VM的I / O中断保持。

3. 发明授权

US5109489A I/O execution method for a virtual machine system and system therefor 失效
标题翻译：虚拟机系统及其系统的I / O执行方法
公开(公告)号：US5109489A
公开(公告)日：1992-04-28
申请号：US369535
申请日：1989-06-21
申请人： Hidenori Umeno , Takashige Kubo , Nobutaka Hagiwara , Hiroaki Sato , Hideo Sawamoto
发明人： Hidenori Umeno , Takashige Kubo , Nobutaka Hagiwara , Hiroaki Sato , Hideo Sawamoto
IPC分类号： G06F9/455 , G06F9/46 , G06F12/08 , G06F12/10 , G06F13/10
CPC分类号： G06F13/10 , G06F9/45558 , G06F2009/45579
摘要： In a virtual machine system (VMS) capable of concurrently running at least one operating system (OS) under one real computer system and a control program (VMCP) for controlling the VMS, the object is to reduce the overhead produced for simulating VM I/Os by direct I/O execution. A VM information area of a real sub-channel control block has a status field in which a flag indicating that the sub-channel is dedicated or not is contained. When the flag is "1", it means that the sub-channel is dedicated to the VM and the sub-channel scheduling by the VMCP is not necessary. As a real interruption priority order is dedicated to a VM, only I/O interruption requests of the VM are queued into the real interruption request queue of that dedicated priority order, and the mixing of VMs in that real interruption priority order is avoided. When an interruption control mask of an interruption priority order of the OS on the VM is "0" indicating that the interruption is not acceptable by the VM, the interruption conrol mask of the corresponding dedicated real interruption priority order is also "0" and the hardware interruption does not take place. Accordingly, the interruption is retained by the hardware and the I/O interruption retention for the VM by the VMCP is avoided.

4. 发明授权

US5499379A Input/output execution apparatus for a plural-OS run system 失效
标题翻译：多OS运行系统的输入输出执行装置
公开(公告)号：US5499379A
公开(公告)日：1996-03-12
申请号：US8842
申请日：1993-01-25
申请人： Shunji Tanaka , Toru Ohtsuki , Hiroaki Sato , Hideo Sawamoto , Ryo Yamagata , Masaya Watanabe , Hidenori Umeno , Masatoshi Haraguchi
发明人： Shunji Tanaka , Toru Ohtsuki , Hiroaki Sato , Hideo Sawamoto , Ryo Yamagata , Masaya Watanabe , Hidenori Umeno , Masatoshi Haraguchi
IPC分类号： G06F13/10 , G06F9/318 , G06F9/455 , G06F9/46 , G06F9/48 , G06F9/00
CPC分类号： G06F9/3017 , G06F9/45558 , G06F9/4812 , G06F2009/45579
摘要： A plural-OS run system in which a plurality of operating systems (OSs) capable of operating on machines of different architectures, respectively, are allowed to run on one bare machine under the control of one control program (CP) or one control means. The input/output instruction and input/output interrupt of the operating system capable of running on a machine of the same architecture as that of the bare machine are directly executed on the bare machine without need for translation of the format. The input/output instruction and the input/output interrupt of the operating system adapted to run on a machine of the architecture differing from that of the bare machine are allowed to be directly executed while translating the format.
摘要翻译：一种多操作系统运行系统，其中可以在一个控制程序（CP）或一个控制装置的控制下，分别在不同架构的机器上操作的多个操作系统（OS）在一个裸机上运行。能够在与裸机相同架构的机器上运行的操作系统的输入/输出指令和输入/输出中断在裸机上直接执行，无需转换格式。允许在转换格式的同时直接执行适用于与裸机机架不同的架构的机器上运行的操作系统的输入/输出指令和输入/输出中断。

5. 发明授权

US09758134B2 Disk brake 有权
公开(公告)号：US09758134B2
公开(公告)日：2017-09-12
申请号：US14390504
申请日：2012-04-11
申请人： Tomohiro Yokoyama , Ikuru Konno , Hiroaki Sato , Kiyoshi Kuwazuru , Takahiro Ishida
发明人： Tomohiro Yokoyama , Ikuru Konno , Hiroaki Sato , Kiyoshi Kuwazuru , Takahiro Ishida
IPC分类号： F16D55/22 , B60T1/06 , F16D55/226 , F16D55/2265 , F16D55/227 , F16D65/092 , F16D121/20 , F16D121/22 , F16D129/06 , F16D55/00 , F16D129/08
CPC分类号： B60T1/065 , F16D55/226 , F16D55/2265 , F16D55/22655 , F16D55/227 , F16D65/092 , F16D2055/0029 , F16D2121/20 , F16D2121/22 , F16D2129/06 , F16D2129/08
摘要： According to an example, a disk brake is disclosed in which a caliper is supported by a mounting bracket via a slide pin, the mounting bracket being attached to a non-rotational portion of a vehicle, the disk brake comprising an electromagnet provided in connection with the slide pin, the electromagnet attracting the slide pin in an axial direction of the slide pin such that brake pads move away from a disk rotor. According to another example, a disk brake in which a caliper is supported by a mounting bracket via a slide pin, the mounting bracket being attached to a non-rotational portion of a vehicle, the disk brake comprising a magnetic material body of a backing plate of a brake pad and an electromagnet provided in a location where the electromagnet is opposed to the magnetic material body in a lateral direction of the vehicle.

6. 发明授权

US09681848B2 X-ray diagnostic system 有权
公开(公告)号：US09681848B2
公开(公告)日：2017-06-20
申请号：US13991457
申请日：2012-01-19
申请人： Yasunori Goto , Hiroaki Sato
发明人： Yasunori Goto , Hiroaki Sato
IPC分类号： A61B6/00 , A61B6/04
CPC分类号： A61B6/4464 , A61B6/0407 , A61B6/4291 , A61B6/4452
摘要： An X-ray diagnostic system is provided that is capable of fitting the vertical position of the X-ray tube to each mode of photography without being affected by the height of the ceiling. The X-rays irradiated from the X-ray tube and transmitted through the subject are detected, and photographed images are captured based on the detected X-rays; the system comprises a supporting member, an arm member, and a height adjuster; the supporting member is provided on the ceiling of a room, formed in a pillar shape, and configured in such a way that the entire length is vertically extended and shortened. The arm member has a base end section connected to the lower end portion of the supporting member and a tip section on which the X-ray tube is mounted. The height adjuster adjusts the vertical position of the X-ray tube by moving the tip section of the arm member relative to the supporting member.

7. 发明授权

US08709633B2 Battery loading and unloading mechanism 有权
标题翻译：电池装卸机构
公开(公告)号：US08709633B2
公开(公告)日：2014-04-29
申请号：US11722917
申请日：2005-12-22
申请人： Takayoshi Yamasaki , Hiroaki Sato , Toshiaki Ueda , Tomonori Watanabe , Yoichi Miyajima , Osamu Nagashima , Mieko Hara
发明人： Takayoshi Yamasaki , Hiroaki Sato , Toshiaki Ueda , Tomonori Watanabe , Yoichi Miyajima , Osamu Nagashima , Mieko Hara
IPC分类号： H01M2/10 , H01M2/00
CPC分类号： H01M2/1066 , H01M2/1022 , H01M2/1061 , H01M2/342 , H01M10/4221 , H01M2220/30
摘要： In a battery loading and unloading mechanism, a battery formed in a flat rectangular parallelepiped and having an almost square main surface is loaded and unloaded to and from a device. The battery is formed with projecting portions at longitudinal both ends of a back surface thereof and along the back surface, whereby the battery can be prevented from being erroneously inserted into the device. The projecting portion has an inclined surface acutely inclined with respect to the back surface, and when the battery is unloaded from the device, unloading of the battery from the device is accelerated by the inclined surface undergoing contact pressure of the retaining means. The device is formed with a notched portion which is adapted to expose the other projecting portion of the battery when the battery is loaded, therebyfacilitating unloading of the battery.
摘要翻译：在电池装载和卸载机构中，形成为平坦的长方体并且具有几乎正方形的主表面的电池被装载和卸载到设备上。电池在其后表面的纵向两端并且沿着后表面形成有突出部分，由此可以防止电池错误地插入到装置中。突出部具有相对于后表面急剧倾斜的倾斜表面，并且当电池从装置卸载时，通过保持装置的接触压力的倾斜表面加速电池从装置的卸载。该装置形成有凹槽部分，该凹口部分在电池装载时适于露出电池的另一个突出部分，从而有助于电池的卸载。

8. 发明授权

US08470465B2 Battery device, electronic apparatus, and battery system 有权
公开(公告)号：US08470465B2
公开(公告)日：2013-06-25
申请号：US13458601
申请日：2012-04-27
申请人： Mieko Hara , Toshio Takeshita , Yoichi Miyajima , Hiroaki Sato , Tomonori Watanabe , Naoki Kamaya
发明人： Mieko Hara , Toshio Takeshita , Yoichi Miyajima , Hiroaki Sato , Tomonori Watanabe , Naoki Kamaya
IPC分类号： H01M2/02 , H01M2/06 , H01M2/10
CPC分类号： H01M2/1066 , H01M2/0202 , H01M2/0217 , H01M2/1022 , H01M2/30 , H01M2220/30
摘要： Disclosed is a battery device including a battery enclosure incorporating a battery cell. The battery device further includes an output terminal that outputs power of the battery cell. The battery enclosure includes a first surface, a second surface, a first step surface, a second step surface, a first engaging portion, a second engaging portion, a first groove, and a second groove formed in the second step surface and the second engaging portion, and a recess is provided in at least one of the first step surface and the second step surface.

9. 发明申请

US20130032944A1 MICROELECTRONIC PACKAGE WITH STACKED MICROELECTRONIC ELEMENTS AND METHOD FOR MANUFACTURE THEREOF 有权
标题翻译：具有堆叠微电子元件的微电子封装及其制造方法
公开(公告)号：US20130032944A1
公开(公告)日：2013-02-07
申请号：US13195187
申请日：2011-08-01
申请人： Hiroaki Sato , Norihito Masuda , Belgacem Haba , Ilyas Mohammed
发明人： Hiroaki Sato , Norihito Masuda , Belgacem Haba , Ilyas Mohammed
IPC分类号： H01L23/48 , H01L21/56
CPC分类号： H01L23/28 , H01L21/56 , H01L23/3185 , H01L23/48 , H01L24/05 , H01L24/13 , H01L24/14 , H01L24/24 , H01L24/25 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/82 , H01L24/96 , H01L24/97 , H01L25/0657 , H01L25/105 , H01L2224/02371 , H01L2224/02375 , H01L2224/0401 , H01L2224/04042 , H01L2224/04105 , H01L2224/05548 , H01L2224/12105 , H01L2224/13021 , H01L2224/13024 , H01L2224/131 , H01L2224/13109 , H01L2224/13111 , H01L2224/13144 , H01L2224/14181 , H01L2224/24011 , H01L2224/24105 , H01L2224/24146 , H01L2224/24226 , H01L2224/245 , H01L2224/25171 , H01L2224/2518 , H01L2224/29099 , H01L2224/32145 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48145 , H01L2224/73209 , H01L2224/73253 , H01L2224/73267 , H01L2224/8203 , H01L2224/82101 , H01L2224/82104 , H01L2224/82105 , H01L2224/82947 , H01L2224/92244 , H01L2224/96 , H01L2224/97 , H01L2225/06524 , H01L2225/06568 , H01L2225/1035 , H01L2225/1052 , H01L2924/12042 , H01L2924/181 , H01L2924/18162 , H01L2924/19107 , H01L2924/01029 , H01L2924/01013 , H01L2924/01028 , H01L2924/01079 , H01L2924/00012 , H01L2224/82 , H01L2224/11 , H01L2924/00014 , H01L2924/014 , H01L2924/00
摘要： A microelectronic package may include a stacked microelectronic unit including at least first and second vertically stacked microelectronic elements each having a front face facing a top surface of the package. The front face of the first element may be adjacent the top surface, and the first element may overlie the front face of the second element such that at least a portion of the front face of the second element having an element contact thereon extends beyond an edge of the first element. A conductive structure may electrically connect a first terminal at the top surface to an element contact at the front face of the second element, and include a continuous monolithic metal feature extending along the top surface and through at least a portion of an encapsulant, which is between the top surface and the front face of the second element, towards the element contact.
摘要翻译：微电子封装可以包括堆叠的微电子单元，其包括至少第一和第二垂直堆叠的微电子元件，每个微电子元件具有面向封装的顶表面的正面。第一元件的前表面可以与顶表面相邻，并且第一元件可以覆盖在第二元件的前表面上，使得具有元件接触的第二元件的前表面的至少一部分延伸超过边缘的第一个元素。导电结构可以将顶表面处的第一端子与第二元件的前表面处的元件接触电连接，并且包括沿着顶表面延伸并通过至少一部分密封剂的连续整体金属特征，在第二元件的顶表面和前表面之间，朝向元件接触。

10. 发明申请

US20120286416A1 SEMICONDUCTOR CHIP PACKAGE ASSEMBLY AND METHOD FOR MAKING SAME 审中-公开
标题翻译：半导体芯片封装组件及其制造方法
公开(公告)号：US20120286416A1
公开(公告)日：2012-11-15
申请号：US13105325
申请日：2011-05-11
申请人： Hiroaki Sato , Yukio Hashimoto , Yoshikuni Nakadaira , Norihito Masuda , Belgacem Haba , Ilyas Mohammed , Philip Damberg
发明人： Hiroaki Sato , Yukio Hashimoto , Yoshikuni Nakadaira , Norihito Masuda , Belgacem Haba , Ilyas Mohammed , Philip Damberg
IPC分类号： H01L23/498 , H01L21/60
CPC分类号： H01L24/97 , H01L21/4857 , H01L21/486 , H01L21/561 , H01L23/49822 , H01L23/49827 , H01L24/13 , H01L24/16 , H01L24/32 , H01L24/73 , H01L24/81 , H01L2224/13109 , H01L2224/13111 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/81191 , H01L2224/81444 , H01L2224/81455 , H01L2224/97 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01049 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/15311 , H01L2224/81 , H01L2924/00012 , H01L2924/00
摘要： A microelectronic assembly may include a microelectronic element having a plurality of element contacts at a face thereof, and a compliant dielectric element having a Young's modulus of less than about two gigapascal (GPa) and substrate contacts at a first surface joined to the element contacts. The substrate contacts may be electrically connected with terminals at a second surface of the compliant dielectric element that opposes the first surface, through conductive vias in the compliant dielectric element. A rigid underfill may be between the face of the microelectronic element and the first surface of the compliant dielectric element. The terminals may be usable for bonding the microelectronic assembly to corresponding contacts of a component external to the microelectronic assembly.
摘要翻译：微电子组件可以包括在其表面具有多个元件触点的微电子元件，以及在与元件触点连接的第一表面处具有小于约二千兆帕（GPa）的杨氏模量和柔性介电元件以及在第一表面处的衬底触点。衬底触点可以通过柔性介电元件中的导电通孔与柔性介电元件的与第一表面相对的第二表面的端子电连接。刚性底部填充物可以位于微电子元件的表面和顺应介电元件的第一表面之间。端子可用于将微电子组件接合到微电子组件外部的部件的相应触点。

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