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1. 发明申请

US20170015493A1 Strap Binders Storage Box 审中-公开
标题翻译：带捆扎机储物盒
公开(公告)号：US20170015493A1
公开(公告)日：2017-01-19
申请号：US14798436
申请日：2015-07-13
申请人： Pei Wong , Fan Ren Lee
发明人： Pei Wong , Fan Ren Lee
IPC分类号： B65D85/00 , B65D25/10
CPC分类号： B65D85/70 , B65D25/10 , B65D85/00
摘要： A Strap binder storage box which comprising a storage box body with multiple storage compartments, each storage compartment comprising a strap storage slot, a binder body storage compartment and a hook storage compartment. The strap storage compartment is in an elongated shape, the binder body storage compartment and the hook storage compartment are positioned at the opening and the two ends of the strap storage slot respectively. Wherein, the strap binder which comprising a binder body, and a primary strap and a secondary strap. When storing, the primary and the secondary strap are placed in the strap storage slot, the hook on the primary and the secondary strap are stacked on top of another and then extended into a hook cover of the hook storage compartment, and then are secured by a coupling piece that couples with coupling slots arranged on the strap storage slot.
摘要翻译：一种捆扎捆扎机储存箱，其包括具有多个储存隔间的储物箱主体，每个储藏室包括带存储槽，粘合剂本体储存室和钩存储室。带子储存室是细长的形状，绑带体储存室和挂钩储存室分别位于带存放槽的开口和两端。其中，包括粘合剂主体的带粘合剂，以及初级带和次级带。存储时，将主带和次级带放置在带存放槽中，将初级和次级带上的钩堆叠在另一个的顶部上，然后延伸到钩存储隔间的钩盖中，然后由联接件，其与布置在带存储槽上的联接槽耦合。

2. 发明授权

US09207330B2 Positioning device and positioning method thereof 有权
标题翻译：定位装置及其定位方法
公开(公告)号：US09207330B2
公开(公告)日：2015-12-08
申请号：US13343237
申请日：2012-01-04
申请人： Fan-Ren Chang , He-Sheng Wang , Hung-Wei Chen , Chih-Horng Li , Shu-Min Chuang , Ping-Feng Wang , Chih-Min Hsu , Shan-Yuan Yang
发明人： Fan-Ren Chang , He-Sheng Wang , Hung-Wei Chen , Chih-Horng Li , Shu-Min Chuang , Ping-Feng Wang , Chih-Min Hsu , Shan-Yuan Yang
IPC分类号： G01S19/40
CPC分类号： G01S19/40
摘要： A positioning device and a positioning method thereof are provided. The positioning device can cooperate with a first satellite group and a second satellite group, and it comprises a storage, a receiver and a processor. The receiver is configured to receive a first satellite group signal from the first satellite group and a second satellite group signal from the second satellite group. The processor is electrically connected to the storage and the receiver, and configured to calculate a positioning offset value according to one of the first satellite group signal and the second satellite group signal. In addition, the processor is configured to calculate a positioning result according to the second satellite group signal and the positioning offset, and store the positioning result in the storage.
摘要翻译：提供了一种定位装置及其定位方法。定位装置可以与第一卫星组和第二卫星组合作，并且其包括存储器，接收器和处理器。接收机被配置为从第一卫星组接收第一卫星组信号和从第二卫星组接收第二卫星组信号。处理器电连接到存储器和接收器，并且被配置为根据第一卫星组信号和第二卫星组信号中的一个来计算定位偏移值。此外，处理器被配置为根据第二卫星组信号和定位偏移来计算定位结果，并将定位结果存储在存储器中。

3. 发明授权

US08828713B2 Sensors using high electron mobility transistors 有权
标题翻译：使用高电子迁移率晶体管的传感器
公开(公告)号：US08828713B2
公开(公告)日：2014-09-09
申请号：US12966531
申请日：2010-12-13
申请人： Fan Ren , Stephen John Pearton , Tanmay Lele
发明人： Fan Ren , Stephen John Pearton , Tanmay Lele
IPC分类号： G01N27/00
CPC分类号： G01N33/54306 , G01N27/4145 , G01N33/0045 , H01L29/2003 , H01L29/7787
摘要： Embodiments of the invention include sensors comprising high electron mobility transistors (HEMTs) with capture reagents on a gate region of the HEMTs. Example sensors include HEMTs with a thin gold layer on the gate region and bound antibodies; a thin gold layer on the gate region and chelating agents; a non-native gate dielectric on the gate region; and nanorods of a non-native dielectric with an immobilized enzyme on the gate region. Embodiments including antibodies or enzymes can have the antibodies or enzymes bound to the Au-gate via a binding group. Other embodiments of the invention are methods of using the sensors for detecting breast cancer, prostate cancer, kidney injury, glucose, metals or pH where a signal is generated by the HEMT when a solution is contacted with the sensor. The solution can be blood, saliva, urine, breath condensate, or any solution suspected of containing any specific analyte for the sensor.
摘要翻译：本发明的实施例包括在HEMT的栅极区域上具有捕获试剂的高电子迁移率晶体管（HEMT）的传感器。示例传感器包括在栅极区域上具有薄金层的HEMT和结合的抗体; 栅区上的薄金层和螯合剂; 栅极区域上的非天然栅极电介质; 以及在栅极区域上具有固定化酶的非天然电介质的纳米棒。包括抗体或酶的实施方案可以具有通过结合基团结合到Au-门的抗体或酶。本发明的其它实施方案是使用传感器检测乳腺癌，前列腺癌，肾损伤，葡萄糖，金属或pH的方法，当溶液与传感器接触时，HEMT产生信号。解决方案可以是血液，唾液，尿液，呼吸冷凝液或任何怀疑含有传感器特定分析物的溶液。

4. 发明申请

US20120098599A1 ENHANCEMENT MODE HEMT FOR DIGITAL AND ANALOG APPLICATIONS 审中-公开
标题翻译：数字和模拟应用的增强模式HEMT
公开(公告)号：US20120098599A1
公开(公告)日：2012-04-26
申请号：US13380956
申请日：2010-06-29
申请人： Chih-Yang Chang , Fan Ren , Stephen John Pearton
发明人： Chih-Yang Chang , Fan Ren , Stephen John Pearton
IPC分类号： H03F3/21 , H01L21/335 , H01L29/778 , H01L27/088 , H01L29/20 , H01L29/161
CPC分类号： H01L29/7787 , H01L29/2003 , H01L29/4236 , H01L29/517
摘要： An enhancement mode (E-mode) HEMT is provided that can be used for analog and digital applications. In a specific embodiment, the HEMT can be an AlN/GaN HEMT. The subject E-mode device can be applied to high power, high voltage, high temperature applications, including but not limited to telecommunications, switches, hybrid electric vehicles, power flow control and remote sensing. According to an embodiment of the present invention, E-mode devices can be fabricated by performing an oxygen plasma treatment with respect to the gate area of the HEMT. The oxygen plasma treatment can be, for example, an O2 plasma treatment. In addition, the threshold voltage of the E-mode HEMT can be controlled by adjusting the oxygen plasma exposure time. By using a masking layer protecting regions for depletion mode (D-mode) devices, D-mode and E-mode devices can be fabricated on a same chip.
摘要翻译：提供了可用于模拟和数字应用的增强模式（E模式）HEMT。在具体实施方式中，HEMT可以是AlN / GaN HEMT。主题E模式设备可以应用于高功率，高电压，高温应用，包括但不限于电信，交换机，混合动力电动车辆，电力流量控制和遥感。根据本发明的实施例，可以通过对HEMT的栅极区进行氧等离子体处理来制造E模式器件。氧等离子体处理可以是例如O 2等离子体处理。此外，E模式HEMT的阈值电压可以通过调节氧等离子体暴露时间来控制。通过使用用于耗尽模式（D模式）器件的掩模层保护区域，可以在同一芯片上制造D模式和E模式器件。

5. 发明申请

US20110088456A1 NORMALIZED HYDROGEN SENSING AND METHODS OF FABRICATING A NORMALIZED HYDROGEN SENSOR 审中-公开
标题翻译：普通氢传感器的正规化感应方法和正规化氢传感器的制作方法
公开(公告)号：US20110088456A1
公开(公告)日：2011-04-21
申请号：US12723802
申请日：2010-03-15
申请人： FAN REN , Stephen John Pearton
发明人： FAN REN , Stephen John Pearton
IPC分类号： G01N27/00 , H01L29/778
CPC分类号： G01N33/005 , G01N27/4141 , H01L27/0605 , H01L27/085 , H01L29/42316 , H01L29/51 , H01L29/7787
摘要： HEMT-based hydrogen sensors are provided. In accordance with one embodiment, a normalized sensor is provided having a control HEMT-based sensor connected in series to an active HEMT-based sensor. The control and the active sensor include functionalized gate regions. The gate functionalization for both the control and the active sensor is the same material that selectively absorbs hydrogen gas. The control sensor further includes a protective layer to inhibit its gate functionalization from being exposed to hydrogen. In one embodiment, the final metal for the contacts of the sensors is used as the protective layer. In other embodiments, the protective layer is a dielectric or polymer.
摘要翻译：提供基于HEMT的氢传感器。根据一个实施例，提供了具有与基于活动的基于HEMT的传感器串联连接的基于控制HEMT的传感器的归一化传感器。控制和主动传感器包括功能化的门区。控制和有源传感器的门功能化是选择性吸收氢气的相同材料。控制传感器还包括一个保护层，以阻止其门官能化暴露于氢气。在一个实施例中，用于传感器的触点的最终金属用作保护层。在其它实施方案中，保护层是电介质或聚合物。

6. 发明申请

US20080303121A1 Integrated Electronic Circuitry and Heat Sink 审中-公开
标题翻译：集成电路和散热器
公开(公告)号：US20080303121A1
公开(公告)日：2008-12-11
申请号：US11916910
申请日：2006-05-31
申请人： Jenshan Lin , Fan Ren , Stephen J. Pearton , Travis J. Anderson , Brent P. Gila
发明人： Jenshan Lin , Fan Ren , Stephen J. Pearton , Travis J. Anderson , Brent P. Gila
IPC分类号： H01L23/34 , H01L23/50
CPC分类号： H01L23/552 , H01L23/367 , H01L23/3735 , H01L23/50 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A multi-layer heatsink module for effecting temperature control in a three-dimensional integrated chip is provided. The module includes a high thermal conductivity substrate having first and second opposing sides, and a gallium nitride (GaN) layer disposed on the first side of the substrate. An integrated array of passive and active elements defining electronic circuitry is formed in the GaN layer. A metal ground plane having first and second opposing sides is disposed on the second side of the substrate, with the first side of the ground plane being adjacent to the second side of the substrate. A dielectric layer of low thermal dielectric material is deposited on the back side of the ground plane, and a metal heatsink is bonded to the dielectric layer. A via extends through the dielectric layer from the metal heatsink to the metal ground plane.
摘要翻译：提供了一种用于在三维集成芯片中实现温度控制的多层散热模块。该模块包括具有第一和第二相对侧的高导热性衬底和设置在衬底的第一侧上的氮化镓（GaN）层。在GaN层中形成限定电子电路的无源和有源元件的集成阵列。具有第一和第二相对侧的金属接地平面设置在基板的第二侧上，接地平面的第一侧与基板的第二侧相邻。在接地面的背面侧沉积有低介电常数的电介质层，金属散热片与电介质层接合。通孔从金属散热器延伸穿过电介质层到金属接地平面。

7. 发明授权

US06271069B1 Method of making an article comprising an oxide layer on a GaAs-based semiconductor body 失效
标题翻译：在GaAs基半导体本体上制造包含氧化物层的制品的方法
公开(公告)号：US06271069B1
公开(公告)日：2001-08-07
申请号：US09122558
申请日：1998-07-24
申请人： Young-Kai Chen , Alfred Yi Cho , William Scott Hobson , Minghwei Hong , Jenn-Ming Kuo , Jueinai Raynien Kwo , Donald Winslow Murphy , Fan Ren
发明人： Young-Kai Chen , Alfred Yi Cho , William Scott Hobson , Minghwei Hong , Jenn-Ming Kuo , Jueinai Raynien Kwo , Donald Winslow Murphy , Fan Ren
IPC分类号： H01L2976
CPC分类号： H01L29/517 , C23C14/08 , H01L21/28158 , H01L21/28264 , H01L21/8252 , H01L27/0605 , H01L29/66522 , H01L29/78 , H01L33/44 , H01S5/028
摘要： Disclosed are a method of making GaAs-based enhancement-type MOS-FETs, and articles (e.g., GaAs-based ICs) that comprise such a MOS-FET. The MOS-FETs are planar devices, without etched recess or epitaxial re-growth, with gate oxide that is primarily Ga2O3, and with low midgap interface state density (e.g., at most 1×1011 cm−2 eV−1 at 20° C.). The method involves ion implantation, implant activation in an As-containing atmosphere, surface reconstruction, and in situ deposition of the gate oxide. In preferred embodiments, no processing step subsequent to gate oxide formation is carried out above 300° C. in air, or above about 700° C. in UHV. The method makes possible fabrication of planar enhancement-type MOS-FETs having excellent characteristics, and also makes possible fabrication of complementary MOS-FETs, as well as ICs comprising MOS-FETs and MES-FETs. The method includes deposition of gate oxide of overall composition GaxAyOz, where Ga substantially is in the 3+ oxidation state, A is one or more electropositive stabilizer element adapted for stabilizing Ga in the 3+ oxidation state, x is greater than or equal to zero, z is selected to satisfy the requirement that both Ga and A are substantially fully oxidized, and y/(x+y) is greater than 0.1.
摘要翻译：公开了制造基于GaAs的增强型MOS-FET的方法以及包括这种MOS-FET的制品（例如，基于GaAs的IC）。 MOS-FET是没有蚀刻凹槽或外延再生长的平面器件，其栅极氧化物主要是Ga 2 O 3，并且具有低的中间隙界面态密度（例如，在20℃下至多为1×10 11 cm -2 eV-1）。该方法涉及离子注入，在含As气氛中的注入活化，表面重构和栅极氧化物的原位沉积。在优选的实施方案中，栅极氧化物形成之后的处理步骤在高于300℃的空气中或在高于约700℃的UHV中进行。该方法可以制造具有优异特性的平面增强型MOS-FET，并且还可以制造互补MOS-FET以及包括MOS-FET和MES-FET的IC。该方法包括沉积总体组成为GaxAyOz的栅极氧化物，其中Ga基本上处于3+氧化态，A是一种或多种适用于稳定3+氧化态的Ga的正电荷稳定剂元素，x大于或等于零选择z以满足Ga和A基本上完全氧化，y /（x + y）大于0.1的要求。

8. 发明授权

US5912498A Article comprising an oxide layer on GAN 失效
标题翻译：文章包括GAN上的氧化物层
公开(公告)号：US5912498A
公开(公告)日：1999-06-15
申请号：US948874
申请日：1997-10-10
申请人： William Scott Hobson , Minghwei Hong , James Robert Lothian , Joseph Petrus Mannaerts , Fan Ren
发明人： William Scott Hobson , Minghwei Hong , James Robert Lothian , Joseph Petrus Mannaerts , Fan Ren
IPC分类号： H01L29/78 , H01L21/20 , H01L21/28 , H01L21/316 , H01L29/51 , H01L29/786 , H01L29/76
CPC分类号： H01L29/517 , H01L21/28264 , H01L21/31604
摘要： A high quality oxide layer has been formed on a GaN surface by a method that involves preparation of the GaN such that the surface is essentially atomically clean and essentially atomically ordered, and that further involves exposing the surface to evaporant from a GGG (gallium gadolinium garnet) evaporation source. MOS structures comprising the GaN/oxide combination have shown low leakage current, as well as charge accumulation and depletion.
摘要翻译：通过涉及制备GaN的方法，GaN表面上形成高质量的氧化物层，使得表面基本上是原子上清洁的并且基本上是原子排列的，并且进一步包括将表面从GGG（镓钆石榴石）蒸发源。包括GaN /氧化物组合的MOS结构显示出低的漏电流以及电荷累积和耗尽。

9. 发明授权

US5903037A GaAs-based MOSFET, and method of making same 失效
标题翻译：基于GaAs的MOSFET及其制造方法
公开(公告)号：US5903037A
公开(公告)日：1999-05-11
申请号：US804782
申请日：1997-02-24
申请人： Alfred Yi Cho , Minghwei Hong , James Robert Lothian , Joseph Petrus Mannaerts , Fan Ren
发明人： Alfred Yi Cho , Minghwei Hong , James Robert Lothian , Joseph Petrus Mannaerts , Fan Ren
IPC分类号： H01L29/78 , B82B1/00 , H01L21/28 , H01L21/336 , H01L21/8234 , H01L27/088 , H01L29/51 , H01L21/316 , H01L23/58
CPC分类号： H01L29/517 , H01L21/28158 , H01L21/28264 , H01L29/66522 , H01L2924/0002
摘要： It has been found that a Ga-oxide-containing layer is substantially not etched in HF solution if the layer is a Ga-Gd-oxide with Gd:Ga atomic ratio of more than about 1:7.5, preferably more than 1:4 or even 1:2. This facilitates removal of a protective dielectric (typically SiO.sub.2) layer after an ohmic contact anneal, with the Ga-Gd-oxide gate oxide layer serving as etch stop and not being adversely affected by contact with the HF etchant. Gd-Ge-oxide also exhibits a composition-dependent etch rate in HCl:H.sub.2 O.
摘要翻译：已经发现，如果该层是Gd:Ga原子比大于约1:7.5，优选大于1:4的Ga-Gd氧化物，则在HF溶液中基本上不蚀刻含Ga氧化物层，或甚至1：2。这有助于在欧姆接触退火之后去除保护性电介质（通常为SiO 2）层，其中Ga-Gd氧化物栅极氧化物层用作蚀刻停止，并且不受与HF蚀刻剂的接触的不利影响。 Gd-Ge-氧化物还表现出在HCl：H 2 O中的组成依赖性蚀刻速率。

10. 发明授权

US5620909A Method of depositing thin passivating film on microminiature semiconductor devices 失效
标题翻译：在微型半导体器件上沉积薄钝化膜的方法
公开(公告)号：US5620909A
公开(公告)日：1997-04-15
申请号：US566766
申请日：1995-12-04
申请人： Jenshan Lin , James R. Lothian , Fan Ren
发明人： Jenshan Lin , James R. Lothian , Fan Ren
IPC分类号： H01L21/285 , H01L21/335 , H01L23/31 , H01L29/423 , H01L21/338 , H01L21/50 , H01L29/812
CPC分类号： H01L29/66462 , H01L21/28587 , H01L23/3171 , H01L29/42316 , H01L2924/0002 , H01L2924/19041 , Y10S438/951 , Y10S438/958
摘要： A thin conformal passivating dielectric film is deposited by ECR-CVD on an IC chip comprising semiconductor devices each of which includes a sub-micron-width irregularly shaped gate electrode. A protective layer of patterned resist is formed overlying each passivated device. Additional dielectric material is then deposited by ECP-CVD, at a temperature below the glass transition temperature of the resist, on the surface of the chip. Subsequently, in a lift-off step, the patterned resist together with the additional dielectric material overlying the resist is removed from the chip.
摘要翻译：通过ECR-CVD将薄的共形钝化电介质膜沉积在包括半微米器件的IC芯片上，每个半导体器件包括亚微米宽度不规则形状的栅电极。形成图案化抗蚀剂的保护层，覆盖在每个钝化器件上。然后通过ECP-CVD在低于抗蚀剂的玻璃化转变温度的温度下在芯片的表面上沉积另外的电介质材料。随后，在剥离步骤中，将图案化的抗蚀剂与覆盖抗蚀剂的附加电介质材料一起从芯片上去除。

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