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1. 发明申请

US20060264020A1 Formation of a masking layer on a dielectric region to facilitate formation of a capping layer on electrically conductive regions separated by the dielectric region 有权
标题翻译：在电介质区域上形成掩模层，以便在由电介质区域分隔的导电区域上形成覆盖层
公开(公告)号：US20060264020A1
公开(公告)日：2006-11-23
申请号：US11132841
申请日：2005-05-18
申请人： David Lazovsky , Sandra Malhotra , Thomas Boussie
发明人： David Lazovsky , Sandra Malhotra , Thomas Boussie
IPC分类号： H01L21/44
CPC分类号： H01L21/76829 , B82Y30/00 , H01L21/02183 , H01L21/3148 , H01L21/31633 , H01L21/31695 , H01L21/3185 , H01L21/76826 , H01L21/76849
摘要： A masking layer is formed on a dielectric region of an electronic device so that, during subsequent formation of a capping layer on electrically conductive regions of the electronic device that are separated by the dielectric region, the masking layer inhibits formation of capping layer material on or in the dielectric region. The capping layer can be formed selectively on the electrically conductive regions or non-selectively; in either case (particularly in the latter), capping layer material formed over the dielectric region can subsequently be removed, thus ensuring that capping layer material is formed only on the electrically conductive regions. Silane-based materials, such as silane-based SAMs, can be used to form the masking layer. The capping layer can be formed of an electrically conductive material (e.g., a cobalt alloy, a nickel alloy, tungsten, tantalum, tantalum nitride), a semiconductor material, or an electrically insulative material, and can be formed using any appropriate process, including conventional deposition processes such as electroless deposition, chemical vapor deposition, physical vapor deposition or atomic layer deposition.
摘要翻译：在电子器件的电介质区域上形成掩模层，使得在随后在由电介质区域分离的电子器件的导电区域上形成覆盖层时，掩模层阻止在其上形成覆盖层材料在电介质区域。可以选择性地在导电区域或非选择性地形成覆盖层; 在任一情况下（特别是在后者中），可以随后去除在电介质区域上形成的覆盖层材料，从而确保覆盖层材料仅在导电区域上形成。可以使用诸如硅烷基SAM之类的硅烷基材料来形成掩模层。覆盖层可以由导电材料（例如，钴合金，镍合金，钨，钽，氮化钽），半导体材料或电绝缘材料形成，并且可以使用任何适当的工艺形成，包括常规沉积工艺如无电沉积，化学气相沉积，物理气相沉积或原子层沉积。

2. 发明申请

US20070089857A1 Systems for discretized processing of regions of a substrate 失效
标题翻译：用于基板区域的离散化处理的系统
公开(公告)号：US20070089857A1
公开(公告)日：2007-04-26
申请号：US11351978
申请日：2006-02-10
申请人： Tony Chiang , David Lazovsky , Thomas Boussie , Thomas McWaid , Alexander Gorer
发明人： Tony Chiang , David Lazovsky , Thomas Boussie , Thomas McWaid , Alexander Gorer
IPC分类号： F28F7/00 , C23C16/00
CPC分类号： B01J19/0046 , B01J2219/00286 , B01J2219/00317 , B01J2219/00328 , B01J2219/00333 , B01J2219/00351 , B01J2219/00364 , B01J2219/00369 , B01J2219/00495 , B01J2219/00527 , B01J2219/00603 , B01J2219/00659 , B01J2219/00691 , H01L21/76849
摘要： The present invention provides methods and systems for discretized, combinatorial processing of regions of a substrate such as for the discovery, implementation, optimization, and qualification of new materials, processes, and process sequence integration schemes used in integrated circuit fabrication. A substrate having an array of differentially processed regions thereon is processed by delivering materials to or modifying regions of the substrate.
摘要翻译：本发明提供了用于基板区域的离散化，组合处理的方法和系统，例如用于集成电路制造中使用的新材料，工艺和工艺顺序集成方案的发现，实现，优化和鉴定。通过将材料输送到衬底或修改衬底的区域来处理其上具有差分处理区域阵列的衬底。

3. 发明申请

US20070082487A1 Methods for discretized processing of regions of a substrate 有权
标题翻译：离子处理基板区域的方法
公开(公告)号：US20070082487A1
公开(公告)日：2007-04-12
申请号：US11352016
申请日：2006-02-10
申请人： Tony Chiang , David Lazovsky , Thomas Boussie , Alexander Gorer
发明人： Tony Chiang , David Lazovsky , Thomas Boussie , Alexander Gorer
IPC分类号： H01L21/44
CPC分类号： H01L21/76849 , B82Y30/00 , H01L21/67051 , H01L21/67126
摘要： The present invention provides methods and systems for discretized, combinatorial processing of regions of a substrate such as for the discovery, implementation, optimization, and qualification of new materials, processes, and process sequence integration schemes used in integrated circuit fabrication. A substrate having an array of differentially processed regions thereon is processed by delivering materials to or modifying regions of the substrate.
摘要翻译：本发明提供了用于基板区域的离散化，组合处理的方法和系统，例如用于集成电路制造中使用的新材料，工艺和工艺顺序集成方案的发现，实现，优化和鉴定。通过将材料输送到衬底或修改衬底的区域来处理其上具有差分处理区域阵列的衬底。

4. 发明申请

US20060292845A1 Processing substrates using site-isolated processing 有权
标题翻译：使用现场隔离处理处理衬底
公开(公告)号：US20060292845A1
公开(公告)日：2006-12-28
申请号：US11418689
申请日：2006-05-05
申请人： Tony Chiang , David Lazovsky , Sandra Malhotra
发明人： Tony Chiang , David Lazovsky , Sandra Malhotra
IPC分类号： C23C16/00 , H01L21/44
CPC分类号： H01L22/26 , H01L21/32051 , H01L21/67028 , H01L21/6708 , H01L21/67207 , H01L21/67745 , H01L21/76834 , H01L21/76841 , H01L21/76849 , H01L21/76871
摘要： Substrate processing systems and methods are described for processing substrates having two or more regions. The processing includes one or more of molecular self-assembly and combinatorial processing. At least one of materials, processes, processing conditions, material application sequences, and process sequences is different for the processing in at least one region of the substrate relative to at least one other region of the substrate. Processing systems are described that include numerous processing modules. The modules include a site-isolated reactor (SIR) configured for one or more of molecular self-assembly and combinatorial processing of a substrate.
摘要翻译：描述了用于处理具有两个或更多个区域的基板的基板处理系统和方法。该处理包括分子自组装和组合处理中的一种或多种。材料，工艺，加工条件，材料应用顺序和工艺顺序中的至少一个不同于衬底相对于衬底的至少一个其它区域的至少一个区域中的处理。描述了包括许多处理模块的处理系统。模块包括配置用于衬底的分子自组装和组合处理中的一个或多个的位点隔离反应器（SIR）。

5. 发明授权

US08803124B2 Creating an embedded reram memory from a high-K metal gate transistor structure 有权
标题翻译：从高K金属栅极晶体管结构创建嵌入式reram存储器
公开(公告)号：US08803124B2
公开(公告)日：2014-08-12
申请号：US13407997
申请日：2012-02-29
申请人： Dipankar Pramanik , Tony P. Chiang , David Lazovsky
发明人： Dipankar Pramanik , Tony P. Chiang , David Lazovsky
IPC分类号： H01L47/00
CPC分类号： H01L45/1658 , H01L27/2436 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/16 , H01L45/1683
摘要： An embodiment of the present invention sets forth an embedded resistive memory cell that includes a first stack of deposited layers, a second stack of deposited layers, a first electrode disposed under a first portion of the first stack, and a second electrode disposed under a second portion of the first stack and extending from under the second portion of the first stack to under the second stack. The second electrode is disposed proximate to the first electrode within the embedded resistive memory cell. The first stack of deposited layers includes a dielectric layer, a high-k dielectric layer disposed above the dielectric layer, and a metal layer disposed above the high-k dielectric layer. The second stack of deposited layers includes a high-k dielectric layer formed simultaneously with the high-k dielectric layer included in the first stack, and a metal layer disposed above the high-k dielectric layer.
摘要翻译：本发明的实施例提出了一种嵌入式电阻式存储单元，其包括沉积层的第一堆叠，沉积层的第二堆叠，设置在第一堆叠的第一部分下方的第一电极和设置在第二堆叠下的第二电极的第二电极第一堆叠的部分并且从第一堆叠的第二部分下方延伸到第二堆叠下方。第二电极设置在嵌入式电阻式存储单元内靠近第一电极。第一堆沉积层包括介电层，设置在电介质层上方的高k电介质层和设置在高k电介质层上方的金属层。第二层沉积层包括与包含在第一堆叠中的高k电介质层同时形成的高k电介质层和设置在高k电介质层上方的金属层。

6. 发明申请

US20070082508A1 Methods for discretized processing and process sequence integration of regions of a substrate 有权
标题翻译：离散化处理方法和基板区域的工艺顺序整合
公开(公告)号：US20070082508A1
公开(公告)日：2007-04-12
申请号：US11352077
申请日：2006-02-10
申请人： Tony Chiang , David Lazovsky , Thomas Boussie , Alexander Gorer
发明人： Tony Chiang , David Lazovsky , Thomas Boussie , Alexander Gorer
IPC分类号： H01L21/00 , H01L21/311 , H01L21/302
CPC分类号： H01L21/67011 , C23C14/54 , C23C16/4412 , C23C16/45544 , C23C16/4557 , C23C16/45578 , C23C16/4583 , C23C16/46 , C23C16/52 , H01J37/32449 , H01J37/32513 , H01J37/32724 , H01J2237/166 , H01J2237/20228 , H01J2237/20235 , H01L21/6715 , H01L21/76849 , H01L22/20 , H01L2924/0002 , Y10S438/907 , Y10S438/913 , Y10T137/8593 , H01L2924/00
摘要： The present invention provides methods and systems for discretized, combinatorial processing of regions of a substrate such as for the discovery, implementation, optimization, and qualification of new materials, processes, and process sequence integration schemes used in integrated circuit fabrication. A substrate having an array of differentially processed regions thereon is processed by delivering materials to or modifying regions of the substrate.
摘要翻译：本发明提供了用于基板区域的离散化，组合处理的方法和系统，例如用于集成电路制造中使用的新材料，工艺和工艺顺序集成方案的发现，实现，优化和鉴定。通过将材料输送到衬底或修改衬底的区域来处理其上具有差分处理区域阵列的衬底。

7. 发明申请

US20060261434A1 Formation of a masking layer on a dielectric region to facilitate formation of a capping layer on electrically conductive regions separated by the dielectric region 有权
公开(公告)号：US20060261434A1
公开(公告)日：2006-11-23
申请号：US11132817
申请日：2005-05-18
申请人： David Lazovsky , Sandra Malhotra , Thomas Boussie
发明人： David Lazovsky , Sandra Malhotra , Thomas Boussie
IPC分类号： H01L21/76 , H01L29/00
CPC分类号： H01L21/7685 , B82Y30/00 , H01L21/02118 , H01L21/02167 , H01L21/0217 , H01L21/02203 , H01L21/288 , H01L21/31 , H01L21/76834
摘要： A masking layer is formed on a dielectric region of an electronic device so that, during subsequent formation of a capping layer on electrically conductive regions of the electronic device that are separated by the dielectric region, the masking layer inhibits formation of capping layer material on or in the dielectric region. The capping layer can be formed selectively on the electrically conductive regions or non-selectively; in either case (particularly in the latter), capping layer material formed over the dielectric region can subsequently be removed, thus ensuring that capping layer material is formed only on the electrically conductive regions. Silane-based materials, such as silane-based SAMs, can be used to form the masking layer. The capping layer can be formed of an electrically conductive material (e.g., a cobalt alloy, a nickel alloy, tungsten, tantalum, tantalum nitride), a semiconductor material, or an electrically insulative material, and can be formed using any appropriate process, including conventional deposition processes such as electroless deposition, chemical vapor deposition, physical vapor deposition or atomic layer deposition.

8. 发明申请

US20060108320A1 Molecular self-assembly in substrate processing 有权
标题翻译：基板加工中的分子自组装
公开(公告)号：US20060108320A1
公开(公告)日：2006-05-25
申请号：US11284572
申请日：2005-11-22
申请人： David Lazovsky , Tony Chiang , Majid Keshavarz
发明人： David Lazovsky , Tony Chiang , Majid Keshavarz
IPC分类号： H01L21/302 , C23F1/00
CPC分类号： H01L23/5329 , B82Y30/00 , H01L21/31 , H01L21/76805 , H01L21/76814 , H01L21/76831 , H01L21/76843 , H01L21/76846 , H01L21/76849 , H01L21/76873 , H01L21/76879 , H01L28/65 , H01L29/06 , H01L2924/0002 , Y10T428/249953 , H01L2924/00
摘要： Systems and methods for molecular self-assembly are provided. The molecular self-assembly receives a substrate that includes one or more regions of dielectric material. A molecularly self-assembled layer is formed on an exposed surface of the dielectric material. The molecularly self-assembled layer includes material(s) having a molecular characteristic and/or a molecular type that includes one or more of a molecular characteristic and/or a molecular type of a head group of molecules of the material, a molecular characteristic and/or a molecular type of a terminal group of molecules of the material, and a molecular characteristic and/or a molecular type of a linking group of molecules of the material. The molecular characteristic(s) and molecular type(s) are selected according to at least one pre-specified property of the molecularly self-assembled layer.
摘要翻译：提供了分子自组装的系统和方法。分子自组装接收包括电介质材料的一个或多个区域的衬底。在介电材料的暴露表面上形成分子自组装层。分子自组装层包括具有分子特征和/或分子类型的材料，其包括材料分子的头基团的分子特征和/或分子类型中的一种或多种，分子特征和 /或分子类型的材料的分子的末端基团，以及材料分子的连接基团的分子特征和/或分子类型。分子特征和分子类型根据分子自组装层的至少一个预先确定的性质来选择。

9. 发明申请

US20060060301A1 Substrate processing using molecular self-assembly 审中-公开
标题翻译：使用分子自组装的基板加工
公开(公告)号：US20060060301A1
公开(公告)日：2006-03-23
申请号：US11231047
申请日：2005-09-19
申请人： David Lazovsky , Tony Chiang , Sandra Malhotra
发明人： David Lazovsky , Tony Chiang , Sandra Malhotra
IPC分类号： H01L21/306 , C23F1/00
CPC分类号： B82Y30/00 , H01L21/76834 , H01L21/76849
摘要： A system for molecular self-assembly referred to herein as a “molecular self-assembly system (MSAS)” includes at least one interface configured to receive at least one substrate. The MSAS also includes at least one molecular self-assembly module coupled to the interface. The MSAS can also include one or more of pre-processing modules, other molecular self-assembly processing modules, and post-processing modules, and may include any number, combination, and/or type of other modules. Each module of the MSAS can contain at least one of a number of different processes as appropriate to a processing configuration of the MSAS. The MSAS also includes at least one handler coupled to the interface and configured to move the substrate between the interface and one or more of the modules.
摘要翻译：本文中称为“分子自组装系统（MSAS）”的分子自组装系统包括至少一个接口，其被配置为接收至少一个衬底。 MSAS还包括耦合到该界面的至少一个分子自组装模块。 MSAS还可以包括一个或多个预处理模块，其他分子自组装处理模块和后处理模块，并且可以包括其他模块的任何数量，组合和/或类型。 MSAS的每个模块可以包含适合于MSAS的处理配置的多个不同进程中的至少一个。 MSAS还包括至少一个处理器，其耦合到接口并且被配置为在接口和一个或多个模块之间移动衬底。

10. 发明申请

US20070202614A1 METHOD AND APPARATUS FOR COMBINATORIALLY VARYING MATERIALS, UNIT PROCESS AND PROCESS SEQUENCE 审中-公开
标题翻译：用于组合变化材料的方法和装置，单元过程和过程序列
公开(公告)号：US20070202614A1
公开(公告)日：2007-08-30
申请号：US11674132
申请日：2007-02-12
申请人： Tony Chiang , David Lazovsky , Kurt Weiner , Gustavo Pinto , Thomas Boussie , Alexander Gorer
发明人： Tony Chiang , David Lazovsky , Kurt Weiner , Gustavo Pinto , Thomas Boussie , Alexander Gorer
IPC分类号： H01L21/66
CPC分类号： H01L22/20 , C23C14/54 , C23C16/52 , H01L21/76849 , H01L22/14 , Y02P80/40
摘要： A method for analyzing and optimizing fabrication techniques using variations of materials, unit processes, and process sequences is provided. In the method, a subset of a semiconductor manufacturing process sequence and build is analyzed for optimization. During the execution of the subset of the manufacturing process sequence, the materials, unit processes, and process sequence for creating a certain structure is varied. During the combinatorial processing, the materials, unit processes, or process sequence is varied between the discrete regions of a semiconductor substrate, wherein within each of the regions the process yields a substantially uniform or consistent result that is representative of a result of a commercial manufacturing operation. A tool for optimizing a process sequence is also provided.
摘要翻译：提供了一种使用材料，单元过程和工艺顺序的变化来分析和优化制造技术的方法。在该方法中，分析半导体制造过程序列和构建的子集以进行优化。在执行制造过程序列的子集期间，用于创建特定结构的材料，单元过程和过程顺序是变化的。在组合处理期间，材料，单元工艺或工艺顺序在半导体衬底的离散区域之间变化，其中在每个区域内，该工艺产生基本均匀或一致的结果，其代表商业制造的结果操作。还提供了用于优化处理顺序的工具。

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