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1. 发明授权

US08803124B2 Creating an embedded reram memory from a high-K metal gate transistor structure 有权
标题翻译：从高K金属栅极晶体管结构创建嵌入式reram存储器
公开(公告)号：US08803124B2
公开(公告)日：2014-08-12
申请号：US13407997
申请日：2012-02-29
申请人： Dipankar Pramanik , Tony P. Chiang , David Lazovsky
发明人： Dipankar Pramanik , Tony P. Chiang , David Lazovsky
IPC分类号： H01L47/00
CPC分类号： H01L45/1658 , H01L27/2436 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/16 , H01L45/1683
摘要： An embodiment of the present invention sets forth an embedded resistive memory cell that includes a first stack of deposited layers, a second stack of deposited layers, a first electrode disposed under a first portion of the first stack, and a second electrode disposed under a second portion of the first stack and extending from under the second portion of the first stack to under the second stack. The second electrode is disposed proximate to the first electrode within the embedded resistive memory cell. The first stack of deposited layers includes a dielectric layer, a high-k dielectric layer disposed above the dielectric layer, and a metal layer disposed above the high-k dielectric layer. The second stack of deposited layers includes a high-k dielectric layer formed simultaneously with the high-k dielectric layer included in the first stack, and a metal layer disposed above the high-k dielectric layer.
摘要翻译：本发明的实施例提出了一种嵌入式电阻式存储单元，其包括沉积层的第一堆叠，沉积层的第二堆叠，设置在第一堆叠的第一部分下方的第一电极和设置在第二堆叠下的第二电极的第二电极第一堆叠的部分并且从第一堆叠的第二部分下方延伸到第二堆叠下方。第二电极设置在嵌入式电阻式存储单元内靠近第一电极。第一堆沉积层包括介电层，设置在电介质层上方的高k电介质层和设置在高k电介质层上方的金属层。第二层沉积层包括与包含在第一堆叠中的高k电介质层同时形成的高k电介质层和设置在高k电介质层上方的金属层。

2. 发明授权

US08878152B2 Nonvolatile resistive memory element with an integrated oxygen isolation structure 有权
标题翻译：具有集成氧隔离结构的非易失性电阻式存储元件
公开(公告)号：US08878152B2
公开(公告)日：2014-11-04
申请号：US13408103
申请日：2012-02-29
申请人： Yun Wang , Tony P. Chiang , Imran Hashim , Dipankar Pramanik
发明人： Yun Wang , Tony P. Chiang , Imran Hashim , Dipankar Pramanik
IPC分类号： H01L29/02
CPC分类号： H01L45/16 , H01L27/2463 , H01L45/10 , H01L45/12 , H01L45/1233 , H01L45/146 , H01L45/1675
摘要： A nonvolatile resistive memory element includes one or more novel oxygen isolation structures that protect the resistive switching material of the memory element from oxygen migration. One such oxygen isolation structure comprises an oxygen barrier layer that isolates the resistive switching material from other portions of the resistive memory device during fabrication and/or operation of the memory device. Another such oxygen isolation structure comprises a sacrificial layer that reacts with unwanted oxygen migrating toward the resistive switching material during fabrication and/or operation of the memory device.
摘要翻译：非易失性电阻存储元件包括一个或多个新颖的氧隔离结构，其保护存储元件的电阻开关材料免于氧迁移。一个这样的氧隔离结构包括氧阻隔层，其在制造和/或操作存储器件期间将电阻性开关材料与电阻式存储器件的其它部分隔离。另一种这样的氧隔离结构包括牺牲层，其在存储器件的制造和/或操作期间与向电阻开关材料迁移的不想要的氧化反应。

3. 发明授权

US08563366B2 Memory device having an integrated two-terminal current limiting resistor 有权
公开(公告)号：US08563366B2
公开(公告)日：2013-10-22
申请号：US13407359
申请日：2012-02-28
申请人： Dipankar Pramanik , Tony P. Chiang , Mankoo Lee
发明人： Dipankar Pramanik , Tony P. Chiang , Mankoo Lee
IPC分类号： H01L29/8605
CPC分类号： H01L45/14 , G11C13/0002 , G11C13/0007 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C2013/0045 , G11C2013/0073 , G11C2013/0078 , G11C2013/0092 , G11C2213/76 , H01L27/2409 , H01L27/2463 , H01L45/08 , H01L45/10 , H01L45/12 , H01L45/1233 , H01L45/146 , H01L45/16
摘要： A resistor structure incorporated into a resistive switching memory cell or device to form memory devices with improved device performance and lifetime is provided. The resistor structure may be a two-terminal structure designed to reduce the maximum current flowing through a memory device. A method is also provided for making such memory device. The method includes depositing a resistor structure and depositing a variable resistance layer of a resistive switching memory cell of the memory device, where the resistor structure is disposed in series with the variable resistance layer to limit the switching current of the memory device. The incorporation of the resistor structure is very useful in obtaining desirable levels of device switching currents that meet the switching specification of various types of memory devices. The memory devices may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices.

4. 发明申请

US20130224928A1 MEMORY DEVICE HAVING AN INTEGRATED TWO-TERMINAL CURRENT LIMITING RESISTOR 有权
标题翻译：具有集成式两端限流电阻的存储器件
公开(公告)号：US20130224928A1
公开(公告)日：2013-08-29
申请号：US13407359
申请日：2012-02-28
申请人： Dipankar Pramanik , Tony P. Chiang , Mankoo Lee
发明人： Dipankar Pramanik , Tony P. Chiang , Mankoo Lee
IPC分类号： H01L21/02
CPC分类号： H01L45/14 , G11C13/0002 , G11C13/0007 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C2013/0045 , G11C2013/0073 , G11C2013/0078 , G11C2013/0092 , G11C2213/76 , H01L27/2409 , H01L27/2463 , H01L45/08 , H01L45/10 , H01L45/12 , H01L45/1233 , H01L45/146 , H01L45/16
摘要： A resistor structure incorporated into a resistive switching memory cell or device to form memory devices with improved device performance and lifetime is provided. The resistor structure may be a two-terminal structure designed to reduce the maximum current flowing through a memory device. A method is also provided for making such memory device. The method includes depositing a resistor structure and depositing a variable resistance layer of a resistive switching memory cell of the memory device, where the resistor structure is disposed in series with the variable resistance layer to limit the switching current of the memory device. The incorporation of the resistor structure is very useful in obtaining desirable levels of device switching currents that meet the switching specification of various types of memory devices. The memory devices may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices.
摘要翻译：提供了并入电阻式开关存储单元或装置中以形成具有改进的器件性能和寿命的存储器件的电阻器结构。电阻器结构可以是设计成减小流过存储器件的最大电流的两端结构。还提供了一种用于制造这种存储器件的方法。该方法包括沉积电阻器结构并沉积存储器件的电阻式开关存储单元的可变电阻层，其中电阻器结构与可变电阻层串联设置以限制存储器件的开关电流。电阻器结构的结合对于获得满足各种类型的存储器件的开关规范的期望的器件开关电流水平是非常有用的。存储器件可以形成为可用于各种电子器件的大容量非易失性存储器集成电路的一部分。

5. 发明申请

US20130221317A1 CREATING AN EMBEDDED RERAM MEMORY FROM A HIGH-K METAL GATE TRANSISTOR STRUCTURE 有权
标题翻译：从高K金属栅晶体管结构创建嵌入式RERAM存储器
公开(公告)号：US20130221317A1
公开(公告)日：2013-08-29
申请号：US13407997
申请日：2012-02-29
申请人： Dipankar Pramanik , Tony P. Chiang , David Lazosky
发明人： Dipankar Pramanik , Tony P. Chiang , David Lazosky
IPC分类号： H01L47/00 , H01L21/02
CPC分类号： H01L45/1658 , H01L27/2436 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/16 , H01L45/1683
摘要： An embodiment of the present invention sets forth an embedded resistive memory cell that includes a first stack of deposited layers, a second stack of deposited layers, a first electrode disposed under a first portion of the first stack, and a second electrode disposed under a second portion of the first stack and extending from under the second portion of the first stack to under the second stack. The second electrode is disposed proximate to the first electrode within the embedded resistive memory cell. The first stack of deposited layers includes a dielectric layer, a high-k dielectric layer disposed above the dielectric layer, and a metal layer disposed above the high-k dielectric layer. The second stack of deposited layers includes a high-k dielectric layer formed simultaneously with the high-k dielectric layer included in the first stack, and a metal layer disposed above the high-k dielectric layer.
摘要翻译：本发明的实施例提出了一种嵌入式电阻式存储单元，其包括沉积层的第一堆叠，沉积层的第二堆叠，设置在第一堆叠的第一部分下方的第一电极和设置在第二堆叠下的第二电极的第二电极第一堆叠的部分并且从第一堆叠的第二部分下方延伸到第二堆叠下方。第二电极设置在嵌入式电阻式存储单元内靠近第一电极。第一堆沉积层包括介电层，设置在电介质层上方的高k电介质层和设置在高k电介质层上方的金属层。第二层沉积层包括与包含在第一堆叠中的高k电介质层同时形成的高k电介质层和设置在高k电介质层上方的金属层。

6. 发明申请

US20130221307A1 NONVOLATILE RESISTIVE MEMORY ELEMENT WITH AN INTEGRATED OXYGEN ISOLATION STRUCTURE 有权
标题翻译：具有一体化氧分离结构的非挥发性电阻记忆元件
公开(公告)号：US20130221307A1
公开(公告)日：2013-08-29
申请号：US13408103
申请日：2012-02-29
申请人： Yun Wang , Tony P. Chiang , Imran Hashim , Dipankar Pramanik
发明人： Yun Wang , Tony P. Chiang , Imran Hashim , Dipankar Pramanik
IPC分类号： H01L45/00
CPC分类号： H01L45/16 , H01L27/2463 , H01L45/10 , H01L45/12 , H01L45/1233 , H01L45/146 , H01L45/1675
摘要： A nonvolatile resistive memory element includes one or more novel oxygen isolation structures that protect the resistive switching material of the memory element from oxygen migration. One such oxygen isolation structure comprises an oxygen barrier layer that isolates the resistive switching material from other portions of the resistive memory device during fabrication and/or operation of the memory device. Another such oxygen isolation structure comprises a sacrificial layer that reacts with unwanted oxygen migrating toward the resistive switching material during fabrication and/or operation of the memory device.
摘要翻译：非易失性电阻存储元件包括一个或多个新颖的氧隔离结构，其保护存储元件的电阻开关材料免于氧迁移。一个这样的氧隔离结构包括氧阻隔层，其在制造和/或操作存储器件期间将电阻性开关材料与电阻式存储器件的其它部分隔离。另一种这样的氧隔离结构包括牺牲层，其在存储器件的制造和/或操作期间与向电阻开关材料迁移的不想要的氧化反应。

7. 发明授权

US08466005B2 Method for forming metal oxides and silicides in a memory device 有权
公开(公告)号：US08466005B2
公开(公告)日：2013-06-18
申请号：US13188835
申请日：2011-07-22
申请人： Dipankar Pramanik , Tony P. Chiang , Tim Minvielle , Takeshi Yamaguchi
发明人： Dipankar Pramanik , Tony P. Chiang , Tim Minvielle , Takeshi Yamaguchi
IPC分类号： H01L21/00 , H01L21/16 , H01L21/332
CPC分类号： H01L45/1253 , H01L27/101 , H01L27/2463 , H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/16 , H01L45/1608
摘要： Embodiments of the invention generally relate to memory devices and methods for fabricating such memory devices. In one embodiment, a method for fabricating a resistive switching memory device includes depositing a metallic layer on a lower electrode disposed on a substrate and exposing the metallic layer to an activated oxygen source while heating the substrate to an oxidizing temperature within a range from about 300° C. to about 600° C. and forming a metal oxide layer from an upper portion of the metallic layer during an oxidation process. The lower electrode contains a silicon material and the metallic layer contains hafnium or zirconium. Subsequent to the oxidation process, the method further includes heating the substrate to an annealing temperature within a range from greater than 600° C. to about 850° C. while forming a metal silicide layer from a lower portion of the metallic layer during a silicidation process.

8. 发明授权

US09472423B2 Method for suppressing lattice defects in a semiconductor substrate 有权
标题翻译：抑制半导体衬底中的晶格缺陷的方法
公开(公告)号：US09472423B2
公开(公告)日：2016-10-18
申请号：US11928142
申请日：2007-10-30
申请人： Victor Moroz , Dipankar Pramanik
发明人： Victor Moroz , Dipankar Pramanik
IPC分类号： H01L21/324 , H01L21/265 , H01L29/10 , H01L29/78
CPC分类号： H01L21/324 , H01L21/26506 , H01L21/26513 , H01L29/1054 , H01L29/1079 , H01L29/7848
摘要： A method for suppressing the formation of leakage-promoting defects in a crystal lattice following dopant implantation in the lattice. The process provides a compressive layer of atoms, these atoms having a size greater than that of the lattice member atoms. The lattice is then annealed for a time sufficient for interstitial defect atoms to be emitted from the compressive layer, and in that manner energetically stable defects are formed in the lattice at a distance from the compressive layer.
摘要翻译：一种用于抑制在晶格中的掺杂剂注入之后的晶格中的渗漏促进缺陷的形成的方法。该方法提供原子的压缩层，这些原子的尺寸大于晶格构件原子的尺寸。然后将晶格退火足以使间隙缺陷原子从压缩层发射的时间，并且以这种方式，在离压缩层一定距离处的晶格中形成能量稳定的缺陷。

9. 发明申请

US20140055152A1 CIRCULAR TRANSMISSION LINE METHODS COMPATIBLE WITH COMBINATORIAL PROCESSING OF SEMICONDUCTORS 有权
标题翻译：圆形传输线方法与半导体的组合处理兼容
公开(公告)号：US20140055152A1
公开(公告)日：2014-02-27
申请号：US13594292
申请日：2012-08-24
申请人： Amol Joshi , Charlene Chen , John Foster , Zhendong Hong , Olov Karlsson , Bei Li , Dipankar Pramanik , Usha Raghuram , Mark Victor Raymond , Jingang Su , Bin Yang
发明人： Amol Joshi , Charlene Chen , John Foster , Zhendong Hong , Olov Karlsson , Bei Li , Dipankar Pramanik , Usha Raghuram , Mark Victor Raymond , Jingang Su , Bin Yang
IPC分类号： G01R27/08
CPC分类号： G01R27/08 , G01R31/2831 , H01L22/14 , H01L22/20
摘要： Methods and structures are described for determining contact resistivities and Schottky barrier heights for conductors deposited on semiconductor wafers that can be combined with combinatorial processing, allowing thereby numerous processing conditions and materials to be tested concurrently. Methods for using multi-ring as well as single-ring CTLM structures to cancel parasitic resistance are also described, as well as structures and processes for inline monitoring of properties.
摘要翻译：描述了用于确定沉积在可与组合处理组合的半导体晶片上的导体的接触电阻率和肖特基势垒高度的方法和结构，从而允许同时测试许多处理条件和材料。还描述了使用多环以及单环CTLM结构来消除寄生电阻的方法，以及用于在线监测性质的结构和方法。

10. 发明授权

US08637413B2 Nonvolatile resistive memory element with a passivated switching layer 有权
标题翻译：具有钝化开关层的非易失性电阻性存储元件
公开(公告)号：US08637413B2
公开(公告)日：2014-01-28
申请号：US13309813
申请日：2011-12-02
申请人： Charlene Chen , Dipankar Pramanik
发明人： Charlene Chen , Dipankar Pramanik
IPC分类号： H01L21/31 , H01L29/00 , G11C11/00
CPC分类号： H01L45/146 , H01L27/2463 , H01L45/08 , H01L45/1233 , H01L45/1616 , H01L45/1625 , H01L45/1641 , H01L45/165
摘要： A nonvolatile resistive memory element has a novel variable resistance layer that is passivated with non-metallic dopant atoms, such as nitrogen, either during or after deposition of the switching layer. The presence of the non-metallic dopant atoms in the variable resistance layer enables the switching layer to operate with reduced switching current while maintaining improved data retention properties.
摘要翻译：非易失性电阻存储元件具有新颖的可变电阻层，其在开关层沉积期间或之后被非金属掺杂剂原子如氮气钝化。可变电阻层中的非金属掺杂剂原子的存在使得开关层能够以降低的开关电流工作，同时保持改进的数据保持性能。

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