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1. 发明申请

US20070202614A1 METHOD AND APPARATUS FOR COMBINATORIALLY VARYING MATERIALS, UNIT PROCESS AND PROCESS SEQUENCE 审中-公开
标题翻译：用于组合变化材料的方法和装置，单元过程和过程序列
公开(公告)号：US20070202614A1
公开(公告)日：2007-08-30
申请号：US11674132
申请日：2007-02-12
申请人： Tony Chiang , David Lazovsky , Kurt Weiner , Gustavo Pinto , Thomas Boussie , Alexander Gorer
发明人： Tony Chiang , David Lazovsky , Kurt Weiner , Gustavo Pinto , Thomas Boussie , Alexander Gorer
IPC分类号： H01L21/66
CPC分类号： H01L22/20 , C23C14/54 , C23C16/52 , H01L21/76849 , H01L22/14 , Y02P80/40
摘要： A method for analyzing and optimizing fabrication techniques using variations of materials, unit processes, and process sequences is provided. In the method, a subset of a semiconductor manufacturing process sequence and build is analyzed for optimization. During the execution of the subset of the manufacturing process sequence, the materials, unit processes, and process sequence for creating a certain structure is varied. During the combinatorial processing, the materials, unit processes, or process sequence is varied between the discrete regions of a semiconductor substrate, wherein within each of the regions the process yields a substantially uniform or consistent result that is representative of a result of a commercial manufacturing operation. A tool for optimizing a process sequence is also provided.
摘要翻译：提供了一种使用材料，单元过程和工艺顺序的变化来分析和优化制造技术的方法。在该方法中，分析半导体制造过程序列和构建的子集以进行优化。在执行制造过程序列的子集期间，用于创建特定结构的材料，单元过程和过程顺序是变化的。在组合处理期间，材料，单元工艺或工艺顺序在半导体衬底的离散区域之间变化，其中在每个区域内，该工艺产生基本均匀或一致的结果，其代表商业制造的结果操作。还提供了用于优化处理顺序的工具。

2. 发明申请

US20070202610A1 METHOD AND APPARATUS FOR COMBINATORIALLY VARYING MATERIALS, UNIT PROCESS AND PROCESS SEQUENCE 审中-公开
公开(公告)号：US20070202610A1
公开(公告)日：2007-08-30
申请号：US11674137
申请日：2007-02-12
申请人： Tony Chiang , David Lazovsky , Kurt Weiner , Gustavo Pinto , Thomas Boussie , Alexander Gorer
发明人： Tony Chiang , David Lazovsky , Kurt Weiner , Gustavo Pinto , Thomas Boussie , Alexander Gorer
IPC分类号： C40B30/02 , C40B40/18 , H01L21/00 , C40B50/00
CPC分类号： H01L22/20 , C23C14/54 , C23C16/52 , H01L21/76849 , H01L22/14 , Y02P80/40
摘要： A method for analyzing and optimizing fabrication techniques using variations of materials, unit processes, and process sequences is provided. In the method, a subset of a semiconductor manufacturing process sequence and build is analyzed for optimization. During the execution of the subset of the manufacturing process sequence, the materials, unit processes, and process sequence for creating a certain structure is varied. During the combinatorial processing, the materials, unit processes, or process sequence is varied between the discrete regions of a semiconductor substrate, wherein within each of the regions the process yields a substantially uniform or consistent result that is representative of a result of a commercial manufacturing operation. A tool for optimizing a process sequence is also provided.

3. 发明申请

US20070082508A1 Methods for discretized processing and process sequence integration of regions of a substrate 有权
标题翻译：离散化处理方法和基板区域的工艺顺序整合
公开(公告)号：US20070082508A1
公开(公告)日：2007-04-12
申请号：US11352077
申请日：2006-02-10
申请人： Tony Chiang , David Lazovsky , Thomas Boussie , Alexander Gorer
发明人： Tony Chiang , David Lazovsky , Thomas Boussie , Alexander Gorer
IPC分类号： H01L21/00 , H01L21/311 , H01L21/302
CPC分类号： H01L21/67011 , C23C14/54 , C23C16/4412 , C23C16/45544 , C23C16/4557 , C23C16/45578 , C23C16/4583 , C23C16/46 , C23C16/52 , H01J37/32449 , H01J37/32513 , H01J37/32724 , H01J2237/166 , H01J2237/20228 , H01J2237/20235 , H01L21/6715 , H01L21/76849 , H01L22/20 , H01L2924/0002 , Y10S438/907 , Y10S438/913 , Y10T137/8593 , H01L2924/00
摘要： The present invention provides methods and systems for discretized, combinatorial processing of regions of a substrate such as for the discovery, implementation, optimization, and qualification of new materials, processes, and process sequence integration schemes used in integrated circuit fabrication. A substrate having an array of differentially processed regions thereon is processed by delivering materials to or modifying regions of the substrate.
摘要翻译：本发明提供了用于基板区域的离散化，组合处理的方法和系统，例如用于集成电路制造中使用的新材料，工艺和工艺顺序集成方案的发现，实现，优化和鉴定。通过将材料输送到衬底或修改衬底的区域来处理其上具有差分处理区域阵列的衬底。

4. 发明申请

US20070089857A1 Systems for discretized processing of regions of a substrate 失效
标题翻译：用于基板区域的离散化处理的系统
公开(公告)号：US20070089857A1
公开(公告)日：2007-04-26
申请号：US11351978
申请日：2006-02-10
申请人： Tony Chiang , David Lazovsky , Thomas Boussie , Thomas McWaid , Alexander Gorer
发明人： Tony Chiang , David Lazovsky , Thomas Boussie , Thomas McWaid , Alexander Gorer
IPC分类号： F28F7/00 , C23C16/00
CPC分类号： B01J19/0046 , B01J2219/00286 , B01J2219/00317 , B01J2219/00328 , B01J2219/00333 , B01J2219/00351 , B01J2219/00364 , B01J2219/00369 , B01J2219/00495 , B01J2219/00527 , B01J2219/00603 , B01J2219/00659 , B01J2219/00691 , H01L21/76849
摘要： The present invention provides methods and systems for discretized, combinatorial processing of regions of a substrate such as for the discovery, implementation, optimization, and qualification of new materials, processes, and process sequence integration schemes used in integrated circuit fabrication. A substrate having an array of differentially processed regions thereon is processed by delivering materials to or modifying regions of the substrate.
摘要翻译：本发明提供了用于基板区域的离散化，组合处理的方法和系统，例如用于集成电路制造中使用的新材料，工艺和工艺顺序集成方案的发现，实现，优化和鉴定。通过将材料输送到衬底或修改衬底的区域来处理其上具有差分处理区域阵列的衬底。

5. 发明申请

US20070082487A1 Methods for discretized processing of regions of a substrate 有权
标题翻译：离子处理基板区域的方法
公开(公告)号：US20070082487A1
公开(公告)日：2007-04-12
申请号：US11352016
申请日：2006-02-10
申请人： Tony Chiang , David Lazovsky , Thomas Boussie , Alexander Gorer
发明人： Tony Chiang , David Lazovsky , Thomas Boussie , Alexander Gorer
IPC分类号： H01L21/44
CPC分类号： H01L21/76849 , B82Y30/00 , H01L21/67051 , H01L21/67126
摘要： The present invention provides methods and systems for discretized, combinatorial processing of regions of a substrate such as for the discovery, implementation, optimization, and qualification of new materials, processes, and process sequence integration schemes used in integrated circuit fabrication. A substrate having an array of differentially processed regions thereon is processed by delivering materials to or modifying regions of the substrate.
摘要翻译：本发明提供了用于基板区域的离散化，组合处理的方法和系统，例如用于集成电路制造中使用的新材料，工艺和工艺顺序集成方案的发现，实现，优化和鉴定。通过将材料输送到衬底或修改衬底的区域来处理其上具有差分处理区域阵列的衬底。

6. 发明申请

US20070082485A1 Methods for discretized formation of masking and capping layers on a substrate 有权
标题翻译：在衬底上离散形成掩蔽层和覆盖层的方法
公开(公告)号：US20070082485A1
公开(公告)日：2007-04-12
申请号：US11352083
申请日：2006-02-10
申请人： Tony Chiang , David Lazovsky , Thomas Boussie , Alexander Gorer
发明人： Tony Chiang , David Lazovsky , Thomas Boussie , Alexander Gorer
IPC分类号： H01L21/44
CPC分类号： H01L21/76849 , B82Y30/00 , H01L21/67051 , H01L21/67126
摘要： The present invention provides methods and systems for discretized, combinatorial processing of regions of a substrate such as for the discovery, implementation, optimization, and qualification of new materials, processes, and process sequence integration schemes used in integrated circuit fabrication. A substrate having an array of differentially processed regions thereon is processed by delivering materials to or modifying regions of the substrate.
摘要翻译：本发明提供了用于基板区域的离散化，组合处理的方法和系统，例如用于集成电路制造中使用的新材料，工艺和工艺顺序集成方案的发现，实现，优化和鉴定。通过将材料输送到衬底或修改衬底的区域来处理其上具有差分处理区域阵列的衬底。

7. 发明授权

US08318534B2 Non-volatile resistive-switching memories formed using anodization 有权
标题翻译：使用阳极氧化形成的非易失性电阻式开关存储器
公开(公告)号：US08318534B2
公开(公告)日：2012-11-27
申请号：US13098632
申请日：2011-05-02
申请人： Alexander Gorer , Prashant Phatak , Tony Chiang , Igor Ivanov
发明人： Alexander Gorer , Prashant Phatak , Tony Chiang , Igor Ivanov
IPC分类号： H01L21/00
CPC分类号： H01L45/10 , H01L27/2463 , H01L45/1233 , H01L45/146 , H01L45/1633
摘要： Non-volatile resistive-switching memories formed using anodization are described. A method for forming a resistive-switching memory element using anodization includes forming a metal containing layer, anodizing the metal containing layer at least partially to form a resistive switching metal oxide, and forming a first electrode over the resistive switching metal oxide. In some examples, an unanodized portion of the metal containing layer may be a second electrode of the memory element.
摘要翻译：描述了使用阳极氧化形成的非易失性电阻式开关存储器。一种使用阳极氧化形成电阻式开关存储元件的方法包括形成含金属层，至少部分地阳极氧化含金属层以形成电阻式开关金属氧化物，以及在电阻式开关金属氧化物上形成第一电极。在一些实例中，含金属层的未渐变部分可以是存储元件的第二电极。

8. 发明申请

US20110204311A1 NON-VOLATILE RESISTIVE-SWITCHING MEMORIES FORMED USING ANODIZATION 有权
标题翻译：使用阳极化形成的非易失性电阻开关存储器
公开(公告)号：US20110204311A1
公开(公告)日：2011-08-25
申请号：US13098632
申请日：2011-05-02
申请人： Alexander Gorer , Prashant Phatak , Tony Chiang , Igor Ivanov
发明人： Alexander Gorer , Prashant Phatak , Tony Chiang , Igor Ivanov
IPC分类号： H01L45/00 , H01L21/8239
CPC分类号： H01L45/10 , H01L27/2463 , H01L45/1233 , H01L45/146 , H01L45/1633
摘要： Non-volatile resistive-switching memories formed using anodization are described. A method for forming a resistive-switching memory element using anodization includes forming a metal containing layer, anodizing the metal containing layer at least partially to form a resistive switching metal oxide, and forming a first electrode over the resistive switching metal oxide. In some examples, an unanodized portion of the metal containing layer may be a second electrode of the memory element.
摘要翻译：描述了使用阳极氧化形成的非易失性电阻式开关存储器。一种使用阳极氧化形成电阻式开关存储元件的方法包括形成含金属层，至少部分地阳极氧化含金属层以形成电阻式开关金属氧化物，以及在电阻式开关金属氧化物上形成第一电极。在一些实例中，含金属层的未渐变部分可以是存储元件的第二电极。

9. 发明授权

US07977152B2 Non-volatile resistive-switching memories formed using anodization 失效
标题翻译：使用阳极氧化形成的非易失性电阻式开关存储器
公开(公告)号：US07977152B2
公开(公告)日：2011-07-12
申请号：US12463319
申请日：2009-05-08
申请人： Alexander Gorer , Prashant Phatak , Tony Chiang , Igor Ivanov
发明人： Alexander Gorer , Prashant Phatak , Tony Chiang , Igor Ivanov
IPC分类号： H01L21/00
CPC分类号： H01L45/10 , H01L27/2463 , H01L45/1233 , H01L45/146 , H01L45/1633
摘要： Non-volatile resistive-switching memories formed using anodization are described. A method for forming a resistive-switching memory element using anodization includes forming a metal containing layer, anodizing the metal containing layer at least partially to form a resistive switching metal oxide, and forming a first electrode over the resistive switching metal oxide. In some examples, an unanodized portion of the metal containing layer may be a second electrode of the memory element.
摘要翻译：描述了使用阳极氧化形成的非易失性电阻式开关存储器。一种使用阳极氧化形成电阻式开关存储元件的方法包括形成含金属层，至少部分地阳极氧化含金属层以形成电阻式开关金属氧化物，以及在电阻式开关金属氧化物上形成第一电极。在一些实例中，含金属层的未渐变部分可以是存储元件的第二电极。

10. 发明授权

US07658790B1 Concentrated electroless solution for selective deposition of cobalt-based capping/barrier layers 失效
标题翻译：用于选择性沉积钴基封端/阻挡层的集中化学镀溶液
公开(公告)号：US07658790B1
公开(公告)日：2010-02-09
申请号：US11773316
申请日：2007-07-03
申请人： Alexander Gorer , Tony Chiang , Chi-I Lang
发明人： Alexander Gorer , Tony Chiang , Chi-I Lang
IPC分类号： C23C18/34
CPC分类号： C23C18/34 , C23C18/50
摘要： An electroless solution for deposition of a cobalt-based alloy on a substrate is provided. The electroless solution may be formed by mixing first and second solutions, with the first and second solutions being prepared from concentrated precursors. In one embodiment, the first solution contains a cobalt (Co) ion source and a complexing and deposition selectivity agent. In one embodiment, the cobalt concentration in the first solution is at least 90 millimoles per liter. The second solution contains a reducing agent. In one embodiment, the reducing agent is dimethylamineborane (DMAB) having a concentration of at least 10 grams per liter. In other embodiments, the first solution also contains a tungsten (W) ion source, and either the first or second solution also contains a phosphorous (P) ion source.
摘要翻译：提供了一种用于在基底上沉积钴基合金的无电溶液。化学溶液可以通过混合第一和第二溶液形成，第一和第二溶液由浓缩的前体制备。在一个实施方案中，第一溶液含有钴（Co）离子源和络合和沉积选择剂。在一个实施方案中，第一溶液中的钴浓度为至少90毫摩尔/升。第二种溶液含有还原剂。在一个实施方案中，还原剂是浓度为至少10克/升的二甲胺硼烷（DMAB）。在其它实施方案中，第一溶液还含有钨（W）离子源，并且第一或第二溶液也含有磷（P）离子源。

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