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1. 发明申请

US20060292845A1 Processing substrates using site-isolated processing 有权
标题翻译：使用现场隔离处理处理衬底
公开(公告)号：US20060292845A1
公开(公告)日：2006-12-28
申请号：US11418689
申请日：2006-05-05
申请人： Tony Chiang , David Lazovsky , Sandra Malhotra
发明人： Tony Chiang , David Lazovsky , Sandra Malhotra
IPC分类号： C23C16/00 , H01L21/44
CPC分类号： H01L22/26 , H01L21/32051 , H01L21/67028 , H01L21/6708 , H01L21/67207 , H01L21/67745 , H01L21/76834 , H01L21/76841 , H01L21/76849 , H01L21/76871
摘要： Substrate processing systems and methods are described for processing substrates having two or more regions. The processing includes one or more of molecular self-assembly and combinatorial processing. At least one of materials, processes, processing conditions, material application sequences, and process sequences is different for the processing in at least one region of the substrate relative to at least one other region of the substrate. Processing systems are described that include numerous processing modules. The modules include a site-isolated reactor (SIR) configured for one or more of molecular self-assembly and combinatorial processing of a substrate.
摘要翻译：描述了用于处理具有两个或更多个区域的基板的基板处理系统和方法。该处理包括分子自组装和组合处理中的一种或多种。材料，工艺，加工条件，材料应用顺序和工艺顺序中的至少一个不同于衬底相对于衬底的至少一个其它区域的至少一个区域中的处理。描述了包括许多处理模块的处理系统。模块包括配置用于衬底的分子自组装和组合处理中的一个或多个的位点隔离反应器（SIR）。

2. 发明申请

US20060060301A1 Substrate processing using molecular self-assembly 审中-公开
标题翻译：使用分子自组装的基板加工
公开(公告)号：US20060060301A1
公开(公告)日：2006-03-23
申请号：US11231047
申请日：2005-09-19
申请人： David Lazovsky , Tony Chiang , Sandra Malhotra
发明人： David Lazovsky , Tony Chiang , Sandra Malhotra
IPC分类号： H01L21/306 , C23F1/00
CPC分类号： B82Y30/00 , H01L21/76834 , H01L21/76849
摘要： A system for molecular self-assembly referred to herein as a “molecular self-assembly system (MSAS)” includes at least one interface configured to receive at least one substrate. The MSAS also includes at least one molecular self-assembly module coupled to the interface. The MSAS can also include one or more of pre-processing modules, other molecular self-assembly processing modules, and post-processing modules, and may include any number, combination, and/or type of other modules. Each module of the MSAS can contain at least one of a number of different processes as appropriate to a processing configuration of the MSAS. The MSAS also includes at least one handler coupled to the interface and configured to move the substrate between the interface and one or more of the modules.
摘要翻译：本文中称为“分子自组装系统（MSAS）”的分子自组装系统包括至少一个接口，其被配置为接收至少一个衬底。 MSAS还包括耦合到该界面的至少一个分子自组装模块。 MSAS还可以包括一个或多个预处理模块，其他分子自组装处理模块和后处理模块，并且可以包括其他模块的任何数量，组合和/或类型。 MSAS的每个模块可以包含适合于MSAS的处理配置的多个不同进程中的至少一个。 MSAS还包括至少一个处理器，其耦合到接口并且被配置为在接口和一个或多个模块之间移动衬底。

3. 发明申请

US20060264020A1 Formation of a masking layer on a dielectric region to facilitate formation of a capping layer on electrically conductive regions separated by the dielectric region 有权
标题翻译：在电介质区域上形成掩模层，以便在由电介质区域分隔的导电区域上形成覆盖层
公开(公告)号：US20060264020A1
公开(公告)日：2006-11-23
申请号：US11132841
申请日：2005-05-18
申请人： David Lazovsky , Sandra Malhotra , Thomas Boussie
发明人： David Lazovsky , Sandra Malhotra , Thomas Boussie
IPC分类号： H01L21/44
CPC分类号： H01L21/76829 , B82Y30/00 , H01L21/02183 , H01L21/3148 , H01L21/31633 , H01L21/31695 , H01L21/3185 , H01L21/76826 , H01L21/76849
摘要： A masking layer is formed on a dielectric region of an electronic device so that, during subsequent formation of a capping layer on electrically conductive regions of the electronic device that are separated by the dielectric region, the masking layer inhibits formation of capping layer material on or in the dielectric region. The capping layer can be formed selectively on the electrically conductive regions or non-selectively; in either case (particularly in the latter), capping layer material formed over the dielectric region can subsequently be removed, thus ensuring that capping layer material is formed only on the electrically conductive regions. Silane-based materials, such as silane-based SAMs, can be used to form the masking layer. The capping layer can be formed of an electrically conductive material (e.g., a cobalt alloy, a nickel alloy, tungsten, tantalum, tantalum nitride), a semiconductor material, or an electrically insulative material, and can be formed using any appropriate process, including conventional deposition processes such as electroless deposition, chemical vapor deposition, physical vapor deposition or atomic layer deposition.
摘要翻译：在电子器件的电介质区域上形成掩模层，使得在随后在由电介质区域分离的电子器件的导电区域上形成覆盖层时，掩模层阻止在其上形成覆盖层材料在电介质区域。可以选择性地在导电区域或非选择性地形成覆盖层; 在任一情况下（特别是在后者中），可以随后去除在电介质区域上形成的覆盖层材料，从而确保覆盖层材料仅在导电区域上形成。可以使用诸如硅烷基SAM之类的硅烷基材料来形成掩模层。覆盖层可以由导电材料（例如，钴合金，镍合金，钨，钽，氮化钽），半导体材料或电绝缘材料形成，并且可以使用任何适当的工艺形成，包括常规沉积工艺如无电沉积，化学气相沉积，物理气相沉积或原子层沉积。

4. 发明申请

US20060261434A1 Formation of a masking layer on a dielectric region to facilitate formation of a capping layer on electrically conductive regions separated by the dielectric region 有权
公开(公告)号：US20060261434A1
公开(公告)日：2006-11-23
申请号：US11132817
申请日：2005-05-18
申请人： David Lazovsky , Sandra Malhotra , Thomas Boussie
发明人： David Lazovsky , Sandra Malhotra , Thomas Boussie
IPC分类号： H01L21/76 , H01L29/00
CPC分类号： H01L21/7685 , B82Y30/00 , H01L21/02118 , H01L21/02167 , H01L21/0217 , H01L21/02203 , H01L21/288 , H01L21/31 , H01L21/76834
摘要： A masking layer is formed on a dielectric region of an electronic device so that, during subsequent formation of a capping layer on electrically conductive regions of the electronic device that are separated by the dielectric region, the masking layer inhibits formation of capping layer material on or in the dielectric region. The capping layer can be formed selectively on the electrically conductive regions or non-selectively; in either case (particularly in the latter), capping layer material formed over the dielectric region can subsequently be removed, thus ensuring that capping layer material is formed only on the electrically conductive regions. Silane-based materials, such as silane-based SAMs, can be used to form the masking layer. The capping layer can be formed of an electrically conductive material (e.g., a cobalt alloy, a nickel alloy, tungsten, tantalum, tantalum nitride), a semiconductor material, or an electrically insulative material, and can be formed using any appropriate process, including conventional deposition processes such as electroless deposition, chemical vapor deposition, physical vapor deposition or atomic layer deposition.

5. 发明授权

US08900422B2 Yttrium and titanium high-K dielectric film 有权
标题翻译：钇和钛高K电介质膜
公开(公告)号：US08900422B2
公开(公告)日：2014-12-02
申请号：US12921776
申请日：2009-04-17
申请人： Imran Hashim , Indranil De , Tony Chiang , Edward Haywood , Hanhong Chen , Nobi Fuchigami , Pragati Kumar , Sandra Malhotra , Sunil Shanker
发明人： Imran Hashim , Indranil De , Tony Chiang , Edward Haywood , Hanhong Chen , Nobi Fuchigami , Pragati Kumar , Sandra Malhotra , Sunil Shanker
IPC分类号： B05D5/12 , C23C14/34 , H01L49/02 , C23C16/40 , C23C16/455 , H01L21/314 , H01L21/316 , H01L27/108 , H01L21/02
CPC分类号： H01L28/65 , C23C16/405 , C23C16/45529 , C23C16/45531 , H01L21/02697 , H01L21/3141 , H01L21/31604 , H01L27/10852 , H01L28/40
摘要： This disclosure provides (a) methods of making an oxide layer (e.g., a dielectric layer) based on yttrium and titanium, to have a high dielectric constant and low leakage characteristic and (b) related devices and structures. An oxide layer having both yttrium and titanium may be fabricated either as an amorphous oxide or as an alternating series of monolayers. In several embodiments, the oxide is characterized by a yttrium contribution to total metal that is specifically controlled. The oxide layer can be produced as the result of a reactive process, if desired, via either a PVD process or, alternatively, via an atomic layer deposition process that employs specific precursor materials to allow for a common process temperature window for both titanium and yttrium reactions.
摘要翻译：本公开内容提供（a）制造基于钇和钛的氧化物层（例如，电介质层）的方法，以具有高介电常数和低泄漏特性，以及（b）相关的器件和结构。具有钇和钛的氧化物层可以制成无定形氧化物或交替的单层系列。在几个实施方案中，氧化物的特征在于对特定控制的总金属的钇贡献。如果需要，可以通过PVD工艺或者通过使用特定的前体材料以允许钛和钇的共同工艺温度窗口的原子层沉积工艺，作为反应过程的结果来生产氧化物层反应。

6. 发明授权

US08143619B2 Methods of combinatorial processing for screening multiple samples on a semiconductor substrate 有权
标题翻译：用于在半导体衬底上筛选多个样品的组合处理方法
公开(公告)号：US08143619B2
公开(公告)日：2012-03-27
申请号：US12905945
申请日：2010-10-15
申请人： Gaurav Verma , Kurt Weiner , Prashant Phatak , Imran Hashim , Sandra Malhotra , Tony Chiang
发明人： Gaurav Verma , Kurt Weiner , Prashant Phatak , Imran Hashim , Sandra Malhotra , Tony Chiang
IPC分类号： H01L29/00
CPC分类号： G01R31/2831 , G01R31/2834 , H01L22/34
摘要： In embodiments of the current invention, methods of combinatorial processing and a test chip for use in these methods are described. These methods and test chips enable the efficient development of materials, processes, and process sequence integration schemes for semiconductor manufacturing processes. In general, the methods simplify the processing sequence of forming devices or partially formed devices on a test chip such that the devices can be tested immediately after formation. The immediate testing allows for the high throughput testing of varied materials, processes, or process sequences on the test chip. The test chip has multiple site isolated regions where each of the regions is varied from one another and the test chip is designed to enable high throughput testing of the different regions.
摘要翻译：在本发明的实施例中，描述了用于这些方法的组合处理方法和测试芯片。这些方法和测试芯片能够有效地开发用于半导体制造工艺的材料，工艺和工艺顺序集成方案。通常，这些方法简化了在测试芯片上形成器件或部分形成的器件的处理顺序，使得器件可以在形成后立即进行测试。即时测试允许测试芯片上各种材料，工艺或工艺顺序的高通量测试。测试芯片具有多个位置隔离区域，其中每个区域彼此变化，并且测试芯片被设计为能够实现不同区域的高通量测试。

7. 发明申请

US20110014359A1 Yttrium and Titanium High-K Dielectric Film 有权
标题翻译：钇和钛高K电介质膜
公开(公告)号：US20110014359A1
公开(公告)日：2011-01-20
申请号：US12921776
申请日：2009-04-17
申请人： Imran Hashim , Indranil De , Tony Chiang , Edward Haywood , Hanhong Chen , Nobi Fuchigami , Pragati Kumar , Sandra Malhotra , Sunil Shanker
发明人： Imran Hashim , Indranil De , Tony Chiang , Edward Haywood , Hanhong Chen , Nobi Fuchigami , Pragati Kumar , Sandra Malhotra , Sunil Shanker
IPC分类号： B05D5/12
CPC分类号： H01L28/65 , C23C16/405 , C23C16/45529 , C23C16/45531 , H01L21/02697 , H01L21/3141 , H01L21/31604 , H01L27/10852 , H01L28/40
摘要： This disclosure provides (a) methods of making an oxide layer (e.g., a dielectric layer) based on yttrium and titanium to have a high dielectric constant and low leakage characteristic and (b) related devices and structures. An oxide layer having both yttrium and titanium may be fabricated either as an amorphous oxide or as an alternating series of monolayers. In several embodiments, the oxide is characterized by a yttrium contribution to total metal that is specifically controlled. The oxide layer can be produced as the result of a reactive process, if desired, via either a PVD process or, alternatively, via an atomic layer deposition process that employs specific precursor materials to allow for a common process temperature window for both titanium and yttrium reactions.
摘要翻译：本公开内容提供（a）制造基于钇和钛的氧化物层（例如，电介质层）具有高介电常数和低泄漏特性的方法，以及（b）相关的器件和结构。具有钇和钛的氧化物层可以制成无定形氧化物或交替的单层系列。在几个实施方案中，氧化物的特征在于对特定控制的总金属的钇贡献。如果需要，可以通过PVD工艺或者通过使用特定的前体材料以允许钛和钇的共同工艺温度窗口的原子层沉积工艺，作为反应过程的结果来生产氧化物层反应。

8. 发明授权

US07824935B2 Methods of combinatorial processing for screening multiple samples on a semiconductor substrate 有权
标题翻译：用于在半导体衬底上筛选多个样品的组合处理方法
公开(公告)号：US07824935B2
公开(公告)日：2010-11-02
申请号：US12167118
申请日：2008-07-02
申请人： Gaurav Verma , Kurt Weiner , Prashant Phatak , Imran Hashim , Sandra Malhotra , Tony Chiang
发明人： Gaurav Verma , Kurt Weiner , Prashant Phatak , Imran Hashim , Sandra Malhotra , Tony Chiang
IPC分类号： H01L21/00
CPC分类号： G01R31/2831 , G01R31/2834 , H01L22/34
摘要： In embodiments of the current invention, methods of combinatorial processing and a test chip for use in these methods are described. These methods and test chips enable the efficient development of materials, processes, and process sequence integration schemes for semiconductor manufacturing processes. In general, the methods simplify the processing sequence of forming devices or partially formed devices on a test chip such that the devices can be tested immediately after formation. The immediate testing allows for the high throughput testing of varied materials, processes, or process sequences on the test chip. The test chip has multiple site isolated regions where each of the regions is varied from one another and the test chip is designed to enable high throughput testing of the different regions.
摘要翻译：在本发明的实施例中，描述了用于这些方法的组合处理方法和测试芯片。这些方法和测试芯片能够有效地开发用于半导体制造工艺的材料，工艺和工艺顺序集成方案。通常，这些方法简化了在测试芯片上形成器件或部分形成的器件的处理顺序，使得器件可以在形成后立即进行测试。即时测试允许测试芯片上各种材料，工艺或工艺顺序的高通量测试。测试芯片具有多个位置隔离区域，其中每个区域彼此变化，并且测试芯片被设计为能够实现不同区域的高通量测试。

9. 发明授权

US08278735B2 Yttrium and titanium high-k dielectric films 有权
标题翻译：钇和钛高k电介质膜
公开(公告)号：US08278735B2
公开(公告)日：2012-10-02
申请号：US12901239
申请日：2010-10-08
申请人： Imran Hashim , Indranil De , Tony Chiang , Edward Haywood , Hanhong Chen , Nobi Fuchigami , Pragati Kumar , Sandra Malhotra , Sunil Shanker
发明人： Imran Hashim , Indranil De , Tony Chiang , Edward Haywood , Hanhong Chen , Nobi Fuchigami , Pragati Kumar , Sandra Malhotra , Sunil Shanker
IPC分类号： H01L21/02
CPC分类号： H01L28/40 , C23C14/083 , C23C14/3464 , C23C16/405 , C23C16/45531 , H01L21/02186 , H01L21/02192 , H01L21/02194 , H01L21/02266 , H01L21/0228
摘要： This disclosure provides (a) methods of making an oxide layer (e.g., a dielectric layer) based on yttrium and titanium, to have a high dielectric constant and low leakage characteristic and (b) related devices and structures. An oxide layer having both yttrium and titanium may be fabricated either as an amorphous oxide or as an alternating series of monolayers. In several embodiments, the oxide is characterized by a yttrium contribution to total metal that is specifically controlled. The oxide layer can be produced as the result of a reactive process, if desired, via either a PVD process or, alternatively, via an atomic layer deposition process that employs specific precursor materials to allow for a common process temperature window for both titanium and yttrium reactions.
摘要翻译：本公开内容提供（a）制造基于钇和钛的氧化物层（例如，电介质层）的方法，以具有高介电常数和低泄漏特性，以及（b）相关的器件和结构。具有钇和钛的氧化物层可以制成无定形氧化物或交替的单层系列。在几个实施方案中，氧化物的特征在于对特定控制的总金属的钇贡献。如果需要，可以通过PVD工艺或者通过使用特定的前体材料以允许钛和钇的共同工艺温度窗口的原子层沉积工艺，作为反应过程的结果来生产氧化物层反应。

10. 发明申请

US20110248264A1 Methods of Combinatorial Processing for Screening Multiple Samples on a Semiconductor Substrate 有权
标题翻译：在半导体基板上筛选多个样品的组合处理方法
公开(公告)号：US20110248264A1
公开(公告)日：2011-10-13
申请号：US12905945
申请日：2010-10-15
申请人： Gaurav Verma , Kurt Weiner , Prashant Phatak , Imran Hashim , Sandra Malhotra , Tony Chiang
发明人： Gaurav Verma , Kurt Weiner , Prashant Phatak , Imran Hashim , Sandra Malhotra , Tony Chiang
IPC分类号： H01L29/66
CPC分类号： G01R31/2831 , G01R31/2834 , H01L22/34
摘要： In embodiments of the current invention, methods of combinatorial processing and a test chip for use in these methods are described. These methods and test chips enable the efficient development of materials, processes, and process sequence integration schemes for semiconductor manufacturing processes. In general, the methods simplify the processing sequence of forming devices or partially formed devices on a test chip such that the devices can be tested immediately after formation. The immediate testing allows for the high throughput testing of varied materials, processes, or process sequences on the test chip. The test chip has multiple site isolated regions where each of the regions is varied from one another and the test chip is designed to enable high throughput testing of the different regions.
摘要翻译：在本发明的实施例中，描述了用于这些方法的组合处理方法和测试芯片。这些方法和测试芯片能够有效地开发用于半导体制造工艺的材料，工艺和工艺顺序集成方案。通常，这些方法简化了在测试芯片上形成器件或部分形成的器件的处理顺序，使得器件可以在形成后立即进行测试。即时测试允许测试芯片上各种材料，工艺或工艺顺序的高通量测试。测试芯片具有多个位置隔离区域，其中每个区域彼此变化，并且测试芯片被设计为能够实现不同区域的高通量测试。

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