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1. 发明授权

US09165917B2 In-line stacking of transistors for soft error rate hardening 有权
标题翻译：用于软错误率硬化的晶体管的在线堆叠
公开(公告)号：US09165917B2
公开(公告)日：2015-10-20
申请号：US12473409
申请日：2009-05-28
申请人： Ethan H. Cannon , David F. Heidel , K. Paul Muller , Alicia Wang
发明人： Ethan H. Cannon , David F. Heidel , K. Paul Muller , Alicia Wang
IPC分类号： H01L27/11 , H01L27/02 , H01L21/8238 , H01L27/092
CPC分类号： H01L27/0207 , H01L21/823871 , H01L27/092
摘要： Each one of a pair of CMOS transistors is formed in its own island and a gate terminal for each transistor is formed by a single, in-line conductor connecting both gate terminals together. This type of “in-line” connection achieves nearly a five-time improvement in the reduction of the ability of ionizing radiation particles to strike both transistors at the same time as compared to prior art “side-by-side” transistor stacking through use of a relatively smaller solid angle spanning the two transistors. This results in “hardening” of the transistors and improving their resistance to single event upsets and, thus, improving the soft error rate (SER) of the transistors.
摘要翻译：一对CMOS晶体管中的每一个形成在其自身的岛中，并且每个晶体管的栅极端子由连接两个栅极端子的单个直列导体形成。与现有技术的“并排”晶体管堆叠通过使用相比，这种“在线”连接实现了与电离辐射颗粒同时撞击两个晶体管的能力的降低近乎五次的改进具有跨越两个晶体管的相对较小的立体角。这导致了晶体管的“硬化”，并提高了它们对单一事件的影响，从而提高了晶体管的软错误率（SER）。

2. 发明申请

US20100301446A1 IN-LINE STACKING OF TRANSISTORS FOR SOFT ERROR RATE HARDENING 有权
标题翻译：用于软错误速率硬化的晶体管的在线堆叠
公开(公告)号：US20100301446A1
公开(公告)日：2010-12-02
申请号：US12473409
申请日：2009-05-28
申请人： Ethan H. Cannon , David F. Heidel , K. Paul Muller , Alicia Wang
发明人： Ethan H. Cannon , David F. Heidel , K. Paul Muller , Alicia Wang
IPC分类号： H01L27/12 , H01L21/28
CPC分类号： H01L27/0207 , H01L21/823871 , H01L27/092
摘要： Each one of a pair of CMOS transistors is formed in its own island and a gate terminal for each transistor is formed by a single, in-line conductor connecting both gate terminals together. This type of “in-line” connection achieves nearly a five-time improvement in the reduction of the ability of ionizing radiation particles to strike both transistors at the same time as compared to prior art “side-by-side” transistor stacking through use of a relatively smaller solid angle spanning the two transistors. This results in “hardening” of the transistors and improving their resistance to single event upsets and, thus, improving the soft error rate (SER) of the transistors.
摘要翻译：一对CMOS晶体管中的每一个形成在其自身的岛中，并且每个晶体管的栅极端子由连接两个栅极端子的单个直列导体形成。与现有技术的“并排”晶体管堆叠通过使用相比，这种“在线”连接实现了与电离辐射颗粒同时撞击两个晶体管的能力的降低近乎五次的改进具有跨越两个晶体管的相对较小的立体角。这导致了晶体管的“硬化”，并提高了它们对单一事件的影响，从而提高了晶体管的软错误率（SER）。

3. 发明授权

US07791330B2 On-chip jitter measurement circuit 失效
标题翻译：片上抖动测量电路
公开(公告)号：US07791330B2
公开(公告)日：2010-09-07
申请号：US12125730
申请日：2008-05-22
申请人： David F. Heidel , Keith A. Jenkins
发明人： David F. Heidel , Keith A. Jenkins
IPC分类号： G01R13/02
CPC分类号： H04L1/205 , G01R29/26 , G01R31/3016 , G01R31/31709 , G01R31/31725
摘要： An on-chip jitter measurement circuit and corresponding method are provided for receiving a reference clock and a signal of interest, the circuit including a latch for latching and comparing the arrival time of the signal of interest to the reference clock, a clock counter in signal communication with the latch for counting the number of reference clock cycles received and latched, a delay chain in signal communication with the reference clock for varying the arrival time of the reference clock, the delay chain having a first stage, middle stages, and a last stage, and a voltage controller in signal communication with at least one of the middle stages of the delay chain for controlling the delay of the arrival time of the reference clock, wherein the voltage controller controls the first and last stages of the delay chain to retain a full voltage swing independent of the delay.
摘要翻译：提供一种用于接收参考时钟和感兴趣信号的片上抖动测量电路和相应方法，该电路包括用于锁存和比较感兴趣信号到参考时钟的到达时间的锁存器，信号中的时钟计数器与锁存器通信，用于对接收和锁存的参考时钟周期的数量进行计数;与参考时钟的信号通信的延迟链，用于改变参考时钟的到达时间;延迟链具有第一级，中间级和最后一位以及与延迟链的至少一个中间级信号通信的电压控制器，用于控制参考时钟的到达时间的延迟，其中电压控制器控制延迟链的第一和最后阶段以保持全电压摆幅独立于延时。

4. 发明授权

US07439724B2 On-chip jitter measurement circuit 失效
标题翻译：片上抖动测量电路
公开(公告)号：US07439724B2
公开(公告)日：2008-10-21
申请号：US10638825
申请日：2003-08-11
申请人： David F. Heidel , Keith A. Jenkins
发明人： David F. Heidel , Keith A. Jenkins
IPC分类号： G01R23/00 , H04L7/00 , H03L7/06
CPC分类号： H04L1/205 , G01R29/26 , G01R31/3016 , G01R31/31709 , G01R31/31725
摘要： An on-chip jitter measurement circuit and corresponding method are provided for receiving a reference clock and a signal of interest, including a latch for comparing the arrival time of the signal of interest to the reference clock, a delay chain in signal communication with the reference clock for varying the arrival time of the reference clock, the delay chain having a first stage, a middle stage, and a last stage, a voltage controller in signal communication with the middle stage of the delay chain for controlling the delay of the arrival time of the reference clock while permitting the first and last stages of the delay chain to retain a full voltage swing independent of the delay.
摘要翻译：提供片上抖动测量电路和相应的方法，用于接收参考时钟和感兴趣的信号，包括用于比较感兴趣信号的到达时间与参考时钟的锁存器，与参考时钟信号通信的延迟链用于改变参考时钟的到达时间的时钟，具有第一级，中级和最后级的延迟链，与延迟链的中间级信号通信的电压控制器，用于控制到达时间的延迟的参考时钟，同时允许延迟链的第一级和最后级保持独立于延迟的全电压摆幅。

5. 发明授权

US07084660B1 System and method for accelerated detection of transient particle induced soft error rates in integrated circuits 失效
标题翻译：用于加速检测集成电路中瞬态粒子诱导的软错误率的系统和方法
公开(公告)号：US07084660B1
公开(公告)日：2006-08-01
申请号：US11098104
申请日：2005-04-04
申请人： Jerry D. Ackaret , Richard B. Bhend , David F. Heidel , Naoko Pia Sanda , Scott B. Swaney , Jane Jones, legal representative
发明人： Theodore H. Zabel, deceased
IPC分类号： G01R31/27 , H01L23/58 , H01L21/00
CPC分类号： G01R31/2881 , G01R31/31816 , H01L21/563 , H01L23/556 , H01L24/31 , H01L24/81 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/81052 , H01L2224/8121 , H01L2224/81815 , H01L2224/83102 , H01L2224/83859 , H01L2224/83951 , H01L2224/92125 , H01L2924/00011 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01082 , H01L2924/01084 , H01L2924/01092 , H01L2924/01094 , H01L2924/14 , H01L2924/3025 , H01L2924/00 , H01L2224/0401
摘要： A method and system are provided for accelerated detection of soft error rates (SER) in integrated circuits (IC's) due to transient particle emission. An integrated circuit is packaged for accelerated transient particle emission by doping the underfill thereof with a transient-particle-emitting material having a predetermined emission rate. The emission rate is substantially constant over a predetermined period of time for testing. Accelerated transient-particle-emission testing is performed on the integrated circuit. Single-event upsets due to soft errors are detected, and a quantitative measurement of SER is determined.
摘要翻译：提供了一种方法和系统，用于加速检测由于瞬态粒子发射引起的集成电路（IC）中的软错误率（SER）。通过用具有预定排放速率的瞬态粒子发射材料掺杂其底部填充物来封装用于加速瞬态粒子发射的集成电路。发射速率在测试的预定时间段内基本上是恒定的。在集成电路上进行加速瞬态粒子发射测试。检测到由于软错误引起的单事件故障，并确定SER的定量测量。

6. 发明申请

US20110026806A1 Detecting Chip Alterations with Light Emission 有权
标题翻译：用光发射检测芯片变化
公开(公告)号：US20110026806A1
公开(公告)日：2011-02-03
申请号：US12512168
申请日：2009-07-30
申请人： Kerry Bernstein , James Culp , David F. Heidel , Dirk Pfeiffer , Anthony D. Polson , Peilin Song , Franco Stellari , Robert L. Wisnieff
发明人： Kerry Bernstein , James Culp , David F. Heidel , Dirk Pfeiffer , Anthony D. Polson , Peilin Song , Franco Stellari , Robert L. Wisnieff
IPC分类号： G03F9/00 , G06F19/00
CPC分类号： G01R31/311
摘要： An emission map of a circuit to be tested for alterations is obtained by measuring the physical circuit to be tested. An emission map of a reference circuit is obtained by measuring a physical reference circuit or by simulating the emissions expected from the reference circuit. The emission map of the circuit to be tested is compared with the emission map of the reference circuit, to determine presence of alterations in the circuit to be tested, as compared to the reference circuit.
摘要翻译：通过测量要测试的物理电路来获得待测试电路的发射图。通过测量物理参考电路或通过模拟从参考电路预期的发射来获得参考电路的发射图。与参考电路相比，要测试的电路的发射图与参考电路的发射图进行比较，以确定待测电路中的变化的存在。

7. 发明申请

US20080284477A1 ON-CHIP JITTER MEASUREMENT CIRCUIT 失效
标题翻译：片上抖动测量电路
公开(公告)号：US20080284477A1
公开(公告)日：2008-11-20
申请号：US12125730
申请日：2008-05-22
申请人： David F. Heidel , Keith A. Jenkins
发明人： David F. Heidel , Keith A. Jenkins
IPC分类号： H03L7/24
CPC分类号： H04L1/205 , G01R29/26 , G01R31/3016 , G01R31/31709 , G01R31/31725
摘要： An on-chip jitter measurement circuit and corresponding method are provided for receiving a reference clock and a signal of interest, including a latch for comparing the arrival time of the signal of interest to the reference clock, a delay chain in signal communication with the reference clock for varying the arrival time of the reference clock, the delay chain having a first stage, a middle stage, and a last stage, a voltage controller in signal communication with the middle stage of the delay chain for controlling the delay of the arrival time of the reference clock while permitting the first and last stages of the delay chain to retain a full voltage swing independent of the delay.
摘要翻译：提供片上抖动测量电路和相应的方法，用于接收参考时钟和感兴趣的信号，包括用于比较感兴趣信号的到达时间与参考时钟的锁存器，与参考时钟信号通信的延迟链用于改变参考时钟的到达时间的时钟，具有第一级，中级和最后级的延迟链，与延迟链的中间级信号通信的电压控制器，用于控制到达时间的延迟的参考时钟，同时允许延迟链的第一级和最后级保持独立于延迟的全电压摆幅。

8. 发明授权

US08362600B2 Method and structure to reduce soft error rate susceptibility in semiconductor structures 有权
标题翻译：减少半导体结构中软错误率敏感性的方法和结构
公开(公告)号：US08362600B2
公开(公告)日：2013-01-29
申请号：US12689268
申请日：2010-01-19
申请人： Cyril Cabral, Jr. , Michael S. Gordon , David F. Heidel , Conal Eugene Murray , Kenneth Parker Rodbell , Henry Hong Ki Tang
发明人： Cyril Cabral, Jr. , Michael S. Gordon , David F. Heidel , Conal Eugene Murray , Kenneth Parker Rodbell , Henry Hong Ki Tang
IPC分类号： H01L23/556 , H01L21/60
CPC分类号： H01L23/556 , H01L24/13 , H01L2924/01019 , H01L2924/01025 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01084 , H01L2924/1305 , H01L2924/14 , H01L2924/3025 , H01L2924/00
摘要： A method is disclosed that includes providing a semiconductor substrate having one or more device levels including a number of devices, and forming a number of wiring levels on a top surface of the one or more device levels, wherein one or more of the number of wiring levels includes one or more alpha particle blocking shields situated between at least one of the number of devices and a predetermined first location where a terminal pad will be formed in one of the wiring levels, the one or more alpha particle blocking shields placed at a second location, having one or more widths, and occupying a predetermined number of the wiring levels, sufficient to prevent a predetermined percentage of alpha particles of a selected energy or less expected to be emitted from an alpha particle emitting metallization to be formed adjacent and connected to the terminal pad from reaching the one device.
摘要翻译：公开了一种方法，其包括提供具有包括多个器件的一个或多个器件电平的半导体衬底，以及在所述一个或多个器件级的顶表面上形成多个布线电平，其中所述多个布线中的一个或多个水平包括一个或多个α粒子阻挡屏蔽，位于多个器件中的至少一个与预定的第一位置之间，其中端子焊盘将形成在一个布线层中，一个或多个α粒子阻挡屏蔽放置在第二个位置，具有一个或多个宽度并且占据预定数量的布线水平，足以防止预定百分比的α粒子被选择的能量或预期从发射的α粒子发射的金属化物发射出来邻近并连接到终端垫到达一个设备。

9. 发明授权

US06230290B1 Method of self programmed built in self test 失效
标题翻译：自我编程内置自检方法
公开(公告)号：US06230290B1
公开(公告)日：2001-05-08
申请号：US08887462
申请日：1997-07-02
申请人： David F. Heidel , Wei Hwang , Toshiaki Kirihata
发明人： David F. Heidel , Wei Hwang , Toshiaki Kirihata
IPC分类号： G11C2900
CPC分类号： G11C29/16
摘要： A method of self-programmable Built In Self Test (BIST) for a memory (e.g., Dynamic Random Access Memory (DRAM)). The DRAM, which may be a DRAM chip, includes a DRAM core, a Microcode or Initial Command ROM, a BIST Engine, a Command Register and a Self-Program Circuit. During self test, the BIST engine may test the DRAM normally until an error is encountered. When an error is encountered, the Self-Program Circuit restarts the self test procedure at less stringent conditions. Optionally, when the DRAM tests error-free, the Self-Program Circuit may restart testing at more stringent conditions to determine DRAM functionality limits.
摘要翻译：一种用于存储器（例如，动态随机存取存储器（DRAM））的自编程内置自检（BIST）的方法。可以是DRAM芯片的DRAM包括DRAM内核，微代码或初始命令ROM，BIST引擎，命令寄存器和自编程电路。在自检期间，BIST引擎可以正常测试DRAM，直到遇到错误。当遇到错误时，自编程电路在较不严格的条件下重新启动自检程序。可选地，当DRAM测试无错误时，自编程电路可以在更严格的条件下重新开始测试以确定DRAM功能限制。

10. 发明授权

US09075106B2 Detecting chip alterations with light emission 有权
标题翻译：用光发射检测芯片变化
公开(公告)号：US09075106B2
公开(公告)日：2015-07-07
申请号：US12512168
申请日：2009-07-30
申请人： Kerry Bernstein , James Culp , David F. Heidel , Dirk Pfeiffer , Anthony D. Polson , Peilin Song , Franco Stellari , Robert L. Wisnieff
发明人： Kerry Bernstein , James Culp , David F. Heidel , Dirk Pfeiffer , Anthony D. Polson , Peilin Song , Franco Stellari , Robert L. Wisnieff
IPC分类号： G06K9/00 , G01R31/311 , G01R31/00
CPC分类号： G01R31/311
摘要： An emission map of a circuit to be tested for alterations is obtained by measuring the physical circuit to be tested. An emission map of a reference circuit is obtained by measuring a physical reference circuit or by simulating the emissions expected from the reference circuit. The emission map of the circuit to be tested is compared with the emission map of the reference circuit, to determine presence of alterations in the circuit to be tested, as compared to the reference circuit.
摘要翻译：通过测量要测试的物理电路来获得待测试电路的发射图。通过测量物理参考电路或通过模拟从参考电路预期的发射来获得参考电路的发射图。与参考电路相比，要测试的电路的发射图与参考电路的发射图进行比较，以确定待测电路中的变化的存在。

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