专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20150303871A1 HIGH FREQUENCY OSCILLATOR CIRCUIT 有权
标题翻译：高频振荡器电路
公开(公告)号：US20150303871A1
公开(公告)日：2015-10-22
申请号：US13569815
申请日：2012-08-08
申请人： Keith A. Jenkins , Yu-ming Lin
发明人： Keith A. Jenkins , Yu-ming Lin
IPC分类号： H03B5/12 , H01L29/16 , H01L29/786
CPC分类号： H03B5/1228 , H01L29/1606 , H01L29/78684 , H03B5/1203 , H03B7/06 , H03B2200/0084
摘要： An oscillator circuit includes a field effect transistor and a resonant circuit having a first terminal connected to the field effect transistor. The resonant circuit includes an inductance and a capacitance and has a second terminal for connecting to a radiator. The field effect transistor includes a gate electrode coupled to a source of gate voltage, a source electrode, a drain electrode and a graphene channel disposed between the source electrode and the drain electrode and electrically connected thereto. The graphene channel is disposed relative to the gate electrode for being biased by the gate electrode into a negative differential resistance region of operation. The oscillator circuit is capable of generating a continuous wave THz frequency signal, and is further capable of being enabled and disabled by the bias applied to the gate electrode.
摘要翻译：振荡器电路包括场效应晶体管和具有连接到场效应晶体管的第一端子的谐振电路。谐振电路包括电感和电容，并且具有用于连接到散热器的第二端子。场效应晶体管包括耦合到栅极电压源的栅电极，源电极，漏电极和设置在源电极和漏电极之间并与其电连接的石墨烯通道。石墨烯通道相对于栅电极设置，以便被栅电极偏压成负的差分电阻区域。振荡器电路能够产生连续波THz频率信号，并且还能够通过施加到栅电极的偏置使能和禁止。

2. 发明授权

US08829922B2 On-chip measurement of AC variability in individual transistor devices 有权
标题翻译：单个晶体管器件的交流变率的片上测量
公开(公告)号：US08829922B2
公开(公告)日：2014-09-09
申请号：US13029214
申请日：2011-02-17
申请人： Karthik Balakrishnan , Keith A. Jenkins
发明人： Karthik Balakrishnan , Keith A. Jenkins
IPC分类号： G01R27/28 , G01R31/28 , G01R31/26
CPC分类号： G01R31/2621 , G01R31/2882
摘要： An apparatus for determining alternating current (AC) delay variation of a transistor device under test includes a ring oscillator, the ring oscillator having the transistor device under test configured within a feedback path of the ring oscillator; and circuitry configured to measure a difference between a first signal delay path and a second signal delay path, the first signal delay path being between a gate terminal and a drain terminal of the transistor device under test, and the second signal delay path being between a source terminal and the drain terminal of the transistor device under test.
摘要翻译：一种用于确定被测晶体管器件的交流（AC）延迟变化的装置包括环形振荡器，环形振荡器具有被配置在环形振荡器的反馈路径内的被测晶体管器件; 以及被配置为测量第一信号延迟路径和第二信号延迟路径之间的差的电路，所述第一信号延迟路径位于被测晶体管器件的栅极端子和漏极端子之间，并且所述第二信号延迟路径位于源极端子和被测晶体管器件的漏极端子。

3. 发明申请

US20110235390A1 HIGH DENSITY MEMORY DEVICE 有权
标题翻译：高密度存储器件
公开(公告)号：US20110235390A1
公开(公告)日：2011-09-29
申请号：US12729856
申请日：2010-03-23
申请人： Tymon Barwicz , Keith A. Jenkins , Supratik Guha
发明人： Tymon Barwicz , Keith A. Jenkins , Supratik Guha
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C11/404 , G11C13/0007 , H01L28/40 , H01L49/003
摘要： A memory device and a method of forming the same are provided. The memory device includes a substrate; a set of electrodes disposed on the substrate; a dielectric layer formed between the set of electrodes; and a transition metal oxide layer formed between the set of electrodes, the transition metal oxide layer configured to undergo a metal-insulator transition (MIT) to perform a read or write operation.
摘要翻译：提供了一种存储器件及其形成方法。存储器件包括衬底; 设置在基板上的一组电极; 形成在该组电极之间的电介质层; 以及形成在所述电极组之间的过渡金属氧化物层，所述过渡金属氧化物层被配置为经历金属 - 绝缘体转变（MIT）以执行读取或写入操作。

4. 发明授权

US07791330B2 On-chip jitter measurement circuit 失效
标题翻译：片上抖动测量电路
公开(公告)号：US07791330B2
公开(公告)日：2010-09-07
申请号：US12125730
申请日：2008-05-22
申请人： David F. Heidel , Keith A. Jenkins
发明人： David F. Heidel , Keith A. Jenkins
IPC分类号： G01R13/02
CPC分类号： H04L1/205 , G01R29/26 , G01R31/3016 , G01R31/31709 , G01R31/31725
摘要： An on-chip jitter measurement circuit and corresponding method are provided for receiving a reference clock and a signal of interest, the circuit including a latch for latching and comparing the arrival time of the signal of interest to the reference clock, a clock counter in signal communication with the latch for counting the number of reference clock cycles received and latched, a delay chain in signal communication with the reference clock for varying the arrival time of the reference clock, the delay chain having a first stage, middle stages, and a last stage, and a voltage controller in signal communication with at least one of the middle stages of the delay chain for controlling the delay of the arrival time of the reference clock, wherein the voltage controller controls the first and last stages of the delay chain to retain a full voltage swing independent of the delay.
摘要翻译：提供一种用于接收参考时钟和感兴趣信号的片上抖动测量电路和相应方法，该电路包括用于锁存和比较感兴趣信号到参考时钟的到达时间的锁存器，信号中的时钟计数器与锁存器通信，用于对接收和锁存的参考时钟周期的数量进行计数;与参考时钟的信号通信的延迟链，用于改变参考时钟的到达时间;延迟链具有第一级，中间级和最后一位以及与延迟链的至少一个中间级信号通信的电压控制器，用于控制参考时钟的到达时间的延迟，其中电压控制器控制延迟链的第一和最后阶段以保持全电压摆幅独立于延时。

5. 发明授权

US07764080B2 Methods of operating an electronic circuit for measurement of transistor variability and the like 失效
标题翻译：操作用于测量晶体管可变性等的电子电路的方法
公开(公告)号：US07764080B2
公开(公告)日：2010-07-27
申请号：US12200334
申请日：2008-08-28
申请人： Keith A. Jenkins , Jae-Joon Kim , Rahul M. Rao
发明人： Keith A. Jenkins , Jae-Joon Kim , Rahul M. Rao
IPC分类号： G01R31/26
CPC分类号： G01R31/2621
摘要： An electronic circuit includes an output terminal and at least a first measuring FET. The second drain-source terminals of a plurality of FETS to be tested are interconnected with the first drain-source terminal of the first measuring FET and the output terminal. The second drain-source terminal of the first measuring FET is interconnected with a first biasing terminal. The first drain-source terminals of the FETS to be tested are interconnected with a second biasing terminal. A state machine is coupled to the gates of the FETS to be tested and the gate of the first measuring FET. The state machine is configured to energize the gate of the first measuring FET and to sequentially energize the gates of the FETS to be tested, so that an output voltage appears on the output terminal. Circuitry to compare the output voltage to a reference value is also provided. The gate of the first measuring field effect transistor is energized; the gates of the field effect transistors to be tested are sequentially energized, whereby an output voltage appears on the output terminal; and the output voltage is compared to the reference value.
摘要翻译：电子电路包括输出端子和至少第一测量FET。待测试的多个FET的第二漏极 - 源极端子与第一测量FET和输出端子的第一漏极 - 源极端子互连。第一测量FET的第二漏极 - 源极端子与第一偏置端子互连。要测试的FETS的第一漏极 - 源极端子与第二偏置端子互连。状态机耦合到要测试的FETs的栅极和第一测量FET的栅极。状态机被配置为对第一测量FET的栅极通电并且顺序地激励要测试的FETS的栅极，使得输出电压出现在输出端子上。还提供了将输出电压与参考值进行比较的电路。第一测量场效应晶体管的栅极通电; 要测试的场效应晶体管的栅极依次通电，从而输出电压出现在输出端上; 并将输出电压与参考值进行比较。

6. 发明申请

US20090309625A1 ELECTRONIC CIRCUIT FOR MEASUREMENT OF TRANSISTOR VARIABILITY AND THE LIKE 有权
标题翻译：用于测量晶体管可变性和类似物的电子电路
公开(公告)号：US20090309625A1
公开(公告)日：2009-12-17
申请号：US12542184
申请日：2009-08-17
申请人： Keith A. Jenkins , Jae-Joon Kim , Rahul M. Rao
发明人： Keith A. Jenkins , Jae-Joon Kim , Rahul M. Rao
IPC分类号： G01R31/26
CPC分类号： G01R31/2621
摘要： An electronic circuit includes an output terminal and at least a first measuring FET. The second drain-source terminals of a plurality of FETS to be tested are interconnected with the first drain-source terminal of the first measuring FET and the output terminal. The second drain-source terminal of the first measuring FET is interconnected with a first biasing terminal. The first drain-source terminals of the FETS to be tested are interconnected with a second biasing terminal. A state machine is coupled to the gates of the FETS to be tested and the gate of the first measuring FET. The state machine is configured to energize the gate of the first measuring FET and to sequentially energize the gates of the FETS to be tested, so that an output voltage appears on the output terminal. Circuitry to compare the output voltage to a reference value is also provided. The gate of the first measuring field effect transistor is energized; the gates of the field effect transistors to be tested are sequentially energized, whereby an output voltage appears on the output terminal; and the output voltage is compared to the reference value.
摘要翻译：电子电路包括输出端子和至少第一测量FET。待测试的多个FET的第二漏极 - 源极端子与第一测量FET和输出端子的第一漏极 - 源极端子互连。第一测量FET的第二漏极 - 源极端子与第一偏置端子互连。要测试的FETS的第一漏极 - 源极端子与第二偏置端子互连。状态机耦合到要测试的FETs的栅极和第一测量FET的栅极。状态机被配置为对第一测量FET的栅极通电并且顺序地激励要测试的FETS的栅极，使得输出电压出现在输出端子上。还提供了将输出电压与参考值进行比较的电路。第一测量场效应晶体管的栅极通电; 要测试的场效应晶体管的栅极依次通电，从而输出电压出现在输出端上; 并将输出电压与参考值进行比较。

7. 发明授权

US07439724B2 On-chip jitter measurement circuit 失效
标题翻译：片上抖动测量电路
公开(公告)号：US07439724B2
公开(公告)日：2008-10-21
申请号：US10638825
申请日：2003-08-11
申请人： David F. Heidel , Keith A. Jenkins
发明人： David F. Heidel , Keith A. Jenkins
IPC分类号： G01R23/00 , H04L7/00 , H03L7/06
CPC分类号： H04L1/205 , G01R29/26 , G01R31/3016 , G01R31/31709 , G01R31/31725
摘要： An on-chip jitter measurement circuit and corresponding method are provided for receiving a reference clock and a signal of interest, including a latch for comparing the arrival time of the signal of interest to the reference clock, a delay chain in signal communication with the reference clock for varying the arrival time of the reference clock, the delay chain having a first stage, a middle stage, and a last stage, a voltage controller in signal communication with the middle stage of the delay chain for controlling the delay of the arrival time of the reference clock while permitting the first and last stages of the delay chain to retain a full voltage swing independent of the delay.
摘要翻译：提供片上抖动测量电路和相应的方法，用于接收参考时钟和感兴趣的信号，包括用于比较感兴趣信号的到达时间与参考时钟的锁存器，与参考时钟信号通信的延迟链用于改变参考时钟的到达时间的时钟，具有第一级，中级和最后级的延迟链，与延迟链的中间级信号通信的电压控制器，用于控制到达时间的延迟的参考时钟，同时允许延迟链的第一级和最后级保持独立于延迟的全电压摆幅。

8. 发明申请

US20080186035A1 ON CHIP TEMPERATURE MEASURING AND MONITORING METHOD 失效
公开(公告)号：US20080186035A1
公开(公告)日：2008-08-07
申请号：US12061692
申请日：2008-04-03
申请人： Robert L. Franch , Keith A. Jenkins
发明人： Robert L. Franch , Keith A. Jenkins
IPC分类号： G01R27/00
CPC分类号： H01L27/0251 , G01K7/01 , G01K7/015
摘要： A device temperature measurement circuit, an integrated circuit (IC) including a device temperature measurement circuit, a method of characterizing device temperature and a method of monitoring temperature. The circuit includes a constant current source and a clamping device. The clamping device selectively shunts current from the constant current source or allows the current to flow through a PN junction, which may be the body to source/drain junction of a field effect transistor (FET). Voltage measurements are taken directly from the PN junction. Junction temperature is determined from measured junction voltage.

9. 发明授权

US07255476B2 On chip temperature measuring and monitoring circuit and method 失效
标题翻译：片上温度测量和监测电路及方法
公开(公告)号：US07255476B2
公开(公告)日：2007-08-14
申请号：US10824297
申请日：2004-04-14
申请人： Robert L. Franch , Keith A. Jenkins
发明人： Robert L. Franch , Keith A. Jenkins
IPC分类号： G01K7/01 , H01L17/78
CPC分类号： H01L27/0251 , G01K7/01 , G01K7/015
摘要： A device temperature measurement circuit, an integrated circuit (IC) including a device temperature measurement circuit, a method of characterizing device temperature and a method of monitoring temperature. The circuit includes a constant current source and a clamping device. The clamping device selectively shunts current from the constant current source or allows the current to flow through a PN junction, which may be the body to source/drain junction of a field effect transistor (FET). Voltage measurements are taken directly from the PN junction. Junction temperature is determined from measured junction voltage.
摘要翻译：一种器件温度测量电路，包括器件温度测量电路的集成电路（IC），表征器件温度的方法和监测温度的方法。电路包括恒流源和夹紧装置。钳位装置选择性地从恒流源分流电流，或允许电流流过PN结，其可以是场效应晶体管（FET）的主体到源极/漏极结。电压测量直接来自PN结。结温从测量的结电压确定。

10. 发明授权

US07033927B2 Apparatus and method for thermal isolation, circuit cooling and electromagnetic shielding of a wafer 有权
标题翻译：晶片的隔热，电路冷却和电磁屏蔽的装置和方法
公开(公告)号：US07033927B2
公开(公告)日：2006-04-25
申请号：US10872451
申请日：2004-06-22
申请人： Guy M. Cohen , Daniel C. Edelstein , Keith A. Jenkins , Chirag S. Patel , Lie Shan
发明人： Guy M. Cohen , Daniel C. Edelstein , Keith A. Jenkins , Chirag S. Patel , Lie Shan
IPC分类号： H01L21/4763
CPC分类号： H01L23/552 , H01L23/3677 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： The disclosure relates to method and apparatus for isolating sensitive regions of a semiconductor device by providing a thermal path or an electromagnetic shield. The thermal path may include vias having different length, depth and configuration such that the thermal path between the two regions is lengthened. In addition, the vias may be fully or partially filled with an insulating material having defined conductive properties to further retard heat electromagnetic or heat transmission between the regions. In another embodiment, electrical isolation between two regions is achieved by etching a closed loop or an open loop trench at the border of the regions and filling the trench with a conductive material to provide proper termination of electromagnetic fields within the substrate.
摘要翻译：本公开涉及通过提供热路径或电磁屏蔽来隔离半导体器件的敏感区域的方法和装置。热路径可以包括具有不同长度，深度和构造的通孔，使得两个区域之间的热路径被延长。此外，通孔可以被完全或部分地填充有具有确定的导电性质的绝缘材料，以进一步延缓区域之间的热电磁或热传递。在另一个实施例中，通过在区域边界处蚀刻闭环或开环沟槽并用导电材料填充沟槽来实现两个区域之间的电隔离，以提供衬底内电磁场的适当终止。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式