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1. 发明申请

US20100301463A1 REDUCED SOFT ERROR RATE THROUGH METAL FILL AND PLACEMENT 有权
标题翻译：通过金属填充和放置减少软错误率
公开(公告)号：US20100301463A1
公开(公告)日：2010-12-02
申请号：US12473435
申请日：2009-05-28
申请人： K. Paul Muller , Alicia Wang
发明人： K. Paul Muller , Alicia Wang
IPC分类号： H01L23/556 , H01L21/71
CPC分类号： H01L23/556 , H01L23/522 , H01L2924/0002 , H01L2924/00
摘要： A method for reducing single event upsets in an integrated circuit includes the step of providing a plurality of levels within the integrated circuit, wherein the plurality of levels within the integrated circuit are in a stacked arrangement. The method also includes the step of providing a plurality of metal fill patterns within each of the plurality of levels within the integrated circuit. The method further includes the step of placing the plurality of metal fill patterns within at least one of the plurality of levels in a pattern such that a line of sight towards an active silicon layer does not exist within the stacked arrangement of the plurality of levels, thereby increasingly absorbing ionizing radiation particles, and thereby reducing single event upsets in the integrated circuit.
摘要翻译：一种用于减少集成电路中的单事件扰乱的方法包括在集成电路内提供多个电平的步骤，其中集成电路内的多个电平处于堆叠布置。该方法还包括在集成电路内的多个电平的每一个内提供多个金属填充图案的步骤。该方法还包括将多个金属填充图案放置在多个层中的至少一个层中的图案的步骤，使得朝向有源硅层的视线不存在于多个层次的堆叠布置中，从而越来越多地吸收电离辐射颗粒，从而减少集成电路中的单个事件的不适。

2. 发明授权

US09165917B2 In-line stacking of transistors for soft error rate hardening 有权
标题翻译：用于软错误率硬化的晶体管的在线堆叠
公开(公告)号：US09165917B2
公开(公告)日：2015-10-20
申请号：US12473409
申请日：2009-05-28
申请人： Ethan H. Cannon , David F. Heidel , K. Paul Muller , Alicia Wang
发明人： Ethan H. Cannon , David F. Heidel , K. Paul Muller , Alicia Wang
IPC分类号： H01L27/11 , H01L27/02 , H01L21/8238 , H01L27/092
CPC分类号： H01L27/0207 , H01L21/823871 , H01L27/092
摘要： Each one of a pair of CMOS transistors is formed in its own island and a gate terminal for each transistor is formed by a single, in-line conductor connecting both gate terminals together. This type of “in-line” connection achieves nearly a five-time improvement in the reduction of the ability of ionizing radiation particles to strike both transistors at the same time as compared to prior art “side-by-side” transistor stacking through use of a relatively smaller solid angle spanning the two transistors. This results in “hardening” of the transistors and improving their resistance to single event upsets and, thus, improving the soft error rate (SER) of the transistors.
摘要翻译：一对CMOS晶体管中的每一个形成在其自身的岛中，并且每个晶体管的栅极端子由连接两个栅极端子的单个直列导体形成。与现有技术的“并排”晶体管堆叠通过使用相比，这种“在线”连接实现了与电离辐射颗粒同时撞击两个晶体管的能力的降低近乎五次的改进具有跨越两个晶体管的相对较小的立体角。这导致了晶体管的“硬化”，并提高了它们对单一事件的影响，从而提高了晶体管的软错误率（SER）。

3. 发明申请

US20100301446A1 IN-LINE STACKING OF TRANSISTORS FOR SOFT ERROR RATE HARDENING 有权
标题翻译：用于软错误速率硬化的晶体管的在线堆叠
公开(公告)号：US20100301446A1
公开(公告)日：2010-12-02
申请号：US12473409
申请日：2009-05-28
申请人： Ethan H. Cannon , David F. Heidel , K. Paul Muller , Alicia Wang
发明人： Ethan H. Cannon , David F. Heidel , K. Paul Muller , Alicia Wang
IPC分类号： H01L27/12 , H01L21/28
CPC分类号： H01L27/0207 , H01L21/823871 , H01L27/092
摘要： Each one of a pair of CMOS transistors is formed in its own island and a gate terminal for each transistor is formed by a single, in-line conductor connecting both gate terminals together. This type of “in-line” connection achieves nearly a five-time improvement in the reduction of the ability of ionizing radiation particles to strike both transistors at the same time as compared to prior art “side-by-side” transistor stacking through use of a relatively smaller solid angle spanning the two transistors. This results in “hardening” of the transistors and improving their resistance to single event upsets and, thus, improving the soft error rate (SER) of the transistors.
摘要翻译：一对CMOS晶体管中的每一个形成在其自身的岛中，并且每个晶体管的栅极端子由连接两个栅极端子的单个直列导体形成。与现有技术的“并排”晶体管堆叠通过使用相比，这种“在线”连接实现了与电离辐射颗粒同时撞击两个晶体管的能力的降低近乎五次的改进具有跨越两个晶体管的相对较小的立体角。这导致了晶体管的“硬化”，并提高了它们对单一事件的影响，从而提高了晶体管的软错误率（SER）。

4. 发明授权

US08102033B2 Reduced soft error rate through metal fill and placement 有权
标题翻译：通过金属填充和放置降低软错误率
公开(公告)号：US08102033B2
公开(公告)日：2012-01-24
申请号：US12473435
申请日：2009-05-28
申请人： K. Paul Muller , Alicia Wang
发明人： K. Paul Muller , Alicia Wang
IPC分类号： H01L23/556
CPC分类号： H01L23/556 , H01L23/522 , H01L2924/0002 , H01L2924/00
摘要： A method for reducing single event upsets in an integrated circuit includes the step of providing a plurality of levels within the integrated circuit, wherein the plurality of levels within the integrated circuit are in a stacked arrangement. The method also includes the step of providing a plurality of metal fill patterns within each of the plurality of levels within the integrated circuit. The method further includes the step of placing the plurality of metal fill patterns within at least one of the plurality of levels in a pattern such that a line of sight towards an active silicon layer does not exist within the stacked arrangement of the plurality of levels, thereby increasingly absorbing ionizing radiation particles, and thereby reducing single event upsets in the integrated circuit.
摘要翻译：一种用于减少集成电路中的单事件扰乱的方法包括在集成电路内提供多个电平的步骤，其中集成电路内的多个电平处于堆叠布置。该方法还包括在集成电路内的多个电平的每一个内提供多个金属填充图案的步骤。该方法还包括将多个金属填充图案放置在多个层中的至少一个层中的图案的步骤，使得朝向有源硅层的视线不存在于多个层次的堆叠布置中，从而越来越多地吸收电离辐射颗粒，从而减少集成电路中的单个事件的不适。

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