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1. 发明申请

US20090280641A1 METHOD OF FORMING A CONTACT STRUCTURE 有权
标题翻译：形成接触结构的方法
公开(公告)号：US20090280641A1
公开(公告)日：2009-11-12
申请号：US12437390
申请日：2009-05-07
申请人： Dae-Hyuk Kang , Young-Hoo Kim , Chang-Ki Hong , Kun-Tack Lee , Jae-Dong Lee , Dae-Hong Eom , Jeong-Nam Han
发明人： Dae-Hyuk Kang , Young-Hoo Kim , Chang-Ki Hong , Kun-Tack Lee , Jae-Dong Lee , Dae-Hong Eom , Jeong-Nam Han
IPC分类号： H01L21/3205
CPC分类号： H01L21/76843 , H01L21/28518 , H01L21/76814 , H01L21/76846 , H01L21/76855 , H01L23/485 , H01L27/24 , H01L2924/0002 , H01L2924/09701 , H01L2924/00
摘要： An insulation layer may be formed on an object having a contact region. The insulation layer may be partially etched to form an opening exposing the contact region. A material layer including silicon and oxygen may be formed on the exposed contact region. A metal layer may be formed on the material layer including silicon and oxygen. The material layer including silicon and oxygen may be reacted with the metal layer to form a metal oxide silicide layer at least on the contact region. A conductive layer may be formed on the metal oxide silicide layer to fill up the opening.
摘要翻译：可以在具有接触区域的物体上形成绝缘层。绝缘层可以被部分蚀刻以形成暴露接触区域的开口。可以在暴露的接触区域上形成包括硅和氧的材料层。可以在包括硅和氧的材料层上形成金属层。包括硅和氧的材料层可以与金属层反应，以至少在接触区域上形成金属氧化物硅化物层。可以在金属氧化物硅化物层上形成导电层以填充开口。

2. 发明授权

US08765551B2 Non-volatile memory device having vertical structure and method of manufacturing the same 有权
标题翻译：具有垂直结构的非易失性存储器件及其制造方法
公开(公告)号：US08765551B2
公开(公告)日：2014-07-01
申请号：US13729856
申请日：2012-12-28
申请人： Jun-youl Yang , Dae-hong Eom , Byoung-moon Yoon , Kyung-hyun Kim , Se-ho Cha
发明人： Jun-youl Yang , Dae-hong Eom , Byoung-moon Yoon , Kyung-hyun Kim , Se-ho Cha
IPC分类号： H01L21/336
CPC分类号： H01L29/7827 , H01L21/28282 , H01L27/1157 , H01L27/11582 , H01L29/7926
摘要： According to an example embodiment, a non-volatile memory device includes a semiconductor layer pattern on a substrate, a plurality of gate patterns and a plurality of interlayer insulating layer patterns that are alternately stacked along a side wall of the semiconductor layer pattern, and a storage structure between the plurality of gate patterns and the semiconductor layer pattern. The semiconductor layer pattern extends in a vertical direction from the substrate. The gate patterns are recessed in a direction from a side wall of the interlayer insulating layer patterns opposing the side wall of the semiconductor layer pattern. A recessed surface of the gate patterns may be formed to be vertical to a surface of the substrate.
摘要翻译：根据示例性实施例，非易失性存储器件包括在衬底上的半导体层图案，沿着半导体层图案的侧壁交替层叠的多个栅极图案和多个层间绝缘层图案，以及多个栅极图案与半导体层图案之间的存储结构。半导体层图案从衬底沿垂直方向延伸。栅极图案沿着与半导体层图案的侧壁相对的层间绝缘层图案的侧壁的方向凹陷。栅极图案的凹陷表面可以形成为垂直于衬底的表面。

3. 发明授权

US08664101B2 Multiple mold structure methods of manufacturing vertical memory devices 有权
标题翻译：制造垂直存储器件的多种模具结构方法
公开(公告)号：US08664101B2
公开(公告)日：2014-03-04
申请号：US13596621
申请日：2012-08-28
申请人： Hyo-Jung Kim , Dae-Hong Eom , Jong-Heun Lim , Myung-Jung Pyo , Byoung-Moon Yoon , Kyung-Hyun Kim
发明人： Hyo-Jung Kim , Dae-Hong Eom , Jong-Heun Lim , Myung-Jung Pyo , Byoung-Moon Yoon , Kyung-Hyun Kim
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L27/11582 , H01L27/11573 , H01L29/7926
摘要： A first insulating interlayer is formed on a substrate including first and second regions. The first insulating interlayer has top surface, a height of which is greater in the first region than in the second region. A first planarization stop layer and a second insulating interlayer are formed. The second insulating interlayer is planarized until the first planarization stop layer is exposed. The first planarization stop layer and the first and second insulating interlayers in the second region are removed to expose the substrate. A lower mold structure including first insulation layer patterns, first sacrificial layer patterns and a second planarization stop layer pattern is formed. The first insulation layer patterns and the first sacrificial layer patterns are alternately and repeatedly formed on the substrate, and a second planarization stop layer pattern is formed on the first insulation layer pattern.
摘要翻译：在包括第一和第二区域的基板上形成第一绝缘中间层。第一绝缘中间层具有顶表面，其高度在第一区域中大于在第二区域中的高度。形成第一平坦化停止层和第二绝缘夹层。平面化第二绝缘层，直到第一平坦化停止层露出。去除第二区域中的第一平坦化停止层和第一和第二绝缘夹层以露出衬底。形成包括第一绝缘层图案，第一牺牲层图案和第二平坦化停止层图案的下模具结构。第一绝缘层图案和第一牺牲层图案在基板上交替重复地形成，并且在第一绝缘层图案上形成第二平坦化停止层图案。

4. 发明申请

US20130171788A1 NON-VOLATILE MEMORY DEVICE HAVING VERTICAL STRUCTURE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：具有垂直结构的非易失性存储器件及其制造方法
公开(公告)号：US20130171788A1
公开(公告)日：2013-07-04
申请号：US13729856
申请日：2012-12-28
申请人： Jun-youl YANG , Dae-hong EOM , Byoung-moon YOON , Kyung-hyun KIM , Se-ho CHA
发明人： Jun-youl YANG , Dae-hong EOM , Byoung-moon YOON , Kyung-hyun KIM , Se-ho CHA
IPC分类号： H01L29/78
CPC分类号： H01L29/7827 , H01L21/28282 , H01L27/1157 , H01L27/11582 , H01L29/7926
摘要： According to an example embodiment, a non-volatile memory device includes a semiconductor layer pattern on a substrate, a plurality of gate patterns and a plurality of interlayer insulating layer patterns that are alternately stacked along a side wall of the semiconductor layer pattern, and a storage structure between the plurality of gate patterns and the semiconductor layer pattern. The semiconductor layer pattern extends in a vertical direction from the substrate. The gate patterns are recessed in a direction from a side wall of the interlayer insulating layer patterns opposing the side wall of the semiconductor layer pattern. A recessed surface of the gate patterns may be formed to be vertical to a surface of the substrate.
摘要翻译：根据示例性实施例，非易失性存储器件包括在衬底上的半导体层图案，沿着半导体层图案的侧壁交替层叠的多个栅极图案和多个层间绝缘层图案，以及多个栅极图案与半导体层图案之间的存储结构。半导体层图案从衬底沿垂直方向延伸。栅极图案沿着与半导体层图案的侧壁相对的层间绝缘层图案的侧壁的方向凹陷。栅极图案的凹陷表面可以形成为垂直于衬底的表面。

5. 发明授权

US08110499B2 Method of forming a contact structure 有权
标题翻译：形成接触结构的方法
公开(公告)号：US08110499B2
公开(公告)日：2012-02-07
申请号：US12437390
申请日：2009-05-07
申请人： Dae-Hyuk Kang , Young-Hoo Kim , Chang-Ki Hong , Kun-Tack Lee , Jae-Dong Lee , Dae-Hong Eom , Jeong-Nam Han
发明人： Dae-Hyuk Kang , Young-Hoo Kim , Chang-Ki Hong , Kun-Tack Lee , Jae-Dong Lee , Dae-Hong Eom , Jeong-Nam Han
IPC分类号： H01L21/44
CPC分类号： H01L21/76843 , H01L21/28518 , H01L21/76814 , H01L21/76846 , H01L21/76855 , H01L23/485 , H01L27/24 , H01L2924/0002 , H01L2924/09701 , H01L2924/00
摘要： An insulation layer may be formed on an object having a contact region. The insulation layer may be partially etched to form an opening exposing the contact region. A material layer including silicon and oxygen may be formed on the exposed contact region. A metal layer may be formed on the material layer including silicon and oxygen. The material layer including silicon and oxygen may be reacted with the metal layer to form a metal oxide silicide layer at least on the contact region. A conductive layer may be formed on the metal oxide silicide layer to fill up the opening.
摘要翻译：可以在具有接触区域的物体上形成绝缘层。绝缘层可以被部分蚀刻以形成暴露接触区域的开口。可以在暴露的接触区域上形成包括硅和氧的材料层。可以在包括硅和氧的材料层上形成金属层。包括硅和氧的材料层可以与金属层反应，以至少在接触区域上形成金属氧化物硅化物层。可以在金属氧化物硅化物层上形成导电层以填充开口。

6. 发明申请

US20110287625A1 METHODS OF FORMING A PATTERN, METHODS OF FORMING A GATE STRUCTURE AND METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE USING THE SAME 审中-公开
标题翻译：形成图案的方法，形成门结构的方法和使用该方法制造半导体器件的方法
公开(公告)号：US20110287625A1
公开(公告)日：2011-11-24
申请号：US13079202
申请日：2011-04-04
申请人： Dae-Hyuk Kang , Kun-Tack Lee , Dae-Hong Eom , Bo-Un Yoon , Jeong-Nam Han
发明人： Dae-Hyuk Kang , Kun-Tack Lee , Dae-Hong Eom , Bo-Un Yoon , Jeong-Nam Han
IPC分类号： H01L21/336
CPC分类号： H01L21/28123 , H01L21/3081 , H01L21/31111 , H01L21/31116 , H01L21/31144 , H01L21/32139 , H01L27/11524 , H01L29/40114
摘要： A method of forming a pattern in a semiconductor device includes forming an etching object layer on a substrate, the etching object layer is an oxide that is substantially free of impurities. A mask is formed on the etching object layer, the mask is an oxide that includes impurities. The etching object layer is patterned using the mask as an etching mask and then the mask is removed. The mask is removed using an etchant having an etching selectivity to an oxide that is substantially free of impurities and an oxide that includes impurities during removing of the mask to limit damage to the patterned etching object layer during removal of the mask.
摘要翻译：在半导体器件中形成图案的方法包括在基板上形成蚀刻对象层，蚀刻对象层是基本上不含杂质的氧化物。在蚀刻对象层上形成掩模，掩模是包含杂质的氧化物。使用掩模将蚀刻对象层图案化为蚀刻掩模，然后去除掩模。使用具有对基本上不含杂质的氧化物的蚀刻选择性的蚀刻剂去除掩模，以及在除去掩模期间包括杂质的氧化物，以限制在去除掩模期间对图案化的蚀刻对象层的损伤。

7. 发明申请

US20090025755A1 Method for treating substrate 审中-公开
标题翻译：底物处理方法
公开(公告)号：US20090025755A1
公开(公告)日：2009-01-29
申请号：US12219562
申请日：2008-07-24
申请人： Dae-Hong Eom , Chang-Ki Hong , Woo-Gwan Shim , Young-Ok Kim
发明人： Dae-Hong Eom , Chang-Ki Hong , Woo-Gwan Shim , Young-Ok Kim
IPC分类号： B08B3/10
CPC分类号： B08B3/04 , B08B3/10 , H01L21/67034 , H01L21/67051
摘要： Example embodiments relate to a method of treating a substrate after performing a cleaning step with a liquid chemical in a single substrate spin cleaner. A method of treating a substrate according to example embodiments may include forming a film of deionized water on a surface of the substrate during rinsing, and drying the substrate by supplying a drying gas to the water film on the surface of the substrate. When rinsing the substrate, the rotating speed of the substrate may be reduced to about 50 rpm or less to form a film of water on the surface of the substrate. The film of water may shield the surface of the substrate from direct exposure to atmospheric air. The film of water may be maintained on the surface of the substrate when commencing the supply of the drying gas. Consequently, the number of water marks on the dried substrate may be reduced or prevented.
摘要翻译：示例性实施方案涉及在单个底物旋转清洁剂中用液体化学品进行清洁步骤之后处理基材的方法。根据示例性实施方案的处理基材的方法可以包括在漂洗期间在基材的表面上形成去离子水膜，并通过向基材表面上的水膜供应干燥气体来干燥基材。当冲洗基板时，基板的旋转速度可以降低到约50rpm或更小，以在基板的表面上形成水膜。水膜可以屏蔽衬底表面直接暴露于大气中。当开始供应干燥气体时，水膜可以保持在基板的表面上。因此，可以减少或防止干燥的基板上的水痕的数量。

8. 发明申请

US20150155297A1 METHODS OF FABRICATING SEMICONDUCTOR DEVICES HAVING DOUBLE-LAYERED BLOCKING INSULATING LAYERS 审中-公开
标题翻译：制备具有双层隔离绝缘层的半导体器件的方法
公开(公告)号：US20150155297A1
公开(公告)日：2015-06-04
申请号：US14315906
申请日：2014-06-26
申请人： Dae-hong EOM , Dong-Chul YOO , Kyung-Hyun KIM , Ki-Hyun HWANG
发明人： Dae-hong EOM , Dong-Chul YOO , Kyung-Hyun KIM , Ki-Hyun HWANG
IPC分类号： H01L27/115
CPC分类号： H01L27/11582 , H01L29/40117 , H01L29/66833 , H01L29/7926
摘要： Provided is a method of fabricating a semiconductor memory device. The method includes alternately stacking interlayer insulating layers and sacrificial layers on a substrate, forming a channel hole exposing the substrate through the interlayer insulating layers and the sacrificial layers, sequentially forming a blocking insulating layer, an electric charge storage layer and a channel layer on a substrate exposed on a sidewall of the channel hole and in the channel hole wherein the blocking insulating layer includes a first blocking insulating layer and a second blocking insulating layer, selectively removing the sacrificial layers to expose the first blocking insulating layer and then forming a gap, removing the first blocking insulating layer exposed in the gap, forming first blocking insulating patterns between the interlayer insulating layers and the second blocking insulating layer, and forming a gate electrode in the gap.
摘要翻译：提供一种制造半导体存储器件的方法。该方法包括在衬底上交替堆叠层间绝缘层和牺牲层，形成通过层间绝缘层和牺牲层暴露衬底的沟道孔，在其上依次形成阻挡绝缘层，电荷存储层和沟道层衬底暴露在通道孔的侧壁和通道孔中，其中阻挡绝缘层包括第一阻挡绝缘层和第二阻挡绝缘层，选择性地去除牺牲层以暴露第一阻挡绝缘层，然后形成间隙，去除在所述间隙中暴露的所述第一阻挡绝缘层，在所述层间绝缘层和所述第二阻挡绝缘层之间形成第一阻挡绝缘图案，以及在所述间隙中形成栅电极。

9. 发明申请

US20130065386A1 MULTIPLE MOLD STRUCTURE METHODS OF MANUFACTURING VERTICAL MEMORY DEVICES 有权
标题翻译：制造垂直存储器件的多种模具结构方法
公开(公告)号：US20130065386A1
公开(公告)日：2013-03-14
申请号：US13596621
申请日：2012-08-28
申请人： Hyo-Jung Kim , Dae-Hong Eom , Jong-Heun Lim , Myung-Jung Pyo , Byoung-Moon Yoon , Kyung-Hyun Kim
发明人： Hyo-Jung Kim , Dae-Hong Eom , Jong-Heun Lim , Myung-Jung Pyo , Byoung-Moon Yoon , Kyung-Hyun Kim
IPC分类号： H01L21/336
CPC分类号： H01L27/11582 , H01L27/11573 , H01L29/7926
摘要： A first insulating interlayer is formed on a substrate including first and second regions. The first insulating interlayer has top surface, a height of which is greater in the first region than in the second region. A first planarization stop layer and a second insulating interlayer are formed. The second insulating interlayer is planarized until the first planarization stop layer is exposed. The first planarization stop layer and the first and second insulating interlayers in the second region are removed to expose the substrate. A lower mold structure including first insulation layer patterns, first sacrificial layer patterns and a second planarization stop layer pattern is formed. The first insulation layer patterns and the first sacrificial layer patterns are alternately and repeatedly formed on the substrate, and a second planarization stop layer pattern is formed on the first insulation layer pattern.
摘要翻译：在包括第一和第二区域的基板上形成第一绝缘中间层。第一绝缘中间层具有顶表面，其高度在第一区域中大于在第二区域中的高度。形成第一平坦化停止层和第二绝缘夹层。平面化第二绝缘层，直到第一平坦化停止层露出。去除第二区域中的第一平坦化停止层和第一和第二绝缘夹层以露出衬底。形成包括第一绝缘层图案，第一牺牲层图案和第二平坦化停止层图案的下模具结构。第一绝缘层图案和第一牺牲层图案在基板上交替重复地形成，并且在第一绝缘层图案上形成第二平坦化停止层图案。

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