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1. 发明申请

US20090025755A1 Method for treating substrate 审中-公开
标题翻译：底物处理方法
公开(公告)号：US20090025755A1
公开(公告)日：2009-01-29
申请号：US12219562
申请日：2008-07-24
申请人： Dae-Hong Eom , Chang-Ki Hong , Woo-Gwan Shim , Young-Ok Kim
发明人： Dae-Hong Eom , Chang-Ki Hong , Woo-Gwan Shim , Young-Ok Kim
IPC分类号： B08B3/10
CPC分类号： B08B3/04 , B08B3/10 , H01L21/67034 , H01L21/67051
摘要： Example embodiments relate to a method of treating a substrate after performing a cleaning step with a liquid chemical in a single substrate spin cleaner. A method of treating a substrate according to example embodiments may include forming a film of deionized water on a surface of the substrate during rinsing, and drying the substrate by supplying a drying gas to the water film on the surface of the substrate. When rinsing the substrate, the rotating speed of the substrate may be reduced to about 50 rpm or less to form a film of water on the surface of the substrate. The film of water may shield the surface of the substrate from direct exposure to atmospheric air. The film of water may be maintained on the surface of the substrate when commencing the supply of the drying gas. Consequently, the number of water marks on the dried substrate may be reduced or prevented.
摘要翻译：示例性实施方案涉及在单个底物旋转清洁剂中用液体化学品进行清洁步骤之后处理基材的方法。根据示例性实施方案的处理基材的方法可以包括在漂洗期间在基材的表面上形成去离子水膜，并通过向基材表面上的水膜供应干燥气体来干燥基材。当冲洗基板时，基板的旋转速度可以降低到约50rpm或更小，以在基板的表面上形成水膜。水膜可以屏蔽衬底表面直接暴露于大气中。当开始供应干燥气体时，水膜可以保持在基板的表面上。因此，可以减少或防止干燥的基板上的水痕的数量。

2. 发明申请

US20050026329A1 Semiconductor device for applying well bias and method of fabricating the same 失效
标题翻译：用于施加阱偏压的半导体器件及其制造方法
公开(公告)号：US20050026329A1
公开(公告)日：2005-02-03
申请号：US10925429
申请日：2004-08-24
申请人： Young-Ok Kim , Soon-Byung Park
发明人： Young-Ok Kim , Soon-Byung Park
IPC分类号： H01L21/8244 , H01L23/485 , H01L21/44
CPC分类号： H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： A first conduction type well is formed in a substrate, and a second conduction type impurity region is formed in the well. A lower interlayer dielectric is formed on the substrate, including the well and the impurity region. A contact plug, connected to the impurity region through the lower interlayer dielectric, is formed with a void inside it. An upper interlayer dielectric is formed on the lower interlayer dielectric and the contact plug. The upper interlayer dielectric is selectively etched, forming an interconnection groove exposing the contact plug. The contact plug and the exposed void are overetched, extending the void into the first conduction type well. The interconnection groove is filled with a conductive layer, forming an interconnection. A seam extending to the well is formed in the void, connecting the contact plug to the well. Due to the seam, a well bias may be applied to the well.
摘要翻译：在衬底中形成第一导电型阱，并在阱中形成第二导电型杂质区。在衬底上形成下层的电介质，包括阱和杂质区。通过下层间电介质连接到杂质区域的接触插塞在其内部形成有空隙。在下层间电介质和接触插塞上形成上层间电介质。选择性地蚀刻上层间电介质，形成露出接触插塞的互连凹槽。接触塞和暴露的空隙被过蚀刻，将空隙延伸到第一导电类型的孔中。互连槽填充有导电层，形成互连。在空隙中形成延伸到井的接缝，将接触塞连接到井。由于接缝，井可能会施加良好的偏压。

3. 发明申请

US20090038883A1 SOUND-ABSORBING PANEL 审中-公开
标题翻译：声音吸收面板
公开(公告)号：US20090038883A1
公开(公告)日：2009-02-12
申请号：US11917703
申请日：2006-06-07
申请人： Young-Ok Kim
发明人： Young-Ok Kim
IPC分类号： E04B1/86
CPC分类号： E04B1/86 , E04B2001/8414 , E04B2001/8433 , E04B2001/8442
摘要： The present invention relates to a sound-absorbing panel in which the structure of a vibration type sound-absorbing panel for absorbing and offsetting sound waves belonging to a low frequency band is modified to improve a sound absorption effect. A sound-absorbing panel comprises a panel body opened on a lower end thereof and formed on the lower end thereof with a rib which extends outward by a predetermined length, and a plurality of sound-absorbing holes defined on an upper surface of the panel body and possessing a sectional shape of a predetermined figure, each sound-absorbing hole being tapered downward to have an inside space which has a gradually decreasing size and then linearly perforated to have an inside space which has a constant size.
摘要翻译：本发明涉及一种吸音板，其中改变了用于吸收和抵消属于低频带的声波的振动型吸声板的结构，以改善吸声效果。吸音板包括在其下端开口并在其下端形成有向外延伸预定长度的肋的面板体，以及限定在面板本体的上表面上的多个吸音孔并且具有预定图形的截面形状，每个吸音孔向下锥形以具有逐渐减小的尺寸的内部空间，然后被线性穿孔以具有恒定尺寸的内部空间。

4. 发明授权

US07041594B2 Semiconductor device for applying well bias and method of fabricating the same 失效
标题翻译：用于施加阱偏压的半导体器件及其制造方法
公开(公告)号：US07041594B2
公开(公告)日：2006-05-09
申请号：US10925429
申请日：2004-08-24
申请人： Young-Ok Kim , Soon-Byung Park
发明人： Young-Ok Kim , Soon-Byung Park
IPC分类号： H01L21/4763
CPC分类号： H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： A first conduction type well is formed in a substrate, and a second conduction type impurity region is formed in the well. A lower interlayer dielectric is formed on the substrate, including the well and the impurity region. A contact plug, connected to the impurity region through the lower interlayer dielectric, is formed with a void inside it. An upper interlayer dielectric is formed on the lower interlayer dielectric and the contact plug. The upper interlayer dielectric is selectively etched, forming an interconnection groove exposing the contact plug. The contact plug and the exposed void are overetched, extending the void into the first conduction type well. The interconnection groove is filled with a conductive layer, forming an interconnection. A seam extending to the well is formed in the void, connecting the contact plug to the well. Due to the seam, a well bias may be applied to the well.
摘要翻译：在衬底中形成第一导电型阱，并在阱中形成第二导电型杂质区。在衬底上形成下层的电介质，包括阱和杂质区。通过下层间电介质连接到杂质区域的接触插塞在其内部形成有空隙。在下层间电介质和接触插塞上形成上层间电介质。选择性地蚀刻上层间电介质，形成露出接触插塞的互连凹槽。接触塞和暴露的空隙被过蚀刻，将空隙延伸到第一导电类型的孔中。互连槽填充有导电层，形成互连。在空隙中形成延伸到井的接缝，将接触塞连接到井。由于接缝，井可能会施加良好的偏压。

5. 发明授权

US06730971B2 Semiconductor devices and methods of fabricating the same 有权
公开(公告)号：US06730971B2
公开(公告)日：2004-05-04
申请号：US10289721
申请日：2002-11-06
申请人： Sun-Ha Hwang , Young-Ok Kim , Cha-Dong Yeo
发明人： Sun-Ha Hwang , Young-Ok Kim , Cha-Dong Yeo
IPC分类号： H01L2976
CPC分类号： H01L21/823814 , H01L21/823878
摘要： A semiconductor device comprises a device isolation layer disposed in a portion of a substrate of first conductivity type. An outline of the device isolation layer defines an active region of the substrate. An impurity diffused region of second conductivity type may be formed in a portion of the active region; and a silicide layer may be formed to cover the impurity diffused region of second conductivity type. The device isolation layer may include a recess formed therein to expose a portion of the substrate of first conductivity type adjacent to the impurity diffused region of second conductivity type. The silicide layer that is formed to cover the impurity diffused layer of second conductivity type may extend over and against the exposed region of the substrate of first conductivity type that was exposed by the recess of the device isolation layer.

6. 发明授权

US07074683B2 Semiconductor devices and methods of fabricating the same 失效
公开(公告)号：US07074683B2
公开(公告)日：2006-07-11
申请号：US10796754
申请日：2004-03-08
申请人： Sun-Ha Hwang , Young-Ok Kim , Cha-Dong Yeo
发明人： Sun-Ha Hwang , Young-Ok Kim , Cha-Dong Yeo
IPC分类号： H01L21/336
CPC分类号： H01L21/823814 , H01L21/823878
摘要： A semiconductor device comprises a device isolation layer disposed in a portion of a substrate of first conductivity type. An outline of the device isolation layer defines an active region of the substrate. An impurity diffused region of second conductivity type may be formed in a portion of the active region; and a silicide layer may be formed to cover the impurity diffused region of second conductivity type. The device isolation layer may include a recess formed therein to expose a portion of the substrate of first conductivity type adjacent to the impurity diffused region of second conductivity type. The silicide layer that is formed to cover the impurity diffused layer of second conductivity type may extend over and against the exposed region of the substrate of first conductivity type that was exposed by the recess of the device isolation layer.

7. 发明授权

US06838737B2 Semiconductor device for applying well bias and method of fabricating the same 有权
标题翻译：用于施加阱偏压的半导体器件及其制造方法
公开(公告)号：US06838737B2
公开(公告)日：2005-01-04
申请号：US10630486
申请日：2003-07-29
申请人： Young-Ok Kim , Soon-Byung Park
发明人： Young-Ok Kim , Soon-Byung Park
IPC分类号： H01L21/8244 , H01L23/485 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： A first conduction type well is formed in a substrate, and a second conduction type impurity region is formed in the well. A lower interlayer dielectric is formed on the substrate, including the well and the purity region. A contact plug, connected to the impurity region through the lower interlayer dielectric, is formed with a void inside it. An upper interlayer dielectric is formed on the lower interlayer dielectric and the contact plug. The upper interlayer dielectric is selectively etched, forming an interconnection groove exposing the contact plug. The contact plug and the exposed void are overetched, extending the void into the first conduction type well. The interconnection groove is filled with a conductive layer, forming an interconnection. A seam extending to the well is formed in the void, connecting the contact plug to the well. Due to the seam, a well bias may be applied to the well.
摘要翻译：在衬底中形成第一导电型阱，并在阱中形成第二导电型杂质区。在衬底上形成下层的电介质，包括阱和纯度区。通过下层间电介质连接到杂质区域的接触插塞在其内部形成有空隙。在下层间电介质和接触插塞上形成上层间电介质。选择性地蚀刻上层间电介质，形成露出接触插塞的互连凹槽。接触塞和暴露的空隙被过蚀刻，将空隙延伸到第一导电类型的孔中。互连槽填充有导电层，形成互连。在空隙中形成延伸到井的接缝，将接触塞连接到井。由于接缝，井可能会施加良好的偏压。

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