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    • 4. 发明授权
    • Cyclic redundancy check code generating circuit, semiconductor memory device, and method of driving semiconductor memory device
    • 循环冗余校验码产生电路,半导体存储器件以及驱动半导体存储器件的方法
    • US08321777B2
    • 2012-11-27
    • US12002557
    • 2007-12-18
    • Kyung-hyun Kim
    • Kyung-hyun Kim
    • G06F11/00H03M13/00
    • H03M13/09G06F11/1004H03M13/1102H03M13/136H03M13/1515H03M13/19H03M13/2957
    • Disclosed are a semiconductor memory device, and a method of driving the same, and a cyclic redundancy check code generating circuit capable of performing cyclic redundancy check. A semiconductor memory device according to an aspect of the present invention includes a memory cell array, a data processing unit receiving data that is read from the memory cell array and selectively outputting at least some of the data according to ordering information, bit structure information, and burst length information, and a check code generating unit generating a cyclic redundancy check code to detect an error in the data being output, the check code generating unit generating and outputting the cyclic redundancy check code by using the read data, the ordering information, the bit structure information, and the burst length information.
    • 公开了一种半导体存储器件及其驱动方法,以及能够执行循环冗余校验的循环冗余校验码产生电路。 根据本发明的一个方面的半导体存储器件包括存储单元阵列,数据处理单元,接收从存储单元阵列读取的数据,并根据排序信息,比特结构信息选择性地输出数据中的至少一些, 检测码生成部,生成循环冗余校验码,检测出正在输出的数据的错误;校验码生成部,使用读取的数据生成并输出循环冗余校验码,排序信息, 比特结构信息和突发长度信息。
    • 5. 发明授权
    • Methods of manufacturing semiconductor devices
    • 制造半导体器件的方法
    • US08283248B2
    • 2012-10-09
    • US13234558
    • 2011-09-16
    • Tae-Hyun KimKyung-Hyun KimJae-Hwang SimJae-Jin ShinJong-Heun LimHyun-Min Park
    • Tae-Hyun KimKyung-Hyun KimJae-Hwang SimJae-Jin ShinJong-Heun LimHyun-Min Park
    • H01L21/4763
    • H01L27/11526H01L21/764H01L21/7682H01L27/11529H01L27/11573
    • A method of manufacturing a semiconductor device includes forming a plurality of preliminary gate structures, forming a capping layer pattern on sidewalls of the plurality of preliminary gate structures, and forming a blocking layer on top surfaces of the plurality of preliminary gate structures and the capping layer pattern such that a void is formed therebetween. The method also includes removing the blocking layer and an upper portion of the capping layer pattern such that at least the upper sidewalls of the plurality of preliminary gate structures are exposed, and a lower portion of the capping layer pattern remains on lower sidewalls of the preliminary gate structures. The method further includes forming a conductive layer on at least the upper sidewalls of the plurality of preliminary gate structures, reacting the conductive layer with the preliminary gate structures, and forming an insulation layer having an air gap therein.
    • 一种制造半导体器件的方法包括:形成多个初步栅极结构,在多个预选栅极结构的侧壁上形成覆盖层图案,以及在多个预选栅极结构的顶表面上形成阻挡层,并且覆盖层 使得它们之间形成空隙。 该方法还包括去除阻挡层和覆盖层图案的上部,使得至少多个预选栅极结构的上侧壁被暴露,并且覆盖层图案的下部保留在预备的栅极结构的下侧壁上 门结构。 所述方法还包括在所述多个预选择门结构的至少上侧壁上形成导电层,使所述导电层与所述预选栅极结构反应,以及在其中形成具有气隙的绝缘层。