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1. 发明申请

US20150155297A1 METHODS OF FABRICATING SEMICONDUCTOR DEVICES HAVING DOUBLE-LAYERED BLOCKING INSULATING LAYERS 审中-公开
标题翻译：制备具有双层隔离绝缘层的半导体器件的方法
公开(公告)号：US20150155297A1
公开(公告)日：2015-06-04
申请号：US14315906
申请日：2014-06-26
申请人： Dae-hong EOM , Dong-Chul YOO , Kyung-Hyun KIM , Ki-Hyun HWANG
发明人： Dae-hong EOM , Dong-Chul YOO , Kyung-Hyun KIM , Ki-Hyun HWANG
IPC分类号： H01L27/115
CPC分类号： H01L27/11582 , H01L29/40117 , H01L29/66833 , H01L29/7926
摘要： Provided is a method of fabricating a semiconductor memory device. The method includes alternately stacking interlayer insulating layers and sacrificial layers on a substrate, forming a channel hole exposing the substrate through the interlayer insulating layers and the sacrificial layers, sequentially forming a blocking insulating layer, an electric charge storage layer and a channel layer on a substrate exposed on a sidewall of the channel hole and in the channel hole wherein the blocking insulating layer includes a first blocking insulating layer and a second blocking insulating layer, selectively removing the sacrificial layers to expose the first blocking insulating layer and then forming a gap, removing the first blocking insulating layer exposed in the gap, forming first blocking insulating patterns between the interlayer insulating layers and the second blocking insulating layer, and forming a gate electrode in the gap.
摘要翻译：提供一种制造半导体存储器件的方法。该方法包括在衬底上交替堆叠层间绝缘层和牺牲层，形成通过层间绝缘层和牺牲层暴露衬底的沟道孔，在其上依次形成阻挡绝缘层，电荷存储层和沟道层衬底暴露在通道孔的侧壁和通道孔中，其中阻挡绝缘层包括第一阻挡绝缘层和第二阻挡绝缘层，选择性地去除牺牲层以暴露第一阻挡绝缘层，然后形成间隙，去除在所述间隙中暴露的所述第一阻挡绝缘层，在所述层间绝缘层和所述第二阻挡绝缘层之间形成第一阻挡绝缘图案，以及在所述间隙中形成栅电极。

2. 发明申请

US20090175328A1 DECISION FEEDBACK EQUALIZER (DFE) CIRCUITS FOR USE IN A SEMICONDUCTOR MEMORY DEVICE AND INITIALIZING METHOD THEREOF 有权
标题翻译：用于半导体存储器件的决策反馈均衡器（DFE）电路及其初始化方法
公开(公告)号：US20090175328A1
公开(公告)日：2009-07-09
申请号：US12261814
申请日：2008-10-30
申请人： Kyung-Hyun KIM , Yongsam MOON
发明人： Kyung-Hyun KIM , Yongsam MOON
IPC分类号： H03H7/30
CPC分类号： G11C7/20 , G11C7/02 , G11C7/1006 , G11C7/1078 , G11C7/1084 , G11C27/02
摘要： A DFE circuit for use in a semiconductor memory device and an initializing method thereof. In the method of initializing a DFE circuit used in a semiconductor memory device having a discontinuous data transmission, the DFE circuit may be used for changing a sampling reference level in response to a level of previous data and sampling transmission data. The method includes terminating a data channel having a transmission of the transmission data at a predefined termination level, and controlling a sampling start time point of the transmission data as a time point preceding a transmission time point of the transmission data by a predefined time. Further, an initialization may be performed of the previous data on the basis of initialization data obtained through a pre-sampling of the data channel at a sampling start time point of the transmission data, thereby obtaining an initialization of the DFE circuit and compensating for a feedback delay.
摘要翻译：一种用于半导体存储器件的DFE电路及其初始化方法。在具有不连续数据传输的半导体存储器件中使用的DFE电路的初始化方法中，DFE电路可以用于响应于先前数据的电平和采样发送数据来改变采样基准电平。该方法包括终止在预定的终止级别具有传输数据的传输的数据信道，并且将传输数据的采样开始时间点控制在传输数据的传输时间点之前的时间点预定的时间。此外，可以基于在发送数据的采样开始时间点通过数据信道的预采样获得的初始化数据来执行先前数据的初始化，从而获得DFE电路的初始化并补偿反馈延迟。

3. 发明申请

US20170084532A1 VERTICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME 审中-公开
公开(公告)号：US20170084532A1
公开(公告)日：2017-03-23
申请号：US15271605
申请日：2016-09-21
申请人： Yong-Hoon SON , Cha-Dong YEO , Han-Mei CHOI , Kyung-Hyun KIM , Phil-Ouk NAM , Kwang-Chui PARK , Yeon-Sil SOHN , Jin-I LEE , Won-Bong JUNG
发明人： Yong-Hoon SON , Cha-Dong YEO , Han-Mei CHOI , Kyung-Hyun KIM , Phil-Ouk NAM , Kwang-Chui PARK , Yeon-Sil SOHN , Jin-I LEE , Won-Bong JUNG
IPC分类号： H01L23/522 , H01L21/768 , H01L23/532 , H01L27/115 , H01L23/528
CPC分类号： H01L23/5226 , H01L21/76816 , H01L21/76877 , H01L27/11565 , H01L27/1157 , H01L27/11575 , H01L27/11582
摘要： A vertical memory device includes a substrate, a plurality of channels on the substrate and extending in a vertical direction with respect to a top surface of the substrate, a plurality of non-metal gate patterns surrounding the channels and being stacked on top of each other and spaced apart from each other along the vertical direction, and a plurality of metal gate patterns stacked on top of each other. The metal gate patterns are spaced apart from each other along the vertical direction. Each of the metal gate patterns surrounds a corresponding one of the non-metal gate patterns.

4. 发明申请

US20140048945A1 NONVOLATILE MEMORY DEVICE AND A METHOD FOR FABRICATING THE SAME 有权
标题翻译：非易失存储器件及其制造方法
公开(公告)号：US20140048945A1
公开(公告)日：2014-02-20
申请号：US13927914
申请日：2013-06-26
申请人： Jong-Heun LIM , Hyo-Jung KIM , Ji-Woon IM , Kyung-Hyun KIM
发明人： Jong-Heun LIM , Hyo-Jung KIM , Ji-Woon IM , Kyung-Hyun KIM
IPC分类号： H01L23/48
CPC分类号： H01L23/48 , H01L27/11575 , H01L27/11582 , H01L2924/0002 , H01L2924/00
摘要： A nonvolatile memory device including a substrate which includes a cell array region and a connection region, an electrode structure formed on the cell array region and the connection region and including a plurality of laminated electrodes, a first recess formed in the electrode structure on the connection region and disposed between the cell array region and a second recess formed in the electrode structure on the connection region, and a plurality of vertical wirings formed on the plurality of electrodes exposed by the first recess.
摘要翻译：一种非易失性存储器件，包括：包括单元阵列区域和连接区域的基板;形成在单元阵列区域上的电极结构和连接区域，并且包括多个层压电极;形成在电极结构中的第一凹部，并且布置在单元阵列区域和形成在连接区域上的电极结构中的第二凹槽之间，以及形成在由第一凹部暴露的多个电极上的多个垂直布线。

5. 发明申请

US20110136216A1 DIAGNOSTIC KIT FOR RESPIRATORY DISEASE 审中-公开
标题翻译：用于呼吸道疾病的诊断用具
公开(公告)号：US20110136216A1
公开(公告)日：2011-06-09
申请号：US12902442
申请日：2010-10-12
申请人： Kyung-Hyun KIM , Chul Huh , Chil-Seong Ah , Gun-Yong Sung
发明人： Kyung-Hyun KIM , Chul Huh , Chil-Seong Ah , Gun-Yong Sung
IPC分类号： C12M1/34
CPC分类号： G01N33/54366 , B01L3/5027 , G01N33/56983 , G01N2800/12
摘要： The present invention relates to a diagnostic kit for a respiratory disease that enables a preprocessing process with respect to a sample to be performed within a diagnostic kit when diagnosing respiratory disease using the diagnostic kit, and thereby enables all the operations starting from collecting the sample to verifying a diagnosis result to be automatically performed within the diagnostic kit. The diagnostic kit for a respiratory disease may perform a field diagnosis at anywhere without being restricted to a specific location, and even a general user may also easily obtain an accurate diagnosis result.
摘要翻译：本发明涉及一种用于呼吸疾病的诊断试剂盒，其能够使用诊断试剂盒诊断呼吸系统疾病时能够在诊断试剂盒内进行关于样品的预处理过程，从而使从收集样品开始的所有操作验证诊断结果在诊断套件内自动执行。用于呼吸系统疾病的诊断套件可以在任何地方执行现场诊断，而不限于特定位置，甚至一般用户也可以容易地获得准确的诊断结果。

6. 发明申请

US20160343730A1 Vertical Memory Devices 有权
标题翻译：垂直存储器件
公开(公告)号：US20160343730A1
公开(公告)日：2016-11-24
申请号：US15155732
申请日：2016-05-16
申请人： Yong-Hoon Son , Kyung-Hyun KIM , Byeong-Ju KIM , Phil-Ouk NAM , Kwang Chul PARK , Yeon-Sil SOHN , Jin-I LEE , Jong-Heun LIM , Won-Bong JUNG , Kohji KANAMORI
发明人： Yong-Hoon Son , Kyung-Hyun KIM , Byeong-Ju KIM , Phil-Ouk NAM , Kwang Chul PARK , Yeon-Sil SOHN , Jin-I LEE , Jong-Heun LIM , Won-Bong JUNG , Kohji KANAMORI
IPC分类号： H01L27/115 , H01L23/528
CPC分类号： H01L27/11582 , H01L23/528
摘要： A vertical memory device includes a substrate, a channel on the substrate, extending in a vertical direction with respect to a top surface of the substrate, and including a protrusion at a lower portion of the channel, the protrusion extending in a parallel direction with respect to the top surface of the substrate, a semiconductor pattern connecting the protrusion and the substrate, and gate lines stacked and spaced apart from each other in the vertical direction, the gate lines on the protrusion and the semiconductor pattern and surrounding the channel.
摘要翻译：垂直存储器件包括衬底，衬底上的通道，相对于衬底的顶表面在垂直方向上延伸，并且在通道的下部包括突起，所述突起在平行方向上相对于到基板的顶面，连接突起和基板的半导体图案，以及在垂直方向上彼此堆叠和间隔开的栅极线，突起和半导体图案上的栅极线并围绕通道。

7. 发明申请

US20110204427A1 CAPACITOR HAVING AN ELECTRODE STRUCTURE, METHOD OF MANUFACTURING A CAPACITOR HAVING AN ELECTRODE STRUCTURE AND SEMICONDUCTOR DEVICE HAVING AN ELECTRODE STRUCTURE 有权
标题翻译：具有电极结构的电容器，具有电极结构的电容器的制造方法和具有电极结构的半导体器件
公开(公告)号：US20110204427A1
公开(公告)日：2011-08-25
申请号：US13035342
申请日：2011-02-25
申请人： Suk-Hun CHOI , Kyung-Hyun KIM , Chang-Sup MUN , Sung-Jun KIM , Jin-I LEE
发明人： Suk-Hun CHOI , Kyung-Hyun KIM , Chang-Sup MUN , Sung-Jun KIM , Jin-I LEE
IPC分类号： H01L29/772 , H01G4/06 , H01G7/00
CPC分类号： H01L27/10852 , H01G4/33 , H01L27/10894 , H01L28/91
摘要： A capacitor includes an object or a substrate including an insulation layer having an opening, an electrode structure having conductive patterns, a dielectric layer and an upper electrode. The electrode structure may have a first conductive pattern including metal and a second conductive pattern including metal oxide generated from the first conductive pattern. The first conductive pattern may fill the opening and may protrude over the insulation layer. The second conductive pattern may extend from the first conductive pattern. The electrode structure may additionally include a third conductive pattern disposed on the second conductive pattern. The capacitor including the electrode structure may ensure improved structural stability and electrical characteristics.
摘要翻译：电容器包括具有开口的绝缘层，具有导电图案的电极结构，电介质层和上部电极的物体或基板。电极结构可以具有包括金属的第一导电图案和包括从第一导电图案产生的金属氧化物的第二导电图案。第一导电图案可以填充开口并且可以突出在绝缘层上。第二导电图案可以从第一导电图案延伸。电极结构可以另外包括设置在第二导电图案上的第三导电图案。包括电极结构的电容器可以确保改进的结构稳定性和电特性。

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