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1. 发明授权

US08766343B2 Integrated circuit capacitors having sidewall supports 有权
标题翻译：具有侧壁支撑件的集成电路电容器
公开(公告)号：US08766343B2
公开(公告)日：2014-07-01
申请号：US13356032
申请日：2012-01-23
申请人： Dae-Hyuk Kang , Bo-Un Yoon , Kun-Tack Lee , Woo-Gwan Shim , Ji-Hoon Cha , Im-Soo Park , Hyo-San Lee , Young-Hoo Kim , Jung-Min Oh
发明人： Dae-Hyuk Kang , Bo-Un Yoon , Kun-Tack Lee , Woo-Gwan Shim , Ji-Hoon Cha , Im-Soo Park , Hyo-San Lee , Young-Hoo Kim , Jung-Min Oh
IPC分类号： H01L27/108 , H01L29/94
CPC分类号： H01L28/91 , H01L27/10817 , H01L27/10852 , H01L28/87
摘要： In a method of forming a capacitor, a first mold layer pattern including a first insulating material may be formed on a substrate. The first mold layer pattern may have a trench. A supporting layer including a second insulating material may be formed in the trench. The second insulating material may have an etching selectivity with respect to the first insulating material. A second mold layer may be formed on the first mold layer pattern and the supporting layer pattern. A lower electrode may be formed through the second mold layer and the first mold layer pattern. The lower electrode may make contact with a sidewall of the supporting layer pattern. The first mold layer pattern and the second mold layer may be removed. A dielectric layer and an upper electrode may be formed on the lower electrode and the supporting layer pattern.
摘要翻译：在形成电容器的方法中，可以在基板上形成包括第一绝缘材料的第一模层图案。第一模层图案可以具有沟槽。可以在沟槽中形成包括第二绝缘材料的支撑层。第二绝缘材料可以具有相对于第一绝缘材料的蚀刻选择性。可以在第一模层图案和支撑层图案上形成第二模层。可以通过第二模具层和第一模具层图案形成下部电极。下电极可以与支撑层图案的侧壁接触。可以去除第一模层图案和第二模层。电介质层和上电极可以形成在下电极和支撑层图案上。

2. 发明申请

US20120152898A1 SUBSTRATE PROCESSING METHOD AND SUBSTRATE PROCESSING SYSTEM FOR PERFORMING THE SAME 有权
标题翻译：基板处理方法及其基板处理系统
公开(公告)号：US20120152898A1
公开(公告)日：2012-06-21
申请号：US13314791
申请日：2011-12-08
申请人： YONG JHIN CHO , Kun-Tack LEE , Hyo-San LEE , Young-Hoo KIM , Jung-Won LEE , Sang-Won BAE , Jung-Min OH
发明人： YONG JHIN CHO , Kun-Tack LEE , Hyo-San LEE , Young-Hoo KIM , Jung-Won LEE , Sang-Won BAE , Jung-Min OH
IPC分类号： C23F1/00 , C23F1/08
CPC分类号： H01L21/67023 , B08B7/0021 , H01L21/0206 , H01L21/02104 , H01L21/31111 , H01L22/00 , H01L22/26 , H01L27/10852 , H01L28/90
摘要： In a supercritical fluid method a supercritical fluid is supplied into a process chamber. The supercritical fluid is discharged from the process chamber as a supercritical fluid process proceeds. A concentration of a target material included in the supercritical fluid discharged from the process chamber is detected during the supercritical fluid process. An end point of the supercritical fluid process may be determined based on a detected concentration of the target material.
摘要翻译：在超临界流体法中，将超临界流体供应到处理室中。当超临界流体处理进行时，超临界流体从处理室排出。在超临界流体处理中检测从处理室排出的超临界流体中包含的目标材料的浓度。超临界流体处理的终点可以基于检测到的目标材料的浓度来确定。

3. 发明申请

US20120112317A1 INTEGRATED CIRCUIT CAPACITORS HAVING SIDEWALL SUPPORTS 有权
标题翻译：集成电路电容器具有支持端口
公开(公告)号：US20120112317A1
公开(公告)日：2012-05-10
申请号：US13356032
申请日：2012-01-23
申请人： Dae-Hyuk Kang , Bo-Un Yoon , Kun-Tack Lee , Woo-Gwan Shim , Ji-Hoon Cha , Im-Soo Park , Hyo-San Lee , Young-Hoo Kim , Jung-Min Oh
发明人： Dae-Hyuk Kang , Bo-Un Yoon , Kun-Tack Lee , Woo-Gwan Shim , Ji-Hoon Cha , Im-Soo Park , Hyo-San Lee , Young-Hoo Kim , Jung-Min Oh
IPC分类号： H01L21/02
CPC分类号： H01L28/91 , H01L27/10817 , H01L27/10852 , H01L28/87
摘要： In a method of forming a capacitor, a first mold layer pattern including a first insulating material may be formed on a substrate. The first mold layer pattern may have a trench. A supporting layer including a second insulating material may be formed in the trench. The second insulating material may have an etching selectivity with respect to the first insulating material. A second mold layer may be formed on the first mold layer pattern and the supporting layer pattern. A lower electrode may be formed through the second mold layer and the first mold layer pattern. The lower electrode may make contact with a sidewall of the supporting layer pattern. The first mold layer pattern and the second mold layer may be removed. A dielectric layer and an upper electrode may be formed on the lower electrode and the supporting layer pattern.
摘要翻译：在形成电容器的方法中，可以在基板上形成包括第一绝缘材料的第一模层图案。第一模层图案可以具有沟槽。可以在沟槽中形成包括第二绝缘材料的支撑层。第二绝缘材料可以具有相对于第一绝缘材料的蚀刻选择性。可以在第一模层图案和支撑层图案上形成第二模层。可以通过第二模具层和第一模具层图案形成下部电极。下电极可以与支撑层图案的侧壁接触。可以去除第一模层图案和第二模层。电介质层和上电极可以形成在下电极和支撑层图案上。

4. 发明授权

US08120089B2 Non-volatile memory device and method for fabricating non-volatile memory device 有权
标题翻译：非易失性存储器件和用于制造非易失性存储器件的方法
公开(公告)号：US08120089B2
公开(公告)日：2012-02-21
申请号：US12650076
申请日：2009-12-30
申请人： Young-Hoo Kim , Daehyuk Kang , Youngok Kim , Sang Won Bae , Boun Yoon , Kuntack Lee
发明人： Young-Hoo Kim , Daehyuk Kang , Youngok Kim , Sang Won Bae , Boun Yoon , Kuntack Lee
IPC分类号： H01L29/76
CPC分类号： H01L29/792 , H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L27/11582 , H01L29/7926
摘要： Provided are nonvolatile memory devices with a three-dimensional structure and methods of fabricating the same. The nonvolatile memory device includes conductive patterns three-dimensionally arranged on a semiconductor substrate, semiconductor patterns that extend from the semiconductor substrate and intersect one-side walls of the conductive patterns, charge storage layers interposed between the semiconductor patterns and one-side walls of the conductive patterns, and seed layer patterns interposed between the charge storage layers and one-side walls of the conductive patterns.
摘要翻译：提供具有三维结构的非易失性存储器件及其制造方法。非易失性存储器件包括三维地布置在半导体衬底上的导电图案，半导体图案从半导体衬底延伸并与导电图案的一侧壁相交，插入在半导体图案和半导体图案的一侧壁之间的电荷存储层导电图案和介于电荷存储层和导电图案的单侧壁之间的种子层图案。

5. 发明授权

US07994011B2 Method of manufacturing nonvolatile memory device and nonvolatile memory device manufactured by the method 有权
标题翻译：通过该方法制造非易失性存储器件和非易失性存储器件的制造方法
公开(公告)号：US07994011B2
公开(公告)日：2011-08-09
申请号：US12590614
申请日：2009-11-10
申请人： Imsoo Park , Young-Hoo Kim , Changki Hong , Jaedong Lee , Daehong Eom , Sung-Jun Kim
发明人： Imsoo Park , Young-Hoo Kim , Changki Hong , Jaedong Lee , Daehong Eom , Sung-Jun Kim
IPC分类号： H01L21/336 , H01L29/66
CPC分类号： H01L27/11578 , G11C16/0483 , H01L27/11582 , H01L29/792 , H01L29/7926
摘要： A method of manufacturing a nonvolatile memory device having a three-dimensional memory device includes alternately stacking a plurality of first and second material layers having a different etching selectivity on a semiconductor substrate; forming an opening penetrating the plurality of first and second material layers; removing the first material layers exposed by the opening to form extended portions extending in a direction perpendicular to the semiconductor substrate from the opening; conformally forming a charge storage layer along a surface of the opening and the extended portions; and removing the charge storage layer formed on sidewalls of the second material layers to locally form the charge storage layer patterns in the extended portions.
摘要翻译：一种制造具有三维存储器件的非易失性存储器件的方法包括在半导体衬底上交替堆叠具有不同蚀刻选择性的多个第一和第二材料层; 形成贯穿所述多个第一和第二材料层的开口; 去除由开口暴露的第一材料层，以形成从开口垂直于半导体衬底的方向延伸的延伸部分; 沿着开口和延伸部分的表面保形地形成电荷存储层; 并且去除形成在第二材料层的侧壁上的电荷存储层，以在延伸部分中局部形成电荷存储层图案。

6. 发明申请

US20110073866A1 VERTICAL-TYPE SEMICONDUCTOR DEVICE 有权
标题翻译：垂直型半导体器件
公开(公告)号：US20110073866A1
公开(公告)日：2011-03-31
申请号：US12872270
申请日：2010-08-31
申请人： Young-Hoo Kim , Hyo-San Lee , Sang-Won Bae , Bo-Un Yoon , Kun-Tack Lee
发明人： Young-Hoo Kim , Hyo-San Lee , Sang-Won Bae , Bo-Un Yoon , Kun-Tack Lee
IPC分类号： H01L27/115
CPC分类号： H01L27/11578 , H01L27/11556 , H01L27/11582
摘要： In a vertical-type non-volatile memory device, an insulation layer pattern is provided on a substrate, the insulation layer pattern having a linear shape. Single-crystalline semiconductor patterns are provided on the substrate to make contact with both sidewalls of the insulation layer pattern, the single-crystalline semiconductor patterns having a pillar shape that extends in a vertical direction relative to the substrate. A tunnel oxide layer is provided on the single-crystalline semiconductor pattern. A lower electrode layer pattern is provided on the tunnel oxide layer and on the substrate. A plurality of insulation interlayer patterns is provided on the lower electrode layer pattern, the insulation interlayer patterns being spaced apart from one another by a predetermined distance along the single-crystalline semiconductor pattern. A charge-trapping layer and a blocking dielectric layer are sequentially formed on the tunnel oxide layer between the insulation interlayer patterns. A plurality of control gate patterns is provided on the blocking dielectric layer between the insulation interlayer patterns. An upper electrode layer pattern is provided on the tunnel oxide layer and on the uppermost insulation interlayer pattern.
摘要翻译：在垂直型非易失性存储器件中，在衬底上设置绝缘层图案，绝缘层图案具有直线形状。单晶半导体图案设置在基板上以与绝缘层图案的两个侧壁接触，单晶半导体图案具有相对于基板在垂直方向上延伸的柱状。隧道氧化物层设置在单晶半导体图案上。在隧道氧化物层和衬底上设置下电极层图案。在下电极层图案上设置多个绝缘层间图案，绝缘层间图案沿着单晶半导体图案彼此隔开预定距离。在绝缘层间图案之间的隧道氧化物层上依次形成电荷捕获层和阻挡介质层。在绝缘夹层图案之间的阻挡介质层上设置多个控制栅极图案。在隧道氧化物层和最上层的绝缘层间图案上设置上电极层图案。

7. 发明申请

US20090280641A1 METHOD OF FORMING A CONTACT STRUCTURE 有权
标题翻译：形成接触结构的方法
公开(公告)号：US20090280641A1
公开(公告)日：2009-11-12
申请号：US12437390
申请日：2009-05-07
申请人： Dae-Hyuk Kang , Young-Hoo Kim , Chang-Ki Hong , Kun-Tack Lee , Jae-Dong Lee , Dae-Hong Eom , Jeong-Nam Han
发明人： Dae-Hyuk Kang , Young-Hoo Kim , Chang-Ki Hong , Kun-Tack Lee , Jae-Dong Lee , Dae-Hong Eom , Jeong-Nam Han
IPC分类号： H01L21/3205
CPC分类号： H01L21/76843 , H01L21/28518 , H01L21/76814 , H01L21/76846 , H01L21/76855 , H01L23/485 , H01L27/24 , H01L2924/0002 , H01L2924/09701 , H01L2924/00
摘要： An insulation layer may be formed on an object having a contact region. The insulation layer may be partially etched to form an opening exposing the contact region. A material layer including silicon and oxygen may be formed on the exposed contact region. A metal layer may be formed on the material layer including silicon and oxygen. The material layer including silicon and oxygen may be reacted with the metal layer to form a metal oxide silicide layer at least on the contact region. A conductive layer may be formed on the metal oxide silicide layer to fill up the opening.
摘要翻译：可以在具有接触区域的物体上形成绝缘层。绝缘层可以被部分蚀刻以形成暴露接触区域的开口。可以在暴露的接触区域上形成包括硅和氧的材料层。可以在包括硅和氧的材料层上形成金属层。包括硅和氧的材料层可以与金属层反应，以至少在接触区域上形成金属氧化物硅化物层。可以在金属氧化物硅化物层上形成导电层以填充开口。

8. 发明申请

US20120080061A1 Apparatus For Drying Substrate 审中-公开
标题翻译：干燥基材的设备
公开(公告)号：US20120080061A1
公开(公告)日：2012-04-05
申请号：US13242442
申请日：2011-09-23
申请人： Young-Hoo Kim , Kun-Tack Lee , Seung-Yul Park , Yong-Bum Kwon
发明人： Young-Hoo Kim , Kun-Tack Lee , Seung-Yul Park , Yong-Bum Kwon
IPC分类号： B08B3/10 , B08B11/00 , F26B7/00 , B08B3/02
CPC分类号： H01L21/67034 , F26B5/005 , F26B5/08 , H01L21/02041 , H01L21/02057 , H01L21/67028
摘要： Example embodiments relate to an apparatus for drying a substrate. The apparatus may include a housing including first barrier walls having a first height, a rotary chuck that is disposed within the housing and configured to rotate the substrate, a nozzle system that is disposed above the rotary chuck and configured to supply a fluid onto the substrate, a cleaning liquid supply unit supplying a cleaning liquid for cleaning the substrate to the nozzle system, and a drying liquid supply unit supplying a drying liquid for drying the substrate to the nozzle system.
摘要翻译：示例性实施例涉及用于干燥基底的装置。该装置可以包括壳体，该壳体包括具有第一高度的第一阻挡壁，设置在壳体内并被配置为使基板旋转的旋转卡盘，布置在旋转卡盘上方并构造成将流体供应到基板上的喷嘴系统向所述喷嘴系统供给清洗所述基板的清洗液的清洗液供给单元，以及向所述喷嘴系统供给干燥所述基板的干燥液的干燥液供给单元。

9. 发明申请

US20120064727A1 SUBSTRATE TREATMENT EQUIPMENT AND METHOD OF TREATING SUBSTRATE USING THE SAME 审中-公开
标题翻译：基板处理设备和使用该基板处理基板的方法
公开(公告)号：US20120064727A1
公开(公告)日：2012-03-15
申请号：US13225696
申请日：2011-09-06
申请人： Jung-min Oh , Kun-tack Lee , Hyo-san Lee , Young-hoo Kim , Jung-won Lee , Sang-won Bae , Yong-jhin Cho
发明人： Jung-min Oh , Kun-tack Lee , Hyo-san Lee , Young-hoo Kim , Jung-won Lee , Sang-won Bae , Yong-jhin Cho
IPC分类号： H01L21/306 , B08B3/00
CPC分类号： H01L21/02057 , H01L21/02101 , H01L21/67028 , H01L21/67034 , H01L21/67051 , H01L21/67109 , H01L21/67742 , H01L21/67748
摘要： Substrate treatment equipment includes a wet treatment apparatus for treating a substrate with a solution (liquid), a drying (treatment) apparatus discrete from the wet treatment apparatus and for drying the substrate using a supercritical fluid, and a transfer device. The substrate is extracted by the transfer device from the wet treatment apparatus after the substrate has been treated and the substrate is transferred by the device while wet to the dry treatment apparatus. To this end, various elements/methods may be used to keep the substrate wet or wet the substrate. In any case, the substrate is prevented from drying naturally, i.e., from air-drying, as the substrate is being transferred from the wet treatment apparatus to the drying apparatus. Thus, equipment and method prevent defects such as water spots and the leaning of fine structures on the substrate.
摘要翻译：衬底处理设备包括用溶液（液体）处理衬底的湿处理设备，从湿处理设备离散的干燥（处理）设备，以及使用超临界流体干燥衬底和转移装置。在处理基板之后，通过转移装置从湿处理装置将基板提取出来，并且将基板通过装置湿润地转移到干燥处理装置。为此，可以使用各种元件/方法来使衬底保持湿润或湿润衬底。在任何情况下，当衬底从湿处理设备转移到干燥设备时，防止衬底自然干燥，即从空气干燥。因此，设备和方法可以防止基底上的水斑和精细结构的倾斜等缺陷。

10. 发明申请

US20120064680A1 METHODS OF FORMING A CAPACITOR STRUCTURE AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES USING THE SAME 审中-公开
标题翻译：形成电容器结构的方法和使用其制造半导体器件的方法
公开(公告)号：US20120064680A1
公开(公告)日：2012-03-15
申请号：US13228867
申请日：2011-09-09
申请人： Jung-Min Oh , Bo-Un Yoon , Gyu-Wan Choi , Kun-Tack Lee , Dae-Hyuk Kang , Im-Soo Park , Dong-Seok Lee , Young-Hoo Kim
发明人： Jung-Min Oh , Bo-Un Yoon , Gyu-Wan Choi , Kun-Tack Lee , Dae-Hyuk Kang , Im-Soo Park , Dong-Seok Lee , Young-Hoo Kim
IPC分类号： H01L21/336 , H01G13/06
CPC分类号： H01G13/06
摘要： A method of forming a capacitor structure and manufacturing a semiconductor device, the method of forming a capacitor structure including sequentially forming a first mold layer, a supporting layer, a second mold layer, an anti-bowing layer, and a third mold layer on a substrate having a conductive region thereon; partially removing the third mold layer, the anti-bowing layer, the second mold layer, the supporting layer, and the first mold layer to form a first opening exposing the conductive region; forming a lower electrode on a sidewall and bottom of the first opening, the lower electrode being electrically connected to the conductive region; further removing the third mold layer, the anti-bowing layer, and the second mold layer; partially removing the supporting layer to form a supporting layer pattern; removing the first mold layer; and sequentially forming a dielectric layer and upper electrode on the lower electrode and the supporting layer pattern.
摘要翻译：一种形成电容器结构并制造半导体器件的方法，形成电容器结构的方法包括：依次形成第一模具层，支撑层，第二模具层，抗弯曲层和第三模具层衬底，其上具有导电区域; 部分地去除第三模具层，抗弯曲层，第二模具层，支撑层和第一模具层，以形成暴露导电区域的第一开口; 在所述第一开口的侧壁和底部形成下电极，所述下电极电连接到所述导电区域; 进一步去除第三模具层，抗弯曲层和第二模具层; 部分地去除支撑层以形成支撑层图案; 去除第一模具层; 并且在下电极和支撑层图案上依次形成电介质层和上电极。

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