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1. 发明授权

US08623726B2 Method for filling a physical isolation trench and integrating a vertical channel array with a periphery circuit 有权
标题翻译：用于填充物理隔离沟槽并将垂直沟道阵列与外围电路集成的方法
公开(公告)号：US08623726B2
公开(公告)日：2014-01-07
申请号：US12977910
申请日：2010-12-23
申请人： Yu-Fong Huang , Tzung-Ting Han
发明人： Yu-Fong Huang , Tzung-Ting Han
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , H01L21/76229 , H01L27/11573 , H01L27/11575 , H01L29/7827 , H01L29/7926
摘要： A method of processing a semiconductor structure may include preparing a vertical channel memory structure for filling of a physical isolation trench formed therein. The physical isolation trench may be formed between active structures adjacent to each other and extending in a first direction. The active structures may have channels adjacent to sides of the active structures that are opposite to sides of the active structures that are adjacent to the physical isolation trench. The method may further include filling the physical isolation trench in connection with application of a multi-dielectric layer (ex. an oxide-nitride-oxide (ONO) layer), a polysilicon liner and/or an oxide film. A corresponding apparatus and method for integrating such a structure with a planar periphery are also provided.
摘要翻译：处理半导体结构的方法可以包括制备用于填充其中形成的物理隔离沟槽的垂直沟道存储器结构。物理隔离沟槽可以形成在彼此相邻并在第一方向上延伸的有源结构之间。活性结构可以具有与活性结构的与物理隔离沟槽相邻的与活性结构的侧面相对的相邻的通道。该方法可以进一步包括与应用多电介质层（例如氧化物 - 氮化物 - 氧化物（ONO）层），多晶硅衬垫和/或氧化物膜相结合地填充物理隔离沟槽。还提供了一种用于将这种结构与平面周边集成的相应装置和方法。

2. 发明授权

US08552528B2 Diode-less array for one-time programmable memory 失效
公开(公告)号：US08552528B2
公开(公告)日：2013-10-08
申请号：US13240589
申请日：2011-09-22
申请人： Kuan-Fu Chen , Yin-Jen Chen , Tzung-Ting Han , Ming Shang Chen
发明人： Kuan-Fu Chen , Yin-Jen Chen , Tzung-Ting Han , Ming Shang Chen
IPC分类号： H01L23/52 , H01L29/40 , G11C5/06 , G11C17/00
CPC分类号： G11C17/16 , H01L21/8221 , H01L27/0688 , H01L27/101
摘要： A one-time programmable memory array includes a first row conductor extending in a first row direction and disposed at a first elevation, a second row conductor extending in a second row direction and disposed at a second elevation and a column conductor extending in a column direction and disposed adjacent to the first row conductor and adjacent to the second row conductor. The array also includes a dielectric layer covering at least a portion of the column conductor, a fuse link coupled between the dielectric layer on the column conductor and the second row conductor.

3. 发明授权

US08466508B2 Non-volatile memory structure including stress material between stacked patterns 有权
标题翻译：非易失性存储器结构，包括层叠图案之间的应力材料
公开(公告)号：US08466508B2
公开(公告)日：2013-06-18
申请号：US11866756
申请日：2007-10-03
申请人： Shaw-Hung Ku , Shih-Chin Lee , Chia-Wei Wu , Shang-Wei Lin , Tzung-Ting Han , Ming-Shang Chen , Wen-Pin Lu
发明人： Shaw-Hung Ku , Shih-Chin Lee , Chia-Wei Wu , Shang-Wei Lin , Tzung-Ting Han , Ming-Shang Chen , Wen-Pin Lu
IPC分类号： H01L29/792 , H01L29/788 , H01L21/762
CPC分类号： H01L27/115 , H01L27/11521
摘要： A non-volatile memory structure including a substrate, stacked patterns and stress patterns is provided. The stacked patterns are disposed on the substrate. Each of the stacked patterns includes a charge storage structure and a gate from bottom to top. Here, the charge storage structure at least includes a charge storage layer. The stress patterns are disposed on the substrate between the two adjacent stacked patterns, respectively.
摘要翻译：提供了包括基板，堆叠图案和应力图案的非易失性存储器结构。层叠图案设置在基板上。每个堆叠图案包括电荷存储结构和从底部到顶部的栅极。这里，电荷存储结构至少包括电荷存储层。应力图案分别设置在两个相邻堆叠图案之间的基板上。

4. 发明申请

US20130020624A1 MEMORY STRUCTURE 有权
标题翻译：内存结构
公开(公告)号：US20130020624A1
公开(公告)日：2013-01-24
申请号：US13186095
申请日：2011-07-19
申请人： Yu-Fong Huang , Tzung-Ting Han
发明人： Yu-Fong Huang , Tzung-Ting Han
IPC分类号： H01L29/788
CPC分类号： H01L27/11531 , H01L27/11548
摘要： A memory structure having a memory cell region and a non-memory cell region is provided. The memory structure includes a plurality of memory cells and a conductive material. The plurality of memory cells are disposed in the memory cell region, wherein a plurality of first concave portions are present in the plurality of memory cells. The conductive material extends across the memory cell region and the non-memory cell region, covers the plurality of memory cells, and extends into the plurality of first concave portions.
摘要翻译：提供了具有存储单元区域和非存储单元区域的存储器结构。存储器结构包括多个存储单元和导电材料。多个存储单元设置在存储单元区域中，其中多个第一凹部存在于多个存储单元中。导电材料延伸穿过存储单元区域和非存储单元区域，覆盖多个存储单元，并延伸到多个第一凹入部分中。

5. 发明申请

US20120008363A1 Diode-Less Array for One-Time Programmable Memory 失效
标题翻译：一次性可编程存储器的二极管阵列
公开(公告)号：US20120008363A1
公开(公告)日：2012-01-12
申请号：US13240589
申请日：2011-09-22
申请人： Kuan-Fu Chen , Yin-Jen Chen , Tzung-Ting Han , Ming Shang Chen
发明人： Kuan-Fu Chen , Yin-Jen Chen , Tzung-Ting Han , Ming Shang Chen
IPC分类号： G11C17/16 , G11C17/00
CPC分类号： G11C17/16 , H01L21/8221 , H01L27/0688 , H01L27/101
摘要： A one-time programmable memory array includes a first row conductor extending in a first row direction and disposed at a first elevation, a second row conductor extending in a second row direction and disposed at a second elevation and a column conductor extending in a column direction and disposed adjacent to the first row conductor and adjacent to the second row conductor. The array also includes a dielectric layer covering at least a portion of the column conductor, a fuse link coupled between the dielectric layer on the column conductor and the second row conductor.
摘要翻译：一次可编程存储器阵列包括在第一行方向上延伸并且设置在第一高度的第一行导体，在第二行方向上延伸并设置在第二高度的第二行导体和沿列方向延伸的列导体并且设置成与第一行导体相邻并且与第二行导体相邻。阵列还包括覆盖列导体的至少一部分的电介质层，耦合在列导体上的电介质层和第二行导体之间的熔丝链。

6. 发明授权

US07668010B2 Flash memory having insulating liners between source/drain lines and channels 有权
标题翻译：闪存在源极/漏极线和通道之间具有绝缘衬垫
公开(公告)号：US07668010B2
公开(公告)日：2010-02-23
申请号：US12038612
申请日：2008-02-27
申请人： Shaw Hung Ku , Ten Hao Yeh , Shih Chin Lee , Shang Wei Lin , Chia Wei Wu , Tzung Ting Han , Ming Shang Chen , Wenpin Lu
发明人： Shaw Hung Ku , Ten Hao Yeh , Shih Chin Lee , Shang Wei Lin , Chia Wei Wu , Tzung Ting Han , Ming Shang Chen , Wenpin Lu
IPC分类号： G11C16/00
CPC分类号： H01L27/11568 , H01L2924/0002 , H01L2924/00
摘要： A memory array comprises a semiconductor body having a plurality of trenches aligned generally in parallel. The trenches contain semiconductor material, such as doped amorphous silicon, and act as source/drain lines for the memory array. Insulating liners lie between the semiconductor material within the trenches and the semiconductor body. A plurality of word lines overlie the plurality of trenches and channel regions in the semiconductor body in an array of cross points. Charge trapping structures lie between the word lines and the channel regions at the cross points, providing an array of flash memory cells. The charge trapping structures comprise dielectric charge trapping structures adapted to be programmed and erased to store data. A method for manufacturing such devices includes patterning and forming the sources/drain lines with insulating liners prior to formation of the charge trapping structure over the channel regions.
摘要翻译：存储器阵列包括具有大致平行对准的多个沟槽的半导体本体。沟槽包含诸如掺杂非晶硅的半导体材料，并且用作存储器阵列的源极/漏极线。绝缘衬垫位于沟槽内的半导体材料和半导体本体之间。多个字线以交叉点的阵列覆盖半导体本体中的多个沟槽和沟道区域。电荷捕获结构位于字线和交叉点处的通道区之间，提供闪存单元阵列。电荷捕获结构包括适于编程和擦除以存储数据的介电电荷俘获结构。制造这种器件的方法包括在通道区域上形成电荷俘获结构之前，利用绝缘衬垫图案化和形成源极/漏极线。

7. 发明授权

US07486534B2 Diode-less array for one-time programmable memory 有权
标题翻译：一次可编程存储器的无二极管阵列
公开(公告)号：US07486534B2
公开(公告)日：2009-02-03
申请号：US11297529
申请日：2005-12-08
申请人： Kuan Fu Chen , Yin Jen Chen , Tzung Ting Han , Ming Shang Chen
发明人： Kuan Fu Chen , Yin Jen Chen , Tzung Ting Han , Ming Shang Chen
IPC分类号： G11C17/00
CPC分类号： G11C17/16 , H01L21/8221 , H01L27/0688 , H01L27/101
摘要： A one-time programmable memory array includes a first row conductor extending in a first row direction and disposed at a first elevation, a second row conductor extending in a second row direction and disposed at a second elevation and a column conductor extending in a column direction and disposed adjacent to the first row conductor and adjacent to the second row conductor. The array also includes a dielectric layer covering at least a portion of the column conductor, a fuse link coupled between the dielectric layer on the column conductor and the second row conductor.
摘要翻译：一次可编程存储器阵列包括在第一行方向上延伸并且设置在第一高度的第一行导体，在第二行方向上延伸并设置在第二高度的第二行导体和沿列方向延伸的列导体并且设置成与第一行导体相邻并且与第二行导体相邻。阵列还包括覆盖列导体的至少一部分的电介质层，耦合在列导体上的电介质层和第二行导体之间的熔丝链。

8. 发明申请

US20090011594A1 Methods of Trench and Contact Formation in Memory Cells 有权
标题翻译：记忆细胞中沟槽和接触形成的方法
公开(公告)号：US20090011594A1
公开(公告)日：2009-01-08
申请号：US12211603
申请日：2008-09-16
申请人： Miao-Chih Hsu , Tzung-Ting Han , Ming-Shang Chen
发明人： Miao-Chih Hsu , Tzung-Ting Han , Ming-Shang Chen
IPC分类号： H01L21/768
CPC分类号： H01L21/76838 , H01L27/105 , H01L27/11521 , H01L27/11568
摘要： Methods of contact formation and memory arrays formed using such methods, which methods include providing a substrate having a contacting area; forming a plurality of line-shape structures extending in a first direction; forming a hard mask spacer beside the line-shape structure; forming an insulating material layer above the hard mask spacer; forming a contiguous trench in the insulating material layer extending in a second direction different from the first direction and exposing the contacting area; and forming a conductive line in the trench to contact the contacting area.
摘要翻译：使用这种方法形成的接触形成方法和记忆阵列，该方法包括提供具有接触区域的基底; 形成沿第一方向延伸的多个线状结构; 在线形结构旁边形成硬掩模间隔物; 在硬掩模间隔物上形成绝缘材料层; 在绝缘材料层中形成连续的沟槽，该沟槽沿与第一方向不同的第二方向延伸并暴露接触区域; 以及在所述沟槽中形成导电线以接触所述接触区域。

9. 发明授权

US07067374B2 Manufacturing methods and structures of memory device 有权
标题翻译：存储器件的制造方法和结构
公开(公告)号：US07067374B2
公开(公告)日：2006-06-27
申请号：US10911959
申请日：2004-08-05
申请人： Tzung Ting Han , Yin Jen Chen , Ming Shang Chen
发明人： Tzung Ting Han , Yin Jen Chen , Ming Shang Chen
IPC分类号： H01L21/336
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11534
摘要： Dual spacer structures are fabricated such that sidewall spacers in a cell region are thinner than sidewall spacers in a periphery region. The fabricating method of memory includes forming a stop layer over the first semiconductor feature and the second semiconductor feature in cell region and periphery region. A spacer layer is formed over the stop layer in the periphery region. The spacer layer is patterned to form a spacer on a sidewall of the second semiconductor feature. An etching process is performed to form a resultant spacer on an interior sidewall of the opening between first semiconductor features. The stop layer on top surfaces of the first and second semiconductor features is removed.
摘要翻译：制造双间隔物结构，使得细胞区域中的侧壁间隔物比周边区域中的侧壁间隔物薄。存储器的制造方法包括在单元区域和外围区域中的第一半导体特征和第二半导体特征之上形成停止层。在周边区域中的停止层上形成间隔层。图案化间隔层以在第二半导体特征的侧壁上形成间隔物。执行蚀刻工艺以在第一半导体特征之间的开口的内侧壁上形成合成的间隔物。去除第一和第二半导体特征的顶表面上的停止层。

10. 发明授权

US08890254B2 Airgap structure and method of manufacturing thereof 有权
标题翻译：气隙结构及其制造方法
公开(公告)号：US08890254B2
公开(公告)日：2014-11-18
申请号：US13617643
申请日：2012-09-14
申请人： Yu-Fong Huang , Kun-Mou Chan , Tzung-Ting Han
发明人： Yu-Fong Huang , Kun-Mou Chan , Tzung-Ting Han
IPC分类号： H01L21/70 , H01L29/788 , H01L21/336 , H01L21/3205
CPC分类号： H01L27/11521 , H01L21/764 , H01L21/7682 , H01L27/11524 , H01L27/11568
摘要： A process for fabricating a gate structure, the gate structure having a plurality of gates defined by a network of spaces. The word line (WL) spaces within a dense WL region having airgaps and those spaces outside of the dense WL being substantially free of airgaps. A gate structure having a silicide layer dispose across the plurality of gates is also provided.
摘要翻译：一种用于制造栅极结构的工艺，所述栅极结构具有由空间网络限定的多个栅极。具有气隙的密集WL区域内的字线（WL）空间，密集WL外部的那些空间基本上没有空气隙。还提供了具有跨越多个栅极的硅化物层的栅极结构。

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