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1. 发明申请

US20120273842A1 MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：存储器件及其制造方法
公开(公告)号：US20120273842A1
公开(公告)日：2012-11-01
申请号：US13549272
申请日：2012-07-13
申请人： Chun-Yuan Lo , Cheng-Ming Yih , Wen-Pin Lu
发明人： Chun-Yuan Lo , Cheng-Ming Yih , Wen-Pin Lu
IPC分类号： H01L27/11 , H01L21/8244
CPC分类号： H01L27/11519 , G11C5/005 , G11C5/025 , G11C5/063 , G11C8/14 , H01L27/11565
摘要： A memory array including a plurality of memory cells, a plurality of word lines, a dummy word line, and a plug is provided. Each word line is coupled to corresponding memory cells. A dummy word line is directly adjacent to an outmost word line of the plurality of word lines. The plug is located between the dummy word line and the outmost word line.
摘要翻译：提供了包括多个存储单元，多个字线，虚拟字线和插头的存储器阵列。每个字线耦合到相应的存储单元。虚拟字线与多个字线的最外侧字线直接相邻。插头位于虚拟字线和最外面的字线之间。

2. 发明申请

US20110156102A1 MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：存储器件及其制造方法
公开(公告)号：US20110156102A1
公开(公告)日：2011-06-30
申请号：US13045153
申请日：2011-03-10
申请人： CHUN-YUAN LO , Cheng-Ming Yih , Wen-Pin Lu
发明人： CHUN-YUAN LO , Cheng-Ming Yih , Wen-Pin Lu
IPC分类号： H01L23/52 , H01L21/8239
CPC分类号： H01L27/11519 , G11C5/005 , G11C5/025 , G11C5/063 , G11C8/14 , H01L27/11565
摘要： A memory array including a plurality of memory cells, a plurality of word lines, a dummy word line, at least a first conductive region and at least a first plug is provided. Each word line is coupled to corresponding memory cells. A dummy word line is directly adjacent to an outmost word line of the plurality of word lines. The first conductive region is disposed only between the dummy word line and the outmost word line. The first plug is located between the dummy word line and the outmost word line.
摘要翻译：提供包括多个存储单元，多个字线，虚拟字线，至少第一导电区域和至少第一插头的存储器阵列。每个字线耦合到相应的存储单元。虚拟字线与多个字线的最外侧字线直接相邻。第一导电区域仅设置在虚拟字线和最外侧字线之间。第一个插头位于虚拟字线和最外面的字线之间。

3. 发明授权

US07776690B2 Method of forming a contact on a semiconductor device 有权
标题翻译：在半导体器件上形成接触的方法
公开(公告)号：US07776690B2
公开(公告)日：2010-08-17
申请号：US11691501
申请日：2007-03-27
申请人： Tzung-Ting Han , Ming-Shang Chen , Wen-Pin Lu , Meng-Hsuan Weng
发明人： Tzung-Ting Han , Ming-Shang Chen , Wen-Pin Lu , Meng-Hsuan Weng
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/0207 , H01L27/11521 , H01L27/11568
摘要： A method of forming a contact on a semiconductor device is provided. First, a substrate is provided. A plurality of gate structures defined by a plurality of word lines in a first direction, and a plurality of diffusion regions covered by a first dielectric layer in a second direction are provided over the substrate. The gate structures located underneath the word lines and isolated by the diffusion regions. Then, an etching stop layer is formed. The etching stop layer and the first dielectric layer have different etching selectivity. A second dielectric layer is formed over the substrate. Furthermore, a plurality of contact holes to the diffusion regions between the word lines are formed by using the etching stop layer as a self-aligned mask.
摘要翻译：提供了一种在半导体器件上形成接触的方法。首先，提供基板。由第一方向上的多个字线限定的多个栅极结构和在第二方向上由第一电介质层覆盖的多个扩散区域设置在该基板上。位于字线下方并由扩散区隔离的栅极结构。然后，形成蚀刻停止层。蚀刻停止层和第一介电层具有不同的蚀刻选择性。第二介质层形成在衬底上。此外，通过使用蚀刻停止层作为自对准掩模，形成到字线之间的扩散区域的多个接触孔。

4. 发明申请

US20070297445A1 PROTOCOL TRANSLATING DEVICE AND METHOD 审中-公开
标题翻译：协议翻译设备和方法
公开(公告)号：US20070297445A1
公开(公告)日：2007-12-27
申请号：US11765460
申请日：2007-06-20
申请人： WEN-PIN LU
发明人： WEN-PIN LU
IPC分类号： H04J3/16
CPC分类号： H04L65/1009 , H04L29/06027 , H04L65/1006 , H04L65/103 , H04L65/104 , H04L65/1069 , H04L69/08
摘要： A protocol translating device (20) for protocols translating, includes a protocol parsing module (200), an endpoint management module (210), a call control state machine (220), and a protocol primitive module (230). The protocol parsing module is used for parsing notices, and sending call events corresponding to the notices. The endpoint management module is used for translating the call events to endpoint management call events. The call control state machine is used for receiving the endpoint management call events, retrieving corresponding call states, determining a type of endpoint management digit collected events, and sending a call make according to the corresponding call states and the type of the endpoint management digit collected events. The protocol primitive module is used for determining a type of the call make and sending a protocol call make request to a corresponding protocol sub-module according to the type of the call make.
摘要翻译：用于协议转换的协议翻译设备（20）包括协议解析模块（200），端点管理模块（210），呼叫控制状态机（220）和协议原语模块（230）。协议解析模块用于解析通知，并发送与通知相对应的呼叫事件。端点管理模块用于将呼叫事件转换为端点管理呼叫事件。呼叫控制状态机用于接收端点管理呼叫事件，检索对应的呼叫状态，确定端点管理数字收集事件的类型，以及根据对应的呼叫状态和收集的端点管理数字的类型发送呼叫事件协议原语模块用于根据呼叫的类型确定呼叫的类型，并向对应的协议子模块发送协议呼叫请求。

5. 发明申请

US20070190719A1 METHOD OF FORMING A CONTACT ON A SEMICONDUCTOR DEVICE 有权
标题翻译：在半导体器件上形成接触的方法
公开(公告)号：US20070190719A1
公开(公告)日：2007-08-16
申请号：US11691501
申请日：2007-03-27
申请人： Tzung-Ting Han , Ming-Shang Chen , Wen-Pin Lu , Meng-Hsuan Weng
发明人： Tzung-Ting Han , Ming-Shang Chen , Wen-Pin Lu , Meng-Hsuan Weng
IPC分类号： H01L21/8242
CPC分类号： H01L27/115 , H01L27/0207 , H01L27/11521 , H01L27/11568
摘要： A method of forming a contact on a semiconductor device is provided. First, a substrate is provided. A plurality of gate structures defined by a plurality of word lines in a first direction, and a plurality of diffusion regions covered by a first dielectric layer in a second direction are provided over the substrate. The gate structures located underneath the word lines and isolated by the diffusion regions. Then, an etching stop layer is formed. The etching stop layer and the first dielectric layer have different etching selectivity. A second dielectric layer is formed over the substrate. Furthermore, a plurality of contact holes to the diffusion regions between the word lines are formed by using the etching stop layer as a self-aligned mask.
摘要翻译：提供了一种在半导体器件上形成接触的方法。首先，提供基板。由第一方向上的多个字线限定的多个栅极结构和在第二方向上由第一电介质层覆盖的多个扩散区域设置在该基板上。位于字线下方并由扩散区隔离的栅极结构。然后，形成蚀刻停止层。蚀刻停止层和第一介电层具有不同的蚀刻选择性。第二介质层形成在衬底上。此外，通过使用蚀刻停止层作为自对准掩模，形成到字线之间的扩散区域的多个接触孔。

6. 发明授权

US07214983B2 Non-volatile memory and fabricating method thereof 有权
标题翻译：非易失性存储器及其制造方法
公开(公告)号：US07214983B2
公开(公告)日：2007-05-08
申请号：US10904703
申请日：2004-11-24
申请人： Tzung-Ting Han , Ming-Shang Chen , Wen-Pin Lu , Meng-Hsuan Weng
发明人： Tzung-Ting Han , Ming-Shang Chen , Wen-Pin Lu , Meng-Hsuan Weng
IPC分类号： H01L29/792
CPC分类号： H01L27/115 , H01L27/0207 , H01L27/11521 , H01L27/11568
摘要： A method of fabricating a non-volatile memory is provided. A plurality of stack gate strips is formed on a substrate and a plurality of source/drain regions is formed in the substrate beside the stack gate strips. A plurality of dielectric strips is formed on the source/drain regions. A plurality of word lines is formed on the stack gate strips and the dielectric strips. Thereafter, the stack gate strips exposed by the word lines are removed to form a plurality of openings. A plurality of spacers is formed on the sidewalls of the openings and the word lines. A dielectric layer is formed over the substrate. A plurality of contacts is formed in the dielectric layer and the dielectric strips between two adjacent word lines.
摘要翻译：提供了一种制造非易失性存储器的方法。在基板上形成多个堆叠栅极条，并且在堆叠栅极条旁边的基板上形成多个源极/漏极区域。在源/漏区上形成多个介质条。多个字线形成在堆叠栅极条和介质条上。此后，除去由字线露出的堆叠栅极条以形成多个开口。在开口和字线的侧壁上形成多个间隔物。介电层形成在衬底上。在电介质层和两个相邻字线之间的介质条形成多个触点。

7. 发明授权

US07157360B2 Memory device and method for forming a passivation layer thereon 有权
标题翻译：用于在其上形成钝化层的存储器件和方法
公开(公告)号：US07157360B2
公开(公告)日：2007-01-02
申请号：US10671773
申请日：2003-09-29
申请人： Hung-Yu Chiu , U-Way Tseng , Wen-Pin Lu , Cheng-Chen Huseh , Pei-Ren Jeng , Fu-Hsiang Hsu
发明人： Hung-Yu Chiu , U-Way Tseng , Wen-Pin Lu , Cheng-Chen Huseh , Pei-Ren Jeng , Fu-Hsiang Hsu
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L23/3192 , H01L23/291 , H01L2924/0002 , Y10S438/954 , H01L2924/00
摘要： A memory device with an improved passivation structure. The memory device includes a semiconductor substrate with memory units thereon, an interconnect structure over the surface of the semiconductor substrate to connect with the memory units, and a passivation structure over the surface of the interconnect structure. The passivation structure comprises a dielectric layer over the surface of the interconnect structure and a silicon-oxy-nitride (SiOxNy) layer over the surface of the dielectric layer.
摘要翻译：具有改善的钝化结构的存储器件。存储器件包括其上具有存储器单元的半导体衬底，在半导体衬底的表面上的与存储器单元连接的互连结构，以及在互连结构的表面上的钝化结构。钝化结构包括在互连结构的表面上的电介质层和介电层表面上的氧 - 氮化硅（SiOxNy）层。

8. 发明授权

US07116606B2 Method and circuit of plasma damage protection 有权
标题翻译：等离子体损伤保护的方法和电路
公开(公告)号：US07116606B2
公开(公告)日：2006-10-03
申请号：US11034945
申请日：2005-01-14
申请人： Ming-Hung Chou , Wen-Pin Lu
发明人： Ming-Hung Chou , Wen-Pin Lu
IPC分类号： G11C11/06
CPC分类号： H01L27/0266
摘要： A protection circuit to discharge plasma-induced charges in a semiconductor device or integrated circuit includes a PMOS transistor and a diode. The PMOS transistor includes a substrate, a drain, a source, and a gate, the source being coupled to receive the plasma-induced charges. The diode has a positive terminal coupled to the substrate of the PMOS transistor and a negative terminal coupled the gate of the PMOS transistor.
摘要翻译：用于在半导体器件或集成电路中放电等离子体感应电荷的保护电路包括PMOS晶体管和二极管。 PMOS晶体管包括衬底，漏极，源极和栅极，源极被耦合以接收等离子体感应的电荷。二极管具有耦合到PMOS晶体管的衬底的正极端子和耦合PMOS晶体管的栅极的负极端子。

9. 发明申请

US20060157744A1 Method and circuit of plasma damage protection 有权
公开(公告)号：US20060157744A1
公开(公告)日：2006-07-20
申请号：US11034945
申请日：2005-01-14
申请人： Ming-Hung Chou , Wen-Pin Lu
发明人： Ming-Hung Chou , Wen-Pin Lu
IPC分类号： H01L29/768
CPC分类号： H01L27/0266
摘要： A protection circuit to discharge plasma-induced charges in a semiconductor device or integrated circuit includes a PMOS transistor and a diode. The PMOS transistor includes a substrate, a drain, a source, and a gate, the source being coupled to receive the plasma-induced charges. The diode has a positive terminal coupled to the substrate of the PMOS transistor and a negative terminal coupled the gate of the PMOS transistor.

10. 发明授权

US07012004B2 Method of manufacturing a nonvolatile memory cell with triple spacers and the structure thereof 有权
公开(公告)号：US07012004B2
公开(公告)日：2006-03-14
申请号：US11128402
申请日：2005-05-13
申请人： U-Way Tseng , Hung-Yu Chiu , Wen-Pin Lu , Pao-Ling Hwang
发明人： U-Way Tseng , Hung-Yu Chiu , Wen-Pin Lu , Pao-Ling Hwang
IPC分类号： H01L21/8247
CPC分类号： H01L29/42324 , H01L29/6656 , H01L29/7881
摘要： A method of manufacturing a nonvolatile memory cell with triple spacers and the structure thereof. A gate structure is formed on a substrate. Diffusion regions are formed in the substrate on either side of the gate structure. A linear oxide layer is formed on the gate structure and the substrate. A conformal nitride layer is formed on the linear oxide layer. The nitride layer and the linear oxide layer are partially etched back to form linear oxide spacers on the sides of the gate structure and nitride spacers on the sides of the linear oxide spacers. A conformal oxide layer is formed on the linear oxide spacers, the nitride spacers, the gate structure and the substrate. The oxide layer is partially etched back to form oxide spacers on the sides of the nitride spacers.

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