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1. 发明申请

US20080299741A1 Etching solution, method of surface modification of semiconductor substrate and method of forming shallow trench isolation 有权
标题翻译：蚀刻溶液，半导体衬底的表面改性方法和形成浅沟槽隔离的方法
公开(公告)号：US20080299741A1
公开(公告)日：2008-12-04
申请号：US11806186
申请日：2007-05-30
申请人： Chia-Wei Wu , Jung-Yu Shieh , Ling-Wu Yang
发明人： Chia-Wei Wu , Jung-Yu Shieh , Ling-Wu Yang
IPC分类号： H01L21/762 , C09K13/08 , H01L21/31
CPC分类号： H01L21/30604 , C09K13/08 , H01L21/30608 , H01L21/76232
摘要： An etching solution, a method of surface modification of a semiconductor substrate and a method of forming shallow trench isolation are provided. The etching solution is used for surface modifying the semiconductor substrate. The etching solution includes an oxidant and an oxide remover. The semiconductor substrate is oxidized to a semiconductor oxide by the oxidant, and the oxide remover subtracts the semiconductor oxide.
摘要翻译：提供蚀刻溶液，半导体衬底的表面改性方法和形成浅沟槽隔离的方法。蚀刻溶液用于表面改性半导体衬底。蚀刻溶液包括氧化剂和氧化物去除剂。半导体衬底被氧化剂氧化成半导体氧化物，并且氧化物去除器减去半导体氧化物。

2. 发明授权

US08211806B2 Method of fabricating integrated circuit with small pitch 有权
标题翻译：制造小间距集成电路的方法
公开(公告)号：US08211806B2
公开(公告)日：2012-07-03
申请号：US11846900
申请日：2007-08-29
申请人： Chia-Wei Wu , Ling-Wu Yang
发明人： Chia-Wei Wu , Ling-Wu Yang
IPC分类号： H01L21/302
CPC分类号： H01L21/76816 , H01L21/0337 , H01L21/0338 , H01L21/31144
摘要： A method of manufacturing an integrated circuit with a small pitch comprises providing a second material layer patterned to form at least two features with an opening between the features. The second material layer is formed over a first material layer and the first material layer is over a substrate. The method also comprises providing a first oxide layer to form a first sidewall surrounding each of the features, and providing a second oxide layer over the first sidewalls and the first material layer. A second sidewall is formed surrounding each of the features. The method further comprises providing a conductive layer over the second oxide layer and removing the conductive layer, the second sidewalls and the first material underneath the second sidewalls.
摘要翻译：制造具有小间距的集成电路的方法包括提供图案化以形成具有特征之间的开口的至少两个特征的第二材料层。第二材料层形成在第一材料层上并且第一材料层在衬底之上。该方法还包括提供第一氧化物层以形成围绕每个特征的第一侧壁，以及在第一侧壁和第一材料层之上提供第二氧化物层。形成围绕每个特征的第二侧壁。该方法还包括在第二氧化物层上提供导电层，并移除第二侧壁下方的导电层，第二侧壁和第一材料。

3. 发明授权

US07776713B2 Etching solution, method of surface modification of semiconductor substrate and method of forming shallow trench isolation 有权
标题翻译：蚀刻溶液，半导体衬底的表面改性方法和形成浅沟槽隔离的方法
公开(公告)号：US07776713B2
公开(公告)日：2010-08-17
申请号：US11806186
申请日：2007-05-30
申请人： Chia-Wei Wu , Jung-Yu Shieh , Ling-Wu Yang
发明人： Chia-Wei Wu , Jung-Yu Shieh , Ling-Wu Yang
IPC分类号： H01L21/465
CPC分类号： H01L21/30604 , C09K13/08 , H01L21/30608 , H01L21/76232
摘要： An etching solution, a method of surface modification of a semiconductor substrate and a method of forming shallow trench isolation are provided. The etching solution is used for surface modifying the semiconductor substrate. The etching solution includes an oxidant and an oxide remover. The semiconductor substrate is oxidized to a semiconductor oxide by the oxidant, and the oxide remover subtracts the semiconductor oxide.
摘要翻译：提供蚀刻溶液，半导体衬底的表面改性方法和形成浅沟槽隔离的方法。蚀刻溶液用于表面改性半导体衬底。蚀刻溶液包括氧化剂和氧化物去除剂。半导体衬底被氧化剂氧化成半导体氧化物，并且氧化物去除器减去半导体氧化物。

4. 发明授权

US08791022B2 Method for reducing wordline bridge rate 有权
标题翻译：减少字桥桥接率的方法
公开(公告)号：US08791022B2
公开(公告)日：2014-07-29
申请号：US12952902
申请日：2010-11-23
申请人： Jeng-Hwa Liao , Jung-Yu Shieh , Ling-Wu Yang
发明人： Jeng-Hwa Liao , Jung-Yu Shieh , Ling-Wu Yang
IPC分类号： H01L21/311
CPC分类号： H01L21/32134 , H01L21/28282 , H01L21/32139 , H01L27/11568
摘要： The method of forming a wordline is provided in the present invention. The proposed method includes steps of: (a) etching a metal-silicide layer and a POLY layer via a hard mask, wherein the metal-silicide layer is disposed on the POLY layer; (b) forming a POLY recess in the POLY layer; and (c) forming a liner film covering the metal-silicide layer.
摘要翻译：在本发明中提供了形成字线的方法。所提出的方法包括以下步骤：（a）通过硬掩模蚀刻金属硅化物层和POLY层，其中金属硅化物层设置在POLY层上; （b）在POLY层中形成POLY凹槽; 和（c）形成覆盖金属硅化物层的衬里膜。

5. 发明授权

US08106483B2 Wafer with improved intrinsic gettering ability 失效
标题翻译：晶圆具有改善的内在吸气能力
公开(公告)号：US08106483B2
公开(公告)日：2012-01-31
申请号：US13074780
申请日：2011-03-29
申请人： Chun-Ling Chiang , Jung-Yu Hsieh , Ling-Wu Yang
发明人： Chun-Ling Chiang , Jung-Yu Hsieh , Ling-Wu Yang
IPC分类号： H01L29/30 , H01L29/207 , H01L29/227 , H01L29/167
CPC分类号： H01L21/3225
摘要： An integrated circuit with improved intrinsic gettering ability is described, having a bulk micro-defect (BMD) density of 3.85×105-3.38×109/cm3 through first and second annealing steps. The first annealing step is performed at a first temperature in an atmosphere containing at least one of oxygen gas and nitrogen gas. The second annealing step is performed at a second temperature higher than the first temperature in the atmosphere.
摘要翻译：描述了具有改善的内在吸气能力的集成电路，通过第一和第二退火步骤具有3.85×10 5 -3.38×10 9 / cm 3的体积微缺陷（BMD）密度。第一退火步骤在包含氧气和氮气中的至少一种的气氛中的第一温度下进行。第二退火步骤在高于大气中的第一温度的第二温度下进行。

6. 发明申请

US20090108331A1 Memory and manufacturing method thereof 有权
标题翻译：其记忆及其制造方法
公开(公告)号：US20090108331A1
公开(公告)日：2009-04-30
申请号：US11979101
申请日：2007-10-31
申请人： Erh-Kun Lai , Yen-Hao Shih , Ling-Wu Yang , Chun-Min Cheng
发明人： Erh-Kun Lai , Yen-Hao Shih , Ling-Wu Yang , Chun-Min Cheng
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L21/28282 , H01L27/11568 , H01L29/66545 , H01L29/66583 , H01L29/7923
摘要： A memory having isolated dual memory cells is provided. A first isolation wall and a second isolation wall are separately disposed between a source and a drain on a substrate. An isolation bottom layer and a polysilicon layer are orderly disposed on the substrate between the first and the second isolation walls. A first charge storage structure and a first gate are orderly disposed on the substrate between the first isolation wall and the source. A second charge storage structure and a second gate are orderly disposed on the substrate between the second isolation wall and the drain. A word line disposed on the polysilicon layer, the first gate, the second gate, the first isolation wall and the second isolation wall is electrically connected to the first gate, the second gate and the polysilicon layer.
摘要翻译：提供具有隔离双存储单元的存储器。第一隔离壁和第二隔离壁分别设置在基板上的源极和漏极之间。隔离底层和多晶硅层有序地设置在第一和第二隔离壁之间的衬底上。第一电荷存储结构和第一栅极有序地设置在第一隔离壁和源极之间的衬底上。第二电荷存储结构和第二栅极有序地设置在第二隔离壁和漏极之间的衬底上。布置在多晶硅层上的字线，第一栅极，第二栅极，第一隔离壁和第二隔离壁电连接到第一栅极，第二栅极和多晶硅层。

7. 发明授权

US08329480B2 Test pattern for detecting piping in a memory array 有权
标题翻译：用于检测存储器阵列中管道的测试模式
公开(公告)号：US08329480B2
公开(公告)日：2012-12-11
申请号：US12892479
申请日：2010-09-28
申请人： Che-Lun Hung , Hsiang-Chou Liao , Tuung Luoh , Ling-Wu Yang
发明人： Che-Lun Hung , Hsiang-Chou Liao , Tuung Luoh , Ling-Wu Yang
IPC分类号： G01R31/26
CPC分类号： G11C29/56 , G11C29/006
摘要： A method of detecting manufacturing defects at a memory array may include disposing an active area of a first width in communication with a first conductive member of the memory array to define a grounded conductive member, disposing an isolation structure of a second width in communication with a second conductive member of the memory array to define a floating conductive member, and providing an alternating arrangement of floating and grounded conductive members including arranging a plurality of the grounded and floating conductive members adjacent to each other to define a sequence of alternating floating and grounded conductive members. A corresponding test device is also provided.
摘要翻译：检测存储器阵列中的制造缺陷的方法可以包括将与存储器阵列的第一导电构件连通的第一宽度的有源区域设置为限定接地导电构件，将与第二宽度的隔离结构存储器阵列的第二导电构件以限定浮动导电构件，以及提供浮动和接地导电构件的交替布置，包括布置彼此相邻的多个接地和浮动导电构件，以限定一系列交替的浮动和接地导电会员还提供了相应的测试装置。

8. 发明授权

US08288280B2 Conductor removal process 有权
标题翻译：导体去除过程
公开(公告)号：US08288280B2
公开(公告)日：2012-10-16
申请号：US11780024
申请日：2007-07-19
申请人： Yung-Tai Hung , Chin-Tsan Yeh , Chin-Ta Su , Ling-Wu Yang , Tung-Han Chuang
发明人： Yung-Tai Hung , Chin-Tsan Yeh , Chin-Ta Su , Ling-Wu Yang , Tung-Han Chuang
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/3212 , H01L21/32105
摘要： A conductor removal process is described, which is applied to a substrate that has thereon a plurality of patterns and a blanket conductor layer covering the patterns. An upper portion of the blanket conductor layer entirely over the patterns is oxidized to form a dielectric layer. A CMP step is performed to remove the dielectric layer and a portion of the remaining conductor layer in turn and thereby expose the patterns.
摘要翻译：描述了导体去除工艺，其应用于其上具有多个图案的基板和覆盖图案的覆盖层导体层。橡皮布导体层的整个图案上方的上部被氧化以形成电介质层。执行CMP步骤以依次去除电介质层和剩余导体层的一部分，从而暴露图案。

9. 发明申请

US20100178758A1 METHODS FOR FABRICATING DIELECTRIC LAYER AND NON-VOLATILE MEMORY 审中-公开
标题翻译：用于制造介电层和非易失性存储器的方法
公开(公告)号：US20100178758A1
公开(公告)日：2010-07-15
申请号：US12354602
申请日：2009-01-15
申请人： Jeng-Hwa Liao , Jung-Yu Hsieh , Ling-Wu Yang
发明人： Jeng-Hwa Liao , Jung-Yu Hsieh , Ling-Wu Yang
IPC分类号： H01L21/443 , H01L21/28
CPC分类号： H01L21/28202 , H01L21/0214 , H01L21/02211 , H01L21/02271 , H01L21/3145 , H01L29/40117
摘要： The method for fabricating the dielectric layer of the present invention is described as follows. A substrate is provided in a chamber, wherein the chamber is a single-wafer LPCVD chamber. A silicon source gas, an oxidation source gas and a nitridation source gas are then introduced into the chamber, wherein a volumetric flow rate ratio of the oxidation source gas to a total amount of the oxidation source gas and the nitridation source gas is varied within a range of 0.0245 to 0.375. Afterwards, the dielectric layer with a dielectric constant within a range of 4.8 to 7.6 is formed on the substrate.
摘要翻译：本发明的电介质层的制造方法如下所述。衬底设置在腔室中，其中腔室是单晶片LPCVD室。然后将硅源气体，氧化源气体和氮化源气体引入室中，其中氧化源气体与氧化源气体和氮化源气体的总量的体积流量比在范围为0.0245至0.375。之后，在基板上形成介电常数为4.8〜7.6的介质层。

10. 发明授权

US07625819B2 Interconnection process 有权
标题翻译：互连过程
公开(公告)号：US07625819B2
公开(公告)日：2009-12-01
申请号：US11806541
申请日：2007-06-01
申请人： Tuung Luoh , Ling-Wu Yang , Chin-Ta Su , Ta-Hung Yang , Kuang-Chao Chen
发明人： Tuung Luoh , Ling-Wu Yang , Chin-Ta Su , Ta-Hung Yang , Kuang-Chao Chen
IPC分类号： H01L21/44 , H01L21/4763
CPC分类号： H01L21/76814 , H01L21/28518 , H01L21/76828
摘要： An interconnection process is provided. The process includes the following steps. Firstly, a semiconductor base having at least a electrical conductive region is provided. Next, a dielectric layer with a contact hole is formed to cover the semiconductor base, wherein the contact hole exposes part of the electrical conductive region. Then, a thermal process is performed on the semiconductor base covered with the dielectric layer. Lastly, a conductive layer is formed on the dielectric layer, wherein the conductive layer is electrically connected to the electrical conductive region through the contact hole.
摘要翻译：提供互连过程。该过程包括以下步骤。首先，设置至少具有导电区域的半导体基板。接下来，形成具有接触孔的电介质层以覆盖半导体基底，其中接触孔暴露部分导电区域。然后，对覆盖有电介质层的半导体基板进行热处理。最后，在电介质层上形成导电层，其中导电层通过接触孔与导电区电连接。

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