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1. 发明授权

US08822287B2 Methods of manufacturing semiconductor devices 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08822287B2
公开(公告)日：2014-09-02
申请号：US13313754
申请日：2011-12-07
申请人： Hyo-Jung Kim , Ki-hyun Hwang , Kyung-Hyun Kim , Han-Mei Choi , Dong-Chul Yoo , Chan-Jin Park , Jong-Heun Lim , Myung-Jung Pyo , Byoung-Moon Yoon , Chang-Sup Mun
发明人： Hyo-Jung Kim , Ki-hyun Hwang , Kyung-Hyun Kim , Han-Mei Choi , Dong-Chul Yoo , Chan-Jin Park , Jong-Heun Lim , Myung-Jung Pyo , Byoung-Moon Yoon , Chang-Sup Mun
IPC分类号： H01L21/336
CPC分类号： H01L21/31053 , H01L21/3212 , H01L27/11573 , H01L27/11575 , H01L27/11582
摘要： Methods of manufacturing semiconductor devices include forming an integrated structure and a first stopping layer pattern in a first region. A first insulating interlayer and a second stopping layer are formed. A second preliminary insulating interlayer is formed by partially etching the second stopping layer and the first insulating interlayer in the first region. A first polishing is performed to remove a protruding portion. A second polishing is performed to expose the first and second stopping layer patterns.
摘要翻译：制造半导体器件的方法包括在第一区域中形成集成结构和第一停止层图案。形成第一绝缘层和第二阻挡层。通过部分蚀刻第一区域中的第二阻挡层和第一绝缘中间层来形成第二初步绝缘中间层。执行第一次抛光以去除突出部分。执行第二抛光以暴露第一和第二停止层图案。

2. 发明授权

US08765551B2 Non-volatile memory device having vertical structure and method of manufacturing the same 有权
标题翻译：具有垂直结构的非易失性存储器件及其制造方法
公开(公告)号：US08765551B2
公开(公告)日：2014-07-01
申请号：US13729856
申请日：2012-12-28
申请人： Jun-youl Yang , Dae-hong Eom , Byoung-moon Yoon , Kyung-hyun Kim , Se-ho Cha
发明人： Jun-youl Yang , Dae-hong Eom , Byoung-moon Yoon , Kyung-hyun Kim , Se-ho Cha
IPC分类号： H01L21/336
CPC分类号： H01L29/7827 , H01L21/28282 , H01L27/1157 , H01L27/11582 , H01L29/7926
摘要： According to an example embodiment, a non-volatile memory device includes a semiconductor layer pattern on a substrate, a plurality of gate patterns and a plurality of interlayer insulating layer patterns that are alternately stacked along a side wall of the semiconductor layer pattern, and a storage structure between the plurality of gate patterns and the semiconductor layer pattern. The semiconductor layer pattern extends in a vertical direction from the substrate. The gate patterns are recessed in a direction from a side wall of the interlayer insulating layer patterns opposing the side wall of the semiconductor layer pattern. A recessed surface of the gate patterns may be formed to be vertical to a surface of the substrate.
摘要翻译：根据示例性实施例，非易失性存储器件包括在衬底上的半导体层图案，沿着半导体层图案的侧壁交替层叠的多个栅极图案和多个层间绝缘层图案，以及多个栅极图案与半导体层图案之间的存储结构。半导体层图案从衬底沿垂直方向延伸。栅极图案沿着与半导体层图案的侧壁相对的层间绝缘层图案的侧壁的方向凹陷。栅极图案的凹陷表面可以形成为垂直于衬底的表面。

3. 发明授权

US08664101B2 Multiple mold structure methods of manufacturing vertical memory devices 有权
标题翻译：制造垂直存储器件的多种模具结构方法
公开(公告)号：US08664101B2
公开(公告)日：2014-03-04
申请号：US13596621
申请日：2012-08-28
申请人： Hyo-Jung Kim , Dae-Hong Eom , Jong-Heun Lim , Myung-Jung Pyo , Byoung-Moon Yoon , Kyung-Hyun Kim
发明人： Hyo-Jung Kim , Dae-Hong Eom , Jong-Heun Lim , Myung-Jung Pyo , Byoung-Moon Yoon , Kyung-Hyun Kim
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L27/11582 , H01L27/11573 , H01L29/7926
摘要： A first insulating interlayer is formed on a substrate including first and second regions. The first insulating interlayer has top surface, a height of which is greater in the first region than in the second region. A first planarization stop layer and a second insulating interlayer are formed. The second insulating interlayer is planarized until the first planarization stop layer is exposed. The first planarization stop layer and the first and second insulating interlayers in the second region are removed to expose the substrate. A lower mold structure including first insulation layer patterns, first sacrificial layer patterns and a second planarization stop layer pattern is formed. The first insulation layer patterns and the first sacrificial layer patterns are alternately and repeatedly formed on the substrate, and a second planarization stop layer pattern is formed on the first insulation layer pattern.
摘要翻译：在包括第一和第二区域的基板上形成第一绝缘中间层。第一绝缘中间层具有顶表面，其高度在第一区域中大于在第二区域中的高度。形成第一平坦化停止层和第二绝缘夹层。平面化第二绝缘层，直到第一平坦化停止层露出。去除第二区域中的第一平坦化停止层和第一和第二绝缘夹层以露出衬底。形成包括第一绝缘层图案，第一牺牲层图案和第二平坦化停止层图案的下模具结构。第一绝缘层图案和第一牺牲层图案在基板上交替重复地形成，并且在第一绝缘层图案上形成第二平坦化停止层图案。

4. 发明申请

US20130171788A1 NON-VOLATILE MEMORY DEVICE HAVING VERTICAL STRUCTURE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：具有垂直结构的非易失性存储器件及其制造方法
公开(公告)号：US20130171788A1
公开(公告)日：2013-07-04
申请号：US13729856
申请日：2012-12-28
申请人： Jun-youl YANG , Dae-hong EOM , Byoung-moon YOON , Kyung-hyun KIM , Se-ho CHA
发明人： Jun-youl YANG , Dae-hong EOM , Byoung-moon YOON , Kyung-hyun KIM , Se-ho CHA
IPC分类号： H01L29/78
CPC分类号： H01L29/7827 , H01L21/28282 , H01L27/1157 , H01L27/11582 , H01L29/7926
摘要： According to an example embodiment, a non-volatile memory device includes a semiconductor layer pattern on a substrate, a plurality of gate patterns and a plurality of interlayer insulating layer patterns that are alternately stacked along a side wall of the semiconductor layer pattern, and a storage structure between the plurality of gate patterns and the semiconductor layer pattern. The semiconductor layer pattern extends in a vertical direction from the substrate. The gate patterns are recessed in a direction from a side wall of the interlayer insulating layer patterns opposing the side wall of the semiconductor layer pattern. A recessed surface of the gate patterns may be formed to be vertical to a surface of the substrate.
摘要翻译：根据示例性实施例，非易失性存储器件包括在衬底上的半导体层图案，沿着半导体层图案的侧壁交替层叠的多个栅极图案和多个层间绝缘层图案，以及多个栅极图案与半导体层图案之间的存储结构。半导体层图案从衬底沿垂直方向延伸。栅极图案沿着与半导体层图案的侧壁相对的层间绝缘层图案的侧壁的方向凹陷。栅极图案的凹陷表面可以形成为垂直于衬底的表面。

5. 发明申请

US20120149185A1 Methods Of Manufacturing Semiconductor Devices 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20120149185A1
公开(公告)日：2012-06-14
申请号：US13313754
申请日：2011-12-07
申请人： Hyo-Jung Kim , Ki-Hyun Hwang , Kyung-Hyun Kim , Han-Mei Choi , Dong-Chul Yoo , Chan-Jin Park , Jong-Heun Lim , Myung-Jung Pyo , Byoung-Moon Yoon , Chang-Sup Mun
发明人： Hyo-Jung Kim , Ki-Hyun Hwang , Kyung-Hyun Kim , Han-Mei Choi , Dong-Chul Yoo , Chan-Jin Park , Jong-Heun Lim , Myung-Jung Pyo , Byoung-Moon Yoon , Chang-Sup Mun
IPC分类号： H01L21/3205 , H01L21/311
CPC分类号： H01L21/31053 , H01L21/3212 , H01L27/11573 , H01L27/11575 , H01L27/11582
摘要： Methods of manufacturing semiconductor devices include forming an integrated structure and a first stopping layer pattern in a first region. A first insulating interlayer and a second stopping layer are formed. A second preliminary insulating interlayer is formed by partially etching the second stopping layer and the first insulating interlayer in the first region. A first polishing is performed to remove a protruding portion. A second polishing is performed to expose the first and second stopping layer patterns.
摘要翻译：制造半导体器件的方法包括在第一区域中形成集成结构和第一停止层图案。形成第一绝缘层和第二阻挡层。通过部分蚀刻第一区域中的第二阻挡层和第一绝缘中间层来形成第二初步绝缘中间层。执行第一次抛光以去除突出部分。执行第二抛光以暴露第一和第二停止层图案。

6. 发明授权

US08039372B2 Methods of manufacturing variable resistance non-volatile memory devices including a uniformly narrow contact layer 有权
标题翻译：制造包括均匀窄接触层的可变电阻非易失性存储器件的方法
公开(公告)号：US08039372B2
公开(公告)日：2011-10-18
申请号：US11829556
申请日：2007-07-27
申请人： Chung-Ki Min , Tae-Eun Kim , Byoung-Moon Yoon
发明人： Chung-Ki Min , Tae-Eun Kim , Byoung-Moon Yoon
IPC分类号： H01L21/62
CPC分类号： H01L45/144 , H01L27/2409 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/143 , H01L45/1675
摘要： A phase changeable memory device is manufactured by forming at least one insulating layer on a substrate. A preliminary first electrode is formed on the insulating layer. The preliminary first electrode is partially etched to form a first electrode electrically connected to the substrate. After the preliminary first electrode is formed, both sidewalls of the preliminary first electrode are partially etched isotropically to form a first electrode having a uniform width and height. A phase changeable material layer pattern and a second electrode are subsequently formed on the first electrode. Related devices also are described.
摘要翻译：通过在基板上形成至少一个绝缘层来制造相变存储器件。在绝缘层上形成初步的第一电极。部分蚀刻预备的第一电极以形成电连接到衬底的第一电极。在初步第一电极形成之后，预成型第一电极的两个侧壁被各向同性地部分蚀刻以形成具有均匀宽度和高度的第一电极。随后在第一电极上形成相变材料层图案和第二电极。还描述了相关设备。

7. 发明申请

US20100210068A1 Method of forming phase change memory device 审中-公开
标题翻译：形成相变存储器件的方法
公开(公告)号：US20100210068A1
公开(公告)日：2010-08-19
申请号：US12591772
申请日：2009-12-01
申请人： Won-jun Lee , Jin-woo Park , Byoung-moon Yoon , Cheol-woo Park
发明人： Won-jun Lee , Jin-woo Park , Byoung-moon Yoon , Cheol-woo Park
IPC分类号： H01L21/06
CPC分类号： H01L45/143 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1675
摘要： Provided is a method of forming a phase change memory device, the method including washing and rinsing a phase change device structure. A phase change material layer may be formed on a semiconductor substrate. The phase change material layer may be etched so as to form a phase change device structure. The semiconductor substrate on which the phase change device structure is formed may be washed using a washing solution including a reducing agent containing fluorine (F), a pH controller, a dissolution agent and water. In addition, the semiconductor substrate on which the washing is performed may be rinsed.
摘要翻译：提供一种形成相变存储器件的方法，该方法包括洗涤和漂洗相变装置结构。相变材料层可以形成在半导体衬底上。相变材料层可以被蚀刻以形成相变器件结构。可以使用包含含氟还原剂（F），pH控制剂，溶解剂和水的洗涤溶液洗涤其上形成相变器件结构的半导体衬底。此外，可以冲洗其上进行洗涤的半导体衬底。

8. 发明授权

US07582559B2 Method of manufacturing a semiconductor device having voids in a polysilicon layer 有权
标题翻译：制造在多晶硅层中具有空隙的半导体器件的方法
公开(公告)号：US07582559B2
公开(公告)日：2009-09-01
申请号：US11249515
申请日：2005-10-14
申请人： In-Joon Yeo , Won-Jun Lee , Tae-Hyun Kim , Ji-Hong Kim , Byoung-Moon Yoon
发明人： In-Joon Yeo , Won-Jun Lee , Tae-Hyun Kim , Ji-Hong Kim , Byoung-Moon Yoon
IPC分类号： H01L21/4763
CPC分类号： H01L27/11521 , H01L27/115
摘要： A method of manufacturing a semiconductor device includes forming an insulation pattern over a substrate. The insulation pattern has at least one opening that exposes a surface of the substrate. Then, a first polysilicon layer is formed over the substrates such that the first polysilicon layer fills the opening. The first polysilicon layer also includes a void therein. An upper portion of the first polysilicon layer is removed such that void expands to a recess and the recess is exposed. A second polysilicon layer is formed over the substrate such that the second polysilicon layer fills the recess.
摘要翻译：制造半导体器件的方法包括在衬底上形成绝缘图案。绝缘图案具有暴露基板表面的至少一个开口。然后，在基板上形成第一多晶硅层，使得第一多晶硅层填充开口。第一多晶硅层还包括空隙。去除第一多晶硅层的上部，使得空隙膨胀到凹部并且凹部暴露。第二多晶硅层形成在衬底上，使得第二多晶硅层填充凹部。

9. 发明授权

US07579284B2 Etching solution, method of forming a pattern using the same, method of manufacturing a multiple gate oxide layer using the same and method of manufacturing a flash memory device using the same 失效
标题翻译：蚀刻溶液，使用其形成图案的方法，使用该方法制造多栅极氧化物层的方法以及使用其制造闪存器件的方法
公开(公告)号：US07579284B2
公开(公告)日：2009-08-25
申请号：US11482773
申请日：2006-07-10
申请人： Byoung-Moon Yoon , Ji-Hong Kim , Yong-Sun Ko , Kyung-Hyun Kim
发明人： Byoung-Moon Yoon , Ji-Hong Kim , Yong-Sun Ko , Kyung-Hyun Kim
IPC分类号： H01L21/311
CPC分类号： C09K13/04 , H01L21/32134
摘要： Example embodiments of the present invention relate to an etching solution, a method of forming a pattern using the same, a method of manufacturing a multiple gate oxide layer using the same and a method of manufacturing a flash memory device using the same. Other example embodiments of the present invention relate to an etching solution having an etching selectivity between a polysilicon layer and an oxide layer, a method of forming a pattern using an etching solution using the same, a method of manufacturing a multiple gate oxide layer using the same, and a method of manufacturing a flash memory device using the same. An etching solution including hydrogen peroxide (H2O2) and ammonium hydroxide (NH4OH) by a volume ratio of about 1:2 to about 1:10 mixed in water. In a method of forming a pattern and methods of manufacturing a multiple gate oxide layer and a flash memory device, a polysilicon layer may be formed on a substrate. An insulation layer pattern including an opening exposing the polysilicon layer may be formed on the polysilicon layer. The polysilicon layer exposed by the insulation layer pattern may be etched using the etching solution. A polysilicon layer pattern may be formed on the substrate using the etching solution.
摘要翻译：本发明的示例性实施例涉及一种蚀刻溶液，使用该方法形成图案的方法，使用该蚀刻溶液的多栅极氧化物层的制造方法以及使用其制造闪存器件的方法。本发明的其它示例性实施例涉及在多晶硅层和氧化物层之间具有蚀刻选择性的蚀刻溶液，使用其使用蚀刻溶液形成图案的方法，使用该栅极氧化物层的方法以及使用其制造闪存器件的方法。包含在水中混合的体积比为约1:2至约1:10的过氧化氢（H 2 O 2）和氢氧化铵（NH 4 OH）的蚀刻溶液。在形成图案的方法和制造多栅极氧化物层和闪存器件的方法中，可以在衬底上形成多晶硅层。可以在多晶硅层上形成包括露出多晶硅层的开口的绝缘层图案。可以使用蚀刻溶液蚀刻由绝缘层图案暴露的多晶硅层。可以使用蚀刻溶液在衬底上形成多晶硅层图案。

10. 发明授权

US07151043B2 Method of manufacturing a semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US07151043B2
公开(公告)日：2006-12-19
申请号：US11082616
申请日：2005-03-17
申请人： Tae-hyun Kim , Byoung-moon Yoon , Won-jun Lee , Yong-sun Ko , Kyung-hyun Kim
发明人： Tae-hyun Kim , Byoung-moon Yoon , Won-jun Lee , Yong-sun Ko , Kyung-hyun Kim
IPC分类号： H01L21/76
CPC分类号： H01L27/11521 , H01L21/76224 , H01L27/115
摘要： Methods of manufacturing a semiconductor device are provided. A trench is formed in a semiconductor substrate. A first field oxide layer is formed that partially fills the trench. The first field oxide layer defines an active region of the substrate that is adjacent to the trench. An upper portion of sidewalls of the trench extends upward beyond a surface of the first field oxide layer. A first liner is formed on the first field oxide layer and on the portion of the sidewalls of the trench that extend upward beyond the first field oxide layer. A second field oxide layer is formed on the first liner and fills the trench. The second field oxide layer and the first liner are each partially removed to expose a top adjacent surface and upper sidewalls of the trench along the active region of the substrate. A dielectric layer is formed on the exposed top adjacent surface and upper sidewalls of the trench. A gate electrode is formed on the dielectric layer.
摘要翻译：提供制造半导体器件的方法。在半导体衬底中形成沟槽。形成部分填充沟槽的第一场氧化物层。第一场氧化物层限定与沟槽相邻的衬底的有源区。沟槽的侧壁的上部向上延伸超过第一场氧化物层的表面。第一衬垫形成在第一场氧化物层上并且在沟槽的侧壁的部分上方向上延伸超过第一场氧化物层。在第一衬垫上形成第二场氧化物层并填充沟槽。每个部分去除第二场氧化物层和第一衬里以沿着衬底的有源区域暴露沟槽的顶部相邻表面和上侧壁。介电层形成在沟槽的暴露的顶部相邻表面和上侧壁上。在电介质层上形成栅电极。

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