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1. 发明申请

US20090081563A1 Integrated Circuits and Methods of Design and Manufacture Thereof 有权
标题翻译：集成电路及其设计和制造方法
公开(公告)号：US20090081563A1
公开(公告)日：2009-03-26
申请号：US12126741
申请日：2008-05-23
申请人： Helen Wang , Scott D. Halle , Henning Haffner , Haoren Zhuang , Klaus Herold , Matthew E. Colburn , Allen H. Gabor , Zachary Baum , Scott M. Mansfield , Jason E. Meiring
发明人： Helen Wang , Scott D. Halle , Henning Haffner , Haoren Zhuang , Klaus Herold , Matthew E. Colburn , Allen H. Gabor , Zachary Baum , Scott M. Mansfield , Jason E. Meiring
IPC分类号： G03F1/14 , G03F7/26
CPC分类号： H01L21/32139 , G03F1/36 , G03F1/70 , H01L21/0274 , H01L21/28123 , H01L21/823437 , Y10S438/942
摘要： Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes depositing a gate material over a semiconductor substrate, and depositing a first resist layer over the gate material. A first mask is used to pattern the first resist layer to form first and second resist features. The first resist features include pattern for gate lines of the semiconductor device and the second resist features include printing assist features. A second mask is used to form a resist template; the second mask removes the second resist features.
摘要翻译：公开了集成电路及其制造和设计方法。例如，制造方法包括在半导体衬底上沉积栅极材料，并且在栅极材料上沉积第一抗蚀剂层。使用第一掩模来图案化第一抗蚀剂层以形成第一和第二抗蚀剂特征。第一抗蚀剂特征包括半导体器件的栅极线的图案，第二抗蚀剂特征包括印刷辅助特征。使用第二掩模形成抗蚀剂模板; 第二掩模移除第二抗蚀剂特征。

2. 发明授权

US08039203B2 Integrated circuits and methods of design and manufacture thereof 有权
标题翻译：集成电路及其设计和制造方法
公开(公告)号：US08039203B2
公开(公告)日：2011-10-18
申请号：US12126741
申请日：2008-05-23
申请人： Helen Wang , Scott D. Halle , Henning Haffner , Haoren Zhuang , Klaus Herold , Matthew E. Colburn , Allen H. Gabor , Zachary Baum , Scott M. Mansfield , Jason E. Meiring
发明人： Helen Wang , Scott D. Halle , Henning Haffner , Haoren Zhuang , Klaus Herold , Matthew E. Colburn , Allen H. Gabor , Zachary Baum , Scott M. Mansfield , Jason E. Meiring
IPC分类号： H01L21/027
CPC分类号： H01L21/32139 , G03F1/36 , G03F1/70 , H01L21/0274 , H01L21/28123 , H01L21/823437 , Y10S438/942
摘要： Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes depositing a gate material over a semiconductor substrate, and depositing a first resist layer over the gate material. A first mask is used to pattern the first resist layer to form first and second resist features. The first resist features include pattern for gate lines of the semiconductor device and the second resist features include printing assist features. A second mask is used to form a resist template; the second mask removes the second resist features.
摘要翻译：公开了集成电路及其制造和设计方法。例如，制造方法包括在半导体衬底上沉积栅极材料，并且在栅极材料上沉积第一抗蚀剂层。使用第一掩模来图案化第一抗蚀剂层以形成第一和第二抗蚀剂特征。第一抗蚀剂特征包括半导体器件的栅极线的图案，第二抗蚀剂特征包括印刷辅助特征。使用第二掩模形成抗蚀剂模板; 第二掩模移除第二抗蚀剂特征。

3. 发明授权

US08507346B2 Method of forming a semiconductor device having a cut-way hole to expose a portion of a hardmask layer 有权
标题翻译：形成具有切割孔以暴露硬掩模层的一部分的半导体器件的方法
公开(公告)号：US08507346B2
公开(公告)日：2013-08-13
申请号：US12949148
申请日：2010-11-18
申请人： Martin Burkhardt , Matthew E. Colburn , Allen H. Gabor , Oleg Gluschenkov , Scott D. Halle , Howard S. Landis , Helen Wang
发明人： Martin Burkhardt , Matthew E. Colburn , Allen H. Gabor , Oleg Gluschenkov , Scott D. Halle , Howard S. Landis , Helen Wang
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/84 , H01L21/338 , H01L21/3205 , H01L21/4763 , H01L21/311 , H01L21/302 , H01L21/461
CPC分类号： H01L29/78 , H01L21/28123 , H01L21/32139 , H01L22/12 , H01L22/26
摘要： A method of forming a semiconductor device having a substrate, an active region and an inactive region includes: forming a hardmask layer over the substrate; transferring a first pattern into the hardmask layer in the active region of the semiconductor device; forming one or more fills in the inactive region; forming a cut-away hole within, covering, or partially covering, the one or more fills to expose a portion of the hardmask layer, the exposed portion being within the one or more fills; and exposing the hardmask layer to an etchant to divide the first pattern into a second pattern including at least two separate elements.
摘要翻译：一种形成具有衬底，有源区和非活性区的半导体器件的方法包括：在衬底上形成硬掩模层; 将第一图案转移到半导体器件的有源区中的硬掩模层中; 在非活性区域中形成一个或多个填充物; 在所述一个或多个填充物内部，覆盖或部分地覆盖所述硬掩模层的一部分以暴露所述硬掩模层的一部分内的切除孔，所述暴露部分在所述一个或多个填充物内; 以及将所述硬掩模层暴露于蚀刻剂以将所述第一图案划分成包括至少两个分离元件的第二图案。

4. 发明申请

US20120126294A1 WAFER FILL PATTERNS AND USES 有权
标题翻译： WAFER FILL PATTERNS和用途
公开(公告)号：US20120126294A1
公开(公告)日：2012-05-24
申请号：US12949148
申请日：2010-11-18
申请人： Martin Burkhardt , Matthew E. Colburn , Allen H. Gabor , Oleg Gluschenkov , Scott D. Halle , Howard S. Landis , Helen Wang
发明人： Martin Burkhardt , Matthew E. Colburn , Allen H. Gabor , Oleg Gluschenkov , Scott D. Halle , Howard S. Landis , Helen Wang
IPC分类号： H01L29/78 , H01L21/28 , H01L29/06 , H01L21/302
CPC分类号： H01L29/78 , H01L21/28123 , H01L21/32139 , H01L22/12 , H01L22/26
摘要： A method of forming a semiconductor device having a substrate, an active region and an inactive region includes: forming a hardmask layer over the substrate; transferring a first pattern into the hardmask layer in the active region of the semiconductor device; forming one or more fills in the inactive region; forming a cut-away hole within, covering, or partially covering, the one or more fills to expose a portion of the hardmask layer, the exposed portion being within the one or more fills; and exposing the hardmask layer to an etchant to divide the first pattern into a second pattern including at least two separate elements.
摘要翻译：一种形成具有衬底，有源区和非活性区的半导体器件的方法包括：在衬底上形成硬掩模层; 将第一图案转移到半导体器件的有源区中的硬掩模层中; 在非活性区域中形成一个或多个填充物; 在所述一个或多个填充物内部，覆盖或部分地覆盖所述硬掩模层的一部分以暴露所述硬掩模层的一部分内的切除孔，所述暴露部分在所述一个或多个填充物内; 以及将所述硬掩模层暴露于蚀刻剂以将所述第一图案划分成包括至少两个分离元件的第二图案。

5. 发明授权

US07993815B2 Line ends forming 有权
标题翻译：线端成型
公开(公告)号：US07993815B2
公开(公告)日：2011-08-09
申请号：US11853353
申请日：2007-09-11
申请人： Matthew E. Colburn , Allen H. Gabor , Scott D. Halle , Donald J. Samuels
发明人： Matthew E. Colburn , Allen H. Gabor , Scott D. Halle , Donald J. Samuels
IPC分类号： H01L21/8229
CPC分类号： G11C11/412 , H01L27/0207 , H01L27/105 , H01L27/1052 , H01L27/11 , H01L27/115
摘要： Methods of forming line ends and a related memory cell including the line ends are disclosed. In one embodiment, the method includes forming a first device element and a second device element separated from the first device element by a space; and forming a first line extending from the first device element, the first line including a bulbous line end over the space and distanced from the first device element, and a second line extending from the second device element, the second line including a bulbous line end over the space and distanced from the second device element.
摘要翻译：公开了形成线端的方法和包括线端的相关存储单元。在一个实施例中，该方法包括通过空间形成与第一器件元件分离的第一器件元件和第二器件元件; 以及形成从所述第一装置元件延伸的第一线，所述第一线包括在所述空间上并与所述第一装置元件间隔开的球形线端，以及从所述第二装置元件延伸的第二线，所述第二线包括球根线端并且与第二设备元件分开。

6. 发明申请

US20090065956A1 MEMORY CELL 审中-公开
标题翻译：记忆体
公开(公告)号：US20090065956A1
公开(公告)日：2009-03-12
申请号：US11853358
申请日：2007-09-11
申请人： Matthew E. Colburn , Allen H. Gabor , Scott D. Halle , Donald J. Samuels
发明人： Matthew E. Colburn , Allen H. Gabor , Scott D. Halle , Donald J. Samuels
IPC分类号： H01L23/48
CPC分类号： G11C5/063 , H01L27/0207 , H01L27/105 , H01L27/1052 , H01L27/11 , H01L27/115
摘要： Methods of forming line ends and a related memory cell including the line ends are disclosed. In one embodiment, the memory cell includes fa first device having a first conductive line extending over a first active region and having a first line end of the first conductive line positioned over an isolation region adjacent to the first active region; and a second device having a second conductive line extending over one of a second active region and a contact element and having a second line end of the second conductive line positioned over the isolation region adjacent to the one of the second active region and the contact element, wherein the first line end and the second line end each include a bulbous end that is distanced from a respective active region or contact element.
摘要翻译：公开了形成线端的方法和包括线端的相关存储单元。在一个实施例中，存储单元包括fa第一器件，其具有在第一有源区上延伸的第一导线，并且第一导线的第一线端位于与第一有源区相邻的隔离区上; 以及第二装置，具有延伸到第二有源区和接触元件之一上的第二导线，并且第二导线的第二线端位于与第二有源区和接触元件中的一个相邻的隔离区上方，其中所述第一线端和所述第二线端各自包括与相应的有源区域或接触元件间隔开的球状端。

7. 发明申请

US20090068837A1 LINE ENDS FORMING 有权
标题翻译：线端形成
公开(公告)号：US20090068837A1
公开(公告)日：2009-03-12
申请号：US11853353
申请日：2007-09-11
申请人： Matthew E. Colburn , Allen H. Gabor , Scott D. Halle , Donald J. Samuels
发明人： Matthew E. Colburn , Allen H. Gabor , Scott D. Halle , Donald J. Samuels
IPC分类号： H01L21/44
CPC分类号： G11C11/412 , H01L27/0207 , H01L27/105 , H01L27/1052 , H01L27/11 , H01L27/115
摘要： Methods of forming line ends and a related memory cell including the line ends are disclosed. In one embodiment, the method includes forming a first device element and a second device element separated from the first device element by a space; and forming a first line extending from the first device element, the first line including a bulbous line end over the space and distanced from the first device element, and a second line extending from the second device element, the second line including a bulbous line end over the space and distanced from the second device element.
摘要翻译：公开了形成线端的方法和包括线端的相关存储单元。在一个实施例中，该方法包括通过空间形成与第一器件元件分离的第一器件元件和第二器件元件; 以及形成从所述第一装置元件延伸的第一线，所述第一线包括在所述空间上并与所述第一装置元件间隔开的球形线端，以及从所述第二装置元件延伸的第二线，所述第二线包括球根线端并且与第二设备元件分开。

8. 发明申请

US20120089953A1 MASK LAYOUT FORMATION 有权
标题翻译：掩蔽布局形成
公开(公告)号：US20120089953A1
公开(公告)日：2012-04-12
申请号：US12901595
申请日：2010-10-11
申请人： Zachary Baum , Scott D. Halle , Henning Haffner
发明人： Zachary Baum , Scott D. Halle , Henning Haffner
IPC分类号： G06F17/50
CPC分类号： G03F1/30 , G03F1/0069
摘要： A method for mask layout formation including forming a plurality of phase shapes on either side of a critical feature of a design layout of an integrated circuit chip having a plurality of critical features, wherein each phase shape has an edge; identifying a plurality of transition edges from the edges, wherein each transition edge is parallel to a critical feature; identifying a transition space defined by one of a group including two transition edges, wherein the space is external to all phase shapes, and one transition edge, wherein the space is external to all phase shapes; forming a transition polygon by closing each transition space with at least one closing edge, wherein each closing edge is perpendicular to the plurality of transition edges; transforming each transition polygon into a printing assist feature; and forming a first mask layout or a second mask layout from the printing assist features and the critical features.
摘要翻译：一种用于掩模布局形成的方法，包括在具有多个关键特征的集成电路芯片的设计布局的关键特征的任一侧上形成多个相位形状，其中每个相位形状具有边缘; 从边缘识别多个过渡边缘，其中每个过渡边缘平行于关键特征; 识别由包括两个过渡边缘的组之一限定的过渡空间，其中所述空间在所有相位形状外部，以及一个过渡边缘，其中所述空间在所有相位形状外部; 通过用至少一个闭合边缘闭合每个过渡空间来形成过渡多边形，其中每个闭合边缘垂直于多个过渡边缘; 将每个过渡多边形变换为打印辅助特征; 以及从打印辅助特征和关键特征形成第一掩模布局或第二掩模布局。

9. 发明授权

US08875063B2 Mask layout formation 有权
标题翻译：面膜布局形成
公开(公告)号：US08875063B2
公开(公告)日：2014-10-28
申请号：US12901595
申请日：2010-10-11
申请人： Zachary Baum , Scott D. Halle , Henning Haffner
发明人： Zachary Baum , Scott D. Halle , Henning Haffner
IPC分类号： G06F17/50 , G03F1/00 , G03F1/30
CPC分类号： G03F1/30 , G03F1/0069
摘要： A method for forming a mask layout is described. A plurality of phase shapes are formed on either side of a critical feature of a design layout of an intergrated circuit chip having a plurality of critical features. A plurality of transition edges are identified from the edges of each phase shape. Each transition edge is parallel to critical feature. A transition space is identified as defined by one of the group including two transition edges and one transition edge. A transition polygon is formed by closing each transition space with at least one closing edge. Each transition polygon is transformed into a printing assist feature. A mask layout is formed from the printing assist features and critical features.
摘要翻译：描述了形成掩模布局的方法。在具有多个关键特征的集成电路芯片的设计布局的关键特征的任一侧上形成多个相位形状。从每个相位形状的边缘识别多个过渡边缘。每个过渡边缘与关键特征平行。识别由包括两个过渡边缘和一个过渡边缘的组之一所定义的过渡空间。通过用至少一个关闭边缘关闭每个过渡空间来形成过渡多边形。每个过渡多边形被转换成打印辅助功能。从打印辅助功能和关键特征形成面罩布局。

10. 发明申请

US20080305623A1 Semiconductor device manufacturing methods 有权
标题翻译：半导体器件制造方法
公开(公告)号：US20080305623A1
公开(公告)日：2008-12-11
申请号：US11810810
申请日：2007-06-07
申请人： Haoren Zhuang , Helen Wang , Len Yuan Tsou , Scott D. Halle
发明人： Haoren Zhuang , Helen Wang , Len Yuan Tsou , Scott D. Halle
IPC分类号： H01L21/8244
CPC分类号： H01L27/11 , H01L27/0207
摘要： Methods for manufacturing semiconductor devices are disclosed. In a preferred embodiment, a method of processing a semiconductor device includes providing a workpiece, the workpiece comprising a material layer to be patterned disposed thereon. A hard mask is formed over the material layer. A first pattern is formed in the hard mask and an upper portion of the material layer using a first etch process. A second pattern is formed in the hard mask and the upper portion of the material layer using a second etch process, the second pattern being different than the first pattern. The first pattern and the second pattern are formed in a lower portion of the material layer using a third etch process and using the hard mask as a mask.
摘要翻译：公开了制造半导体器件的方法。在优选实施例中，处理半导体器件的方法包括提供工件，所述工件包括待设置在其上的图案的材料层。在材料层上形成硬掩模。使用第一蚀刻工艺在硬掩模和材料层的上部形成第一图案。使用第二蚀刻工艺在硬掩模和材料层的上部形成第二图案，第二图案不同于第一图案。第一图案和第二图案使用第三蚀刻工艺形成在材料层的下部，并使用硬掩模作为掩模。

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