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    • 81. 发明授权
      US4784969A Method of manufacturing a semiconductor memory device 失效
    • Method of manufacturing a semiconductor memory device
    • 制造半导体存储器件的方法
    • US4784969A
    • 1988-11-15
    • US43444
    • 1987-04-28
    • Akihiro Nitayama
    • Akihiro Nitayama
    • H01L27/10 , G11C11/403 , H01L21/8242 , H01L27/108 , H01L21/385 , H01L21/425 , H01L29/94
    • H01L27/10861
    • A method of manufacturing a semiconductor memory apparatus comprising a memory cell structure consisting of a transistor and capacitor. The method comprises the steps of forming a groove in the capacitor-forming region of a semiconductor substrate, forming a capacitor insulating film on the surface of the semiconductor substrate, including the inner surface of the groove, providing first and second contact holes in the capacitor insulating film, forming a first conductive film over the entire surface of thus produced structure, patterning the first conductive material, thereby providing a capacitor electrode covering the inner surface of the groove and first contact hole, and an interconnection electrode covering the second contact hole, forming a first interlayer insulating film over the surfaces of the capacitor electrode and interconnection electrode, forming a gate insulating film on that portion of the surface of the semiconductor substrate which lies between the capacitor electrode and interconnection electrode, forming a second conductive film over the entire surface of thus produced structure, and back-etching the second conductive film, to form a gate electrode on the gate insulating film which lies between the capacitor electrode and interconnection electrode.
    • 一种制造半导体存储装置的方法，包括由晶体管和电容器组成的存储单元结构。 该方法包括以下步骤：在半导体衬底的电容器形成区域中形成沟槽，在半导体衬底的表面上形成电容器绝缘膜，包括沟槽的内表面，在电容器中提供第一和第二接触孔 绝缘膜，在由此制造的结构的整个表面上形成第一导电膜，构图第一导电材料，从而提供覆盖凹槽内表面的电容器电极和第一接触孔，以及覆盖第二接触孔的互连电极， 在电容器电极和互连电极的表面上形成第一层间绝缘膜，在半导体衬底的位于电容器电极和互连电极之间的部分表面上形成栅极绝缘膜，在整个电容器电极和互连电极之间形成第二导电膜 由此产生的结构的表面和背蚀刻 第二导电膜，在位于电容器电极和互连电极之间的栅极绝缘膜上形成栅电极。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 82. 发明授权
      US4780426A Method for manufacturing high-breakdown voltage semiconductor device 失效
    • Method for manufacturing high-breakdown voltage semiconductor device
    • 高耐压半导体器件的制造方法
    • US4780426A
    • 1988-10-25
    • US101026
    • 1987-09-24
    • Yutaka Koshino , Yoshiro Baba , Jiro Ohshima
    • Yutaka Koshino , Yoshiro Baba , Jiro Ohshima
    • H01L21/033 , H01L21/22 , H01L21/225 , H01L21/331 , H01L29/06 , H01L29/10 , H01L29/73 , H01L21/385 , H01L21/425
    • H01L29/6625 , H01L21/033 , H01L21/22 , H01L21/2253 , H01L29/0615 , H01L29/1004
    • A first silicon oxide film is formed on the major surface of an n-type silicon substrate. A silicon nitride film is formed on the first silicon oxide film. The first silicon oxide film and the silicon nitride film are selectively etched to form an opening. Boron ions are implanted into the silicon substrate using the first silicon oxide film and the silicon nitride film as a mask. A second silicon oxide film is formed on the silicon substrate exposed by the opening. Gallium ions are implanted into the second silicon oxide film using the silicon nitride film as a mask. Boron and gallium ions are simultaneously diffused in the silicon substrate. In this case, a diffusion rate of gallium in the silicon substrate is higher than that of boron in the silicon substrate, and the diffusion rate of gallium in the silicon oxide film is higher than that in the silicon substrate. Therefore, a p-type second layer is formed in the substrate to surround a p.sup.+ -type first layer in a self-aligned manner.
    • 在n型硅衬底的主表面上形成第一氧化硅膜。 在第一氧化硅膜上形成氮化硅膜。 选择性地蚀刻第一氧化硅膜和氮化硅膜以形成开口。 使用第一氧化硅膜和氮化硅膜作为掩模将硼离子注入到硅衬底中。 在由开口暴露的硅衬底上形成第二氧化硅膜。 使用氮化硅膜作为掩模将镓离子注入到第二氧化硅膜中。 硼和镓离子同时扩散到硅衬底中。 在这种情况下，硅衬底中镓的扩散速率高于硅衬底中的硼的扩散速率，并且硅氧化膜中镓的扩散速率高于硅衬底中的扩散速率。 因此，在衬底中形成p型第二层，以自对准的方式包围p +型第一层。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 84. 发明授权
      US4694565A Method of making hardened CMOS sub-micron field effect transistors 失效
    • Method of making hardened CMOS sub-micron field effect transistors
    • 制造硬化CMOS亚微米场效应晶体管的方法
    • US4694565A
    • 1987-09-22
    • US856304
    • 1986-04-28
    • Frank Z. Custode
    • Frank Z. Custode
    • H01L21/762 , H01L21/8238 , H01L21/385 , H01L21/425
    • H01L21/762 , H01L21/823871 , Y10S438/953
    • The invention provides a novel high speed hardened CMOS structure and process for developing the structure. In a first embodiment, the surface of the silicon wafer is preserved intact by building the field oxide above this surface so there is no transition from the plane to the plane. In a first embodiment, one of the gate electrode overlaps is avoided, thereby eliminating the sidewalk effect or parasitic device from causing leakage on that side of the channel. The preferred embodiment provides a device with no field oxide extending into the silicon wafer and with no overlap of the gate electrode over the field oxide. This is achieved by causing the gate metal interconnect to proceed linearly along the active region over either the source or drain before it leaves the active region, thereby avoiding the establishing of an extra field in the gate region. An alternative method for accomplishing the foregoing is to provide double metal layers and allow the gate metal interconnect to leave the active area directly from the gate electrode because the spacing is sufficient to render the metal interconnect field ineffective to cause parasitic problems; also, in this embodiment the metal interconnect can be run linearly along the active region and depart the same over the source or drain thereby even decreasing gate capacitance effects. A method for establishing sub-micron contacts is disclosed which permits manufacture of the CMOS devices to sub-micron dimensions.
    • 本发明提供了一种用于开发结构的新型高速硬化CMOS结构和工艺。 在第一实施例中，通过在该表面上建立场氧化物，硅晶片的<100>表面保持完整，因此不存在从<100>平面到<111>平面的转变。 在第一实施例中，避免了栅电极重叠中的一个，从而消除了人行道效应或寄生装置在通道的该侧上的泄漏。 优选实施例提供一种没有场氧化物的器件延伸到硅晶片中，并且在场氧化物上没有栅电极的重叠。 这是通过使栅极金属互连在离开有源区之前在源极或漏极上沿着有源区线性地进行，从而避免在栅极区域中建立额外的场。 实现上述目的的替代方法是提供双金属层，并允许栅极金属互连直接从栅电极离开有源区，因为间隔足以使金属互连场无效以引起寄生问题; 此外，在该实施例中，金属互连可以沿有源区线性地运行并且在源极或漏极上偏离，从而甚至降低栅极电容效应。 公开了一种用于建立亚微米接触的方法，其允许将CMOS器件制造成亚微米尺寸。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 86. 发明授权
      US4504334A Gettering method for mercury cadmium telluride 失效
    • Gettering method for mercury cadmium telluride
    • 碲化汞吸附方法
    • US4504334A
    • 1985-03-12
    • US564872
    • 1983-12-23
    • Herbert F. Schaake , John H. Tregilgas , Jeffrey D. Beck
    • Herbert F. Schaake , John H. Tregilgas , Jeffrey D. Beck
    • H01L21/477 , H01L21/324 , H01L21/385
    • H01L21/477
    • The disclosure relates to a method for removing the unwanted impurities from an HgCdTe alloy which consists of the steps of depositing a thin film on the order of from about 1 to about 100 microns in thickness of tellurium onto the backside of a mercury cadmium telluride bar to insure the presence of a substantial amount of excess tellurium on the backside of the alloy bar and allow the gettering mechanism to work. A protective film to shield the tellurium film from mercury ambient atmosphere is then optionally placed over the tellurium film. The protective film can be formed of a silicon oxide such as SiO and is preferably in the range of about 1000 angstroms to 10 microns or more in thickness. The bar with the tellurium and protective film thereon is then annealed at a temperature of less than 450.degree. C., preferably about 280.degree. C., for a period of from about one day to about four weeks in a saturated mercury atmosphere to allow the impurities in the alloy to diffuse to the backside thereof and into the tellurium layer. The bulk of the impurities will travel into the tellurium layer within a matter of several days at the preferred temperature noted hereinabove. The tellurium layer and protective film are then removed such as by grinding, etching or other appropriate method to remove the impurities from the alloy bar.
    • 本公开涉及一种从HgCdTe合金中除去不需要的杂质的方法，该方法包括以下步骤：将碲厚度约1至约100微米的薄膜沉积到碲化汞镉池的背面上， 确保在合金棒的背面存在大量过量的碲，并允许吸气机构工作。 然后任选地将碲膜从汞环境大气屏蔽的保护膜放置在碲膜上。 保护膜可以由诸如SiO的氧化硅形成，并且优选在约1000埃到10微米或更大的范围内。 然后将其上具有碲和保护膜的棒在饱和汞气氛中在小于450℃，优选约280℃的温度下退火约1天至约4周的时间，以使 合金中的杂质扩散到其背面并进入碲层。 在上述优选温度下，大部分杂质将在数天内进入碲层。 然后通过研磨，蚀刻或其它适当的方法除去碲层和保护膜以从合金棒中除去杂质。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
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