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81. 发明授权

US08895977B2 Thin film transistor and method of forming the same 有权
标题翻译：薄膜晶体管及其形成方法
公开(公告)号：US08895977B2
公开(公告)日：2014-11-25
申请号：US13673195
申请日：2012-11-09
申请人： Samsung Display Co., Ltd.
发明人： Doo Hyoung Lee , Bo Sung Kim , Chan Woo Yang , Seung-Ho Jung , Yeon Taek Jeong , June Whan Choi , Tae-Young Choi
IPC分类号： H01L21/786 , H01L29/786 , H01L21/385
CPC分类号： H01L29/66969 , H01L21/02565 , H01L21/02614 , H01L21/385 , H01L21/441 , H01L21/477 , H01L29/7869
摘要： A thin film transistor includes a substrate, an oxide semiconductor layer that is disposed on the substrate, a gate electrode that overlaps with the oxide semiconductor layer, a gate insulating layer that is disposed between the oxide semiconductor layer and the gate electrode, and a source electrode and a drain electrode that at least partially overlap with the oxide semiconductor layer and are spaced from each other. The gate insulating layer includes an oxide including a first material. The oxide semiconductor layer includes an oxide which includes a same material as the first material and a second material, and the source electrode and the drain electrode include an oxide that includes a same material as the second material and a third material, and a grain boundary is not formed on an interface between at least one of the gate insulating layer and the oxide semiconductor layer or between the oxide semiconductor layer, and the source electrode and the drain electrode.
摘要翻译：薄膜晶体管包括衬底，设置在衬底上的氧化物半导体层，与氧化物半导体层重叠的栅电极，设置在氧化物半导体层和栅电极之间的栅极绝缘层，以及源极电极和与氧化物半导体层至少部分重叠并且彼此间隔开的漏电极。栅极绝缘层包括包含第一材料的氧化物。氧化物半导体层包括与第一材料相同的材料和第二材料的氧化物，源电极和漏极包括包含与第二材料相同的材料的氧化物和第三材料，以及晶界不形成在栅极绝缘层和氧化物半导体层中的至少一个之间或氧化物半导体层以及源电极和漏电极之间的界面上。

82. 发明申请

US20130320327A1 THIN FILM TRANSISTOR AND METHOD OF FORMING THE SAME 有权
公开(公告)号：US20130320327A1
公开(公告)日：2013-12-05
申请号：US13673195
申请日：2012-11-09
申请人： SAMSUNG DISPLAY CO., LTD.
发明人： Doo Hyoung LEE , Bo Sung Kim , Chan Woo Yang , Seung-Ho Jung , Yeon Taek Jeong , June Whan Choi , Tae-Young Choi
IPC分类号： H01L29/786 , H01L21/385
CPC分类号： H01L29/66969 , H01L21/02565 , H01L21/02614 , H01L21/385 , H01L21/441 , H01L21/477 , H01L29/7869
摘要： A thin film transistor includes a substrate, an oxide semiconductor layer that is disposed on the substrate, a gate electrode that overlaps with the oxide semiconductor layer, a gate insulating layer that is disposed between the oxide semiconductor layer and the gate electrode, and a source electrode and a drain electrode that at least partially overlap with the oxide semiconductor layer and are spaced from each other. The gate insulating layer includes an oxide including a first material. The oxide semiconductor layer includes an oxide which includes a same material as the first material and a second material, and the source electrode and the drain electrode include an oxide that includes a same material as the second material and a third material, and a grain boundary is not formed on an interface between at least one of the gate insulating layer and the oxide semiconductor layer or between the oxide semiconductor layer, and the source electrode and the drain electrode.

83. 发明授权

US07534691B2 Isolation structures for preventing photons and carriers from reaching active areas and methods of formation 有权
标题翻译：用于防止光子和载体到达有源区域的隔离结构和形成方法
公开(公告)号：US07534691B2
公开(公告)日：2009-05-19
申请号：US11495547
申请日：2006-07-31
申请人： Bryan G. Cole , Troy Sorensen
发明人： Bryan G. Cole , Troy Sorensen
IPC分类号： H01L21/225 , H01L21/385 , H01L31/118
CPC分类号： H01L27/1463 , H01L31/103
摘要： Regions of an integrated circuit are isolated by a structure that includes at least one isolating trench on the periphery of an active area. The trench is deep, extending at least about 0.5 μm into the substrate. The isolating structure prevents photons and electrons originating in peripheral circuitry from reaching the active area. Where the substrate has a heavily-doped lower layer and an upper layer on it, the trench can extend through the upper layer to the lower layer. A thermal oxide can be grown on the trench walls. A liner can also be deposited on the sidewalls of each trench. A fill material having a high-extinction coefficient is then deposited over the liner. The liner can also be light absorbent so that both the liner and fill material block photons.
摘要翻译：集成电路的区域由在有源区域的外围包括至少一个隔离沟槽的结构隔离。沟槽是深的，延伸至少约0.5μm的衬底。隔离结构防止源自外围电路的光子和电子到达有源区。当衬底在其上具有重掺杂的下层和上层时，沟槽可以延伸通过上层到下层。热氧化物可以在沟槽壁上生长。衬垫也可以沉积在每个沟槽的侧壁上。然后将具有高消光系数的填充材料沉积在衬垫上。衬里也可以是轻的吸收剂，以便衬垫和填充材料阻挡光子。

84. 发明申请

US20070026650A1 Method of limiting vacancy diffusion in a heterostructure 审中-公开
标题翻译：限制异质结构中空位扩散的方法
公开(公告)号：US20070026650A1
公开(公告)日：2007-02-01
申请号：US11521146
申请日：2006-09-13
申请人： Xavier Hebras
发明人： Xavier Hebras
IPC分类号： H01L21/385
CPC分类号： H01L21/26506 , H01L21/76254
摘要： A method of fabricating a heterostructure comprising at least a first layer of semi-conductor material such as, for example, a silicon-germanium (SiGe) layer on a second layer or a substrate of another material. The material of the second layer may differ from that of the first layer. To prevent elements of the semiconductor material of the first layer from diffusing into the first layer as well as the adjacent layers by a vacancy mechanism, the first layer may be enriched with interstitial defects to limit vacancy diffusion of elements of the first layer.
摘要翻译：一种制造异质结构的方法，其包括至少第一层半导体材料，例如第二层上的硅 - 锗（SiGe）层或另一材料的衬底。第二层的材料可以不同于第一层的材料。为了防止第一层的半导体材料的元件通过空位机构扩散到第一层以及相邻层中，第一层可能富含间隙缺陷以限制第一层的元件的空位扩散。

85. 发明授权

US5994206A Method of forming a high conductivity metal interconnect using metal gettering plug and system performing the method 失效
标题翻译：使用金属吸气塞形成高导电性金属互连的方法和执行该方法的系统
公开(公告)号：US5994206A
公开(公告)日：1999-11-30
申请号：US944170
申请日：1997-10-06
申请人： Subhash Gupta , Susan Hsuching Chen
发明人： Subhash Gupta , Susan Hsuching Chen
IPC分类号： H01L21/768 , H01L21/225 , H01L21/385
CPC分类号： H01L21/76877 , H01L21/76802
摘要： A method and system for providing a via structure for a high conductivity metal of a integrated circuit is disclosed. In a first aspect the method and system comprises etching a photoresist material and a dielectric material down to the high conductivity metal to form a via hole. The via hole includes sputtered high conductivity metal on the sidewalls. The method and system further includes providing a via plug material within the via hole. The vial plug material substantially covers a base portion of the high conductivity metal and the sidewalls of the via hole. The via plug material is also capable of gettering or dissolving the high conductivity metal sputtered on the sidewalls of the dielectric material. In a second aspect, a via structure for an integrated circuit is disclosed in accordance with the present invention. The via structure includes a high conductivity metal and a dielectric material surrounding the high conductivity metal. The dielectric material includes sidewalls to form a via hole on tope of the high conductivity metal. The via structure further includes a via plug material covering the high conductivity metal and substantially filling the via hole. The via plug material is also capable of gettering or dissolving the high conductivity metal sputtered on the sidewalls of the via hole. Accordingly, by providing a via plug material within the via hole, the via plug material getters or dissolves the high conductivity metal that reaches the sidewalls of the dielectric layer during the via etch and sputter etch processes and the junction poisoning problems associated therewith are substantially minimized.
摘要翻译：公开了一种用于为集成电路的高导电性金属提供通孔结构的方法和系统。在第一方面，该方法和系统包括将光致抗蚀剂材料和电介质材料蚀刻到高导电性金属上以形成通孔。通孔包括在侧壁上的溅射的高导电性金属。该方法和系统还包括在通孔内提供通孔塞材料。小瓶插头材料基本上覆盖高导电性金属的基部和通孔的侧壁。通孔插塞材料还能够吸收或溶解溅射在电介质材料的侧壁上的高导电性金属。在第二方面中，根据本发明公开了一种用于集成电路的通孔结构。通孔结构包括高导电性金属和围绕高导电性金属的介电材料。电介质材料包括在高导电性金属的顶部上形成通孔的侧壁。通孔结构还包括覆盖高导电性金属并基本上填充通孔的通孔塞材料。通孔插塞材料还能够吸收或溶解溅射在通孔的侧壁上的高导电性金属。因此，通过在通孔内提供通孔插塞材料，通孔插塞材料在通孔蚀刻和溅射蚀刻工艺期间吸收或溶解到达介电层侧壁的高导电性金属，并且与之相关的结中毒问题基本上最小化。

86. 发明授权

US5877072A Process for forming doped regions from solid phase diffusion source 失效
标题翻译：用于从固相扩散源形成掺杂区的工艺
公开(公告)号：US5877072A
公开(公告)日：1999-03-02
申请号：US829113
申请日：1997-03-31
申请人： Ebrahim Andideh , Scott E. Thompson
发明人： Ebrahim Andideh , Scott E. Thompson
IPC分类号： H01L21/225 , H01L21/316 , H01L21/385
CPC分类号： H01L21/02129 , H01L21/02271 , H01L21/02362 , H01L21/2255 , H01L21/31612
摘要： A process for doping a region in a substrate from a solid phase source. An inert gas is bubbled through a dopant containing ester and supplied to a chamber along with the gases used to form a silicon dioxide layer such as a TEOS formed layer. The flow of the inert gas can be modulated to grade the dopant concentration in the silicon dioxide layer. The dopant is diffused from the silicon dioxide layer into the substrate to form, for instance, source and drain regions in field-effect transistors.
摘要翻译：用于从固相源掺杂在衬底中的区域的工艺。将惰性气体鼓泡通过含掺杂剂的酯，并与用于形成诸如TEOS形成层的二氧化硅层的气体一起供应到室。可以调节惰性气体的流动，以评估二氧化硅层中的掺杂剂浓度。掺杂剂从二氧化硅层扩散到衬底中以在场效应晶体管中形成例如源极和漏极区。

87. 发明授权

US4927773A Method of minimizing implant-related damage to a group II-VI semiconductor material 失效
标题翻译：将II-VI族半导体材料的植入物相关损伤最小化的方法
公开(公告)号：US4927773A
公开(公告)日：1990-05-22
申请号：US361452
申请日：1989-06-05
申请人： Michael D. Jack , George R. Chapman , Michael Ray
发明人： Michael D. Jack , George R. Chapman , Michael Ray
IPC分类号： H01L21/324 , H01L21/265 , H01L21/385 , H01L21/425 , H01L21/477
CPC分类号： H01L21/385
摘要： A method of forming in a semiconductor material a region having a different chemical composition or a different concentration than a chemical composition or concentration of material surrounding the region. The method includes an initial step of providing a substantially single crystalline body of material, such as an epitaxial layer 10 of HgCdTe. Another step forms a cap layer 12 over a surface of the body, the layer having a thickness T. The cap layer 12 is comprised of a layer of polycrystalline material, such as CdTe, or is comprised of a layer of an organic material, an amorphous dielectric or a single-crystalline layer. A further step implants a selected chemical species through an upper surface of the cap, the species being implanted to a depth such that substantially no implant damage is sustained by the underlying body. In p-n junction formation the species is selected to form a region having an opposite type of electrical conductivity than the conductivity of the layer 10. A further step diffuses during a thermal anneal the implanted species from the cap layer down into the underlying layer to form a region therein having a different chemical composition or concentration than the chemical composition or concentration of the material surrounding the region. The method is also shown to be suitable for bipolar and JFET transistor fabrication in Group II-VI and Group III-V materials.

88. 发明授权

US4757027A Method for fabricating improved oxide defined transistors 失效
标题翻译：制造改进的氧化物限定晶体管的方法
公开(公告)号：US4757027A
公开(公告)日：1988-07-12
申请号：US009773
申请日：1987-02-02
申请人： Madhukar B. Vora
发明人： Madhukar B. Vora
IPC分类号： H01L21/8222 , H01L21/225 , H01L21/285 , H01L21/331 , H01L21/76 , H01L27/06 , H01L29/08 , H01L29/10 , H01L29/73 , H01L29/732 , H01L21/385
CPC分类号： H01L21/225 , H01L21/2257 , H01L21/28525 , H01L21/28531 , H01L29/0804 , H01L29/10 , H01L29/6628 , H01L29/7325
摘要： Two insulating layers may be employed to define boundaries of junctions in transistor structures useful in integrated circuit fabrication. The junctions may overlie one another, have approximately equal areas, and terminate in the insulating layers.
摘要翻译：可以使用两个绝缘层来限定用于集成电路制造的晶体管结构中的结的边界。接头可以彼此叠置，具有大致相等的面积，并终止在绝缘层中。

89. 发明授权

US4755486A Method of producing a defined arsenic doping in silicon semiconductor substrates 失效
标题翻译：在硅半导体衬底中制造定义的砷掺杂的方法
公开(公告)号：US4755486A
公开(公告)日：1988-07-05
申请号：US108558
申请日：1987-10-15
申请人： Helmuth Treichel , Frank S. Becker
发明人： Helmuth Treichel , Frank S. Becker
IPC分类号： H01L21/225 , H01L21/316 , H01L21/385
CPC分类号： H01L21/2255 , H01L21/31604
摘要： A method of producing a defined arsenic doping in silicon semiconductor substrates is provided. Preferably, the arsenic doping is produced in the sidewalls and floors of trenches having high aspect ratio which are etched into the substrates. An arseno-silicate glass layer is deposited into these trenches to be used as a diffusion source, the glass layer being removed after the diffusion. The arseno-silicate glass layer is deposited by thermal decomposition from the vapor phase of tetraethylortho silicate Si)OC.sub.2 H.sub.5).sub.4 and triethylarsenate AsO(OC.sub.2 H.sub.5).sub.3. A steep and reproducible doping profile having constant, maximum penetration depth and high arsenic concentration in the substrate surface which is needed for VLSI semiconductor circuits is obtained through the process of the present invention.
摘要翻译：提供了一种在硅半导体衬底中制造规定的砷掺杂的方法。优选地，在具有高纵横比的沟槽的侧壁和底板中产生砷掺杂，其被蚀刻到衬底中。在这些沟槽中沉积砷硅酸盐玻璃层作为扩散源，在扩散后去除玻璃层。通过从四乙基硅酸盐Si）OC 2 H 5）4和二乙基砷酸盐AsO（OC2H5）3的气相中的热分解沉积砷硅酸盐玻璃层。通过本发明的方法获得了在VLSI半导体电路所需的衬底表面中具有恒定的最大穿透深度和高砷浓度的陡峭且可再现的掺杂分布。

90. 发明授权

US4742015A Method for producing a protective arrangement for a field-effect transistor 失效
标题翻译：用于产生场效应晶体管的保护装置的方法
公开(公告)号：US4742015A
公开(公告)日：1988-05-03
申请号：US35265
申请日：1987-04-06
申请人： Manfred Ohagen
发明人： Manfred Ohagen
IPC分类号： H01L21/265 , H01L27/02 , H01L29/06 , H01L29/08 , H01L21/385 , H01L21/425
CPC分类号： H01L29/0619 , H01L21/26513 , H01L27/0255 , H01L29/0847
摘要： The invention relates to a protective arrangement for field-effect transistors with an insulated gate electrode. An integrated, indiffused protective diode whose breakdown voltage is smaller than that of the gate insulating layer is used therefor. The gist of the invention is that the breakdown voltage of the protective diode is set by two implantation processes, one of which is substantially limited to the region containing the in-diffused diode and the other of which substantially covers the surface of the substrate other than at least the channel region of the field-effect transistor so as to simultaneously increase the field inversion voltage.
摘要翻译：本发明涉及一种具有绝缘栅电极的场效晶体管的保护装置。使用其击穿电压小于栅极绝缘层的击穿电压的集成的，不扩散的保护二极管。本发明的要点是保护二极管的击穿电压是通过两个注入工艺来设定的，其中之一基本上限于含有扩散二极管的区域，另外一个基本上覆盖基板的表面，而不是至少场效应晶体管的沟道区域，以便同时增加场反转电压。

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