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81. 发明申请

US20120186747A1 PLASMA PROCESSING APPARATUS 审中-公开
标题翻译：等离子体加工设备
公开(公告)号：US20120186747A1
公开(公告)日：2012-07-26
申请号：US13236775
申请日：2011-09-20
申请人： Shinji OBAMA , Masaru Izawa , Kenji Maeda , Yoshihide Kihara , Kouichi Yamamoto , Hitoshi Tamura
发明人： Shinji OBAMA , Masaru Izawa , Kenji Maeda , Yoshihide Kihara , Kouichi Yamamoto , Hitoshi Tamura
IPC分类号： H01L21/00 , C23F1/08
CPC分类号： H01J37/32284
摘要： A plasma processing apparatus is provided with a processing chamber which is arranged inside a vacuum container and plasma is formed inside, a circular shape plate member made of a dielectric material arranged above the processing chamber through which an electric field is transmitted, and a cavity part having a cylindrical shape arranged above the plate member and the electric field is introduced inside, in which the cavity part is provided with a first cylindrical cavity part having a cylindrical shape cavity with a large diameter and having the plate member as the bottom face, a second cylindrical cavity part arranged above to be connected to the first cylindrical cavity part and having a cylindrical shape cavity with a small diameter, and a step portion for connecting these between the first and the second cylindrical cavity parts.
摘要翻译：一种等离子体处理装置，具有设置在真空容器内的等离子体内部的处理室，配置在通过电场传播的处理室上方的电介质材料构成的圆形板状构件，以及空腔部具有布置在板构件上方的圆柱形状并且将电场引入内部，其中空腔部分设置有具有大直径的圆柱形形状的腔体并具有板构件作为底面的第一圆柱形空腔部分，第二圆柱形空腔部分，其布置在上面以连接到第一圆柱形空腔部分并且具有小直径的圆柱形形状腔;以及阶梯部分，用于将它们连接在第一和第二圆柱形空腔部分之间。

82. 发明授权

US08197635B2 Plasma processing apparatus including etching processing apparatus and ashing processing apparatus and plasma processing method using plasma processing apparatus 失效
标题翻译：等离子体处理装置，包括蚀刻处理装置和灰化处理装置以及使用等离子体处理装置的等离子体处理方法
公开(公告)号：US08197635B2
公开(公告)日：2012-06-12
申请号：US13018838
申请日：2011-02-01
申请人： Hiroyuki Kobayashi , Masaru Izawa
发明人： Hiroyuki Kobayashi , Masaru Izawa
IPC分类号： C23F1/00 , H01L21/306 , C23C16/00 , B05C13/00
CPC分类号： H01J37/32642 , H01J37/32623 , H01J2237/335 , H01L21/67207 , H01L21/68735 , H01L21/68785 , Y10S156/915
摘要： A diameter of a mounting unit of the stage of an ashing processing apparatus is less than a diameter of a mounting unit of the stage of an etching processing apparatus, and the diameter of the mounting unit of the stage of the etching processing apparatus is less than a diameter of an objective item.
摘要翻译：灰化处理装置的台的安装单元的直径小于蚀刻处理装置的台的安装单元的直径，并且蚀刻处理装置的台的安装单元的直径小于客观物品的直径。

83. 发明授权

US07915055B2 Manufacturing method of semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US07915055B2
公开(公告)日：2011-03-29
申请号：US11693776
申请日：2007-03-30
申请人： Masaru Kurihara , Masaru Izawa , Junichi Tanaka
发明人： Masaru Kurihara , Masaru Izawa , Junichi Tanaka
IPC分类号： H01L21/66 , G01R31/26
CPC分类号： H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a manufacturing technique of a semiconductor device that reduces fluctuation of electric characteristic and a working size of a semiconductor device and can manufacture semiconductor devices at high quality and at high yield. In a semiconductor device manufacturing system, a control method for a manufacturing process of a semiconductor device having a function (a data collecting unit) of collecting examination data at a plurality of examining steps including an examining step of setting a length of a measurement region in a wiring direction to at least 10 times a wire width to measure the wire width and an examining step of examining the wire width, a function (a data analyzing unit) of generating a prediction model of electric characteristic or working size of a semiconductor device using the examination data to generate a control model from the prediction model, and a function (a process control unit) of properly controlling processing conditions for a control process based upon examination data of the plurality of examining steps in the manufacturing process of a semiconductor device and the control model is realized.
摘要翻译：本发明提供一种能够降低半导体装置的电气特性和工作尺寸的波动的半导体装置的制造技术，能够高质量，高产率地制造半导体装置。在半导体器件制造系统中，具有在多个检查步骤中收集检查数据的功能（数据收集单元）的半导体器件的制造过程的控制方法包括将测量区域的长度设置在布线方向为线宽的至少10倍以测量线宽度和检查线宽度的检查步骤，产生半导体器件的电特性或工作尺寸的预测模型的功能（数据分析单元），其使用根据预测模型生成控制模型的检查数据和根据半导体装置的制造过程中的多个检查步骤的检查数据适当地控制用于控制处理的处理条件的功能（过程控制单元），以及实现了控制模型。

84. 发明授权

US07720632B2 Dimension measuring apparatus and dimension measuring method for semiconductor device 有权
标题翻译：半导体器件的尺寸测量装置和尺寸测量方法
公开(公告)号：US07720632B2
公开(公告)日：2010-05-18
申请号：US12128364
申请日：2008-05-28
申请人： Masaru Kurihara , Masaru Izawa , Junichi Tanaka
发明人： Masaru Kurihara , Masaru Izawa , Junichi Tanaka
IPC分类号： G01B15/00 , G01N23/00
CPC分类号： H01L22/12 , H01J2237/2813
摘要： A dimension measuring apparatus used for measuring a dimension of a semiconductor device having a first pattern of repeated structure and a second pattern that is linear and formed on the first pattern to extend over the repeated structure. The invention includes a shape information acquisition unit which acquires information on a shape of the first pattern; a width value acquisition unit which acquires a width value of each portion of the second pattern; an analytic area setting unit, which sets a plurality of analytic areas on the second pattern; and a dimension determining unit, which extracts, for each of the set analytic areas, width values of portions included in the analytic area, and uses the extracted width values to determine a dimension of the second pattern at portions overlapping the first pattern.
摘要翻译：一种尺寸测量装置，用于测量具有重复结构的第一图案和第二图案的半导体器件的尺寸，该第二图案是线性的并形成在第一图案上以在重复结构上延伸。本发明包括获取关于第一图案的形状的信息的形状信息获取单元; 宽度值获取单元，其获取所述第二图案的每个部分的宽度值; 分析区域设置单元，其设置所述第二图案上的多个分析区域; 以及尺寸确定单元，其针对每个所述分析区域提取包括在所述分析区域中的部分的宽度值，并且使用所提取的宽度值来确定与所述第一图案重叠的部分处的所述第二图案的尺寸。

85. 发明申请

US20070023143A1 Plasma processing apparatus including etching processing apparatus and ashing processing apparatus and plasma processing method using plasma processing apparatus 审中-公开
标题翻译：等离子体处理装置，包括蚀刻处理装置和灰化处理装置以及使用等离子体处理装置的等离子体处理方法
公开(公告)号：US20070023143A1
公开(公告)日：2007-02-01
申请号：US11355162
申请日：2006-02-16
申请人： Hiroyuki Kobayashi , Masaru Izawa
发明人： Hiroyuki Kobayashi , Masaru Izawa
IPC分类号： H01L21/306
CPC分类号： H01J37/32642 , H01J37/32623 , H01J2237/335 , H01L21/67207 , H01L21/68735 , H01L21/68785 , Y10S156/915
摘要： A diameter of a mounting unit of the stage of an ashing processing apparatus is less than a diameter of a mounting unit of the stage of an etching processing apparatus, and the diameter of the mounting unit of the stage of the etching processing apparatus is less than a diameter of an objective item.
摘要翻译：灰化处理装置的台的安装单元的直径小于蚀刻处理装置的台的安装单元的直径，并且蚀刻处理装置的台的安装单元的直径小于客观物品的直径。

86. 发明申请

US20050017178A1 Micro-spectroscopic measuring device and micro-chemical system 失效
标题翻译：微光谱测量装置和微观化学系统
公开(公告)号：US20050017178A1
公开(公告)日：2005-01-27
申请号：US10788275
申请日：2004-03-01
申请人： Taro Ogawa , Toshiki Sugawara , Kazuhiko Hosomi , Masataka Shirai , Toshio Katsuyama , Kaoru Umemura , Masaru Izawa , Kazuhiko Sagara , Hiroshi Kakibayashi
发明人： Taro Ogawa , Toshiki Sugawara , Kazuhiko Hosomi , Masataka Shirai , Toshio Katsuyama , Kaoru Umemura , Masaru Izawa , Kazuhiko Sagara , Hiroshi Kakibayashi
IPC分类号： G01J3/14 , B01J19/00 , B01L3/00 , G01J3/42 , G01N21/05 , G01N21/31 , G01N21/35 , G01N21/3577 , G01N37/00
CPC分类号： G01N21/31 , B01L3/502715 , B01L2200/027 , B01L2300/0654 , B01L2300/0816 , B01L2300/0887 , G01N21/05 , G01N2021/0346 , G01N2021/058 , G01N2201/0873
摘要： A micro-spectroscopic measuring device having a structure in which a spectroscopic element made of an array of photonic crystals with defects, flow paths for introducing a sample, and light detecting elements with sensitivity to a band from near infrared to infrared are stacked.
摘要翻译：具有这样的结构的微分光学测量装置被堆叠，其中由具有缺陷的光子晶体阵列制成的分光元件，用于引入样品的流动路径和对从近红外线到红外线的频带具有灵敏度的光检测元件。

87. 发明授权

US06842658B2 Method of manufacturing a semiconductor device and manufacturing system 失效
标题翻译：制造半导体器件和制造系统的方法
公开(公告)号：US06842658B2
公开(公告)日：2005-01-11
申请号：US09791666
申请日：2001-02-26
申请人： Masaru Izawa , Masahito Mori , Nobuyuki Negishi , Shinichi Tachi
发明人： Masaru Izawa , Masahito Mori , Nobuyuki Negishi , Shinichi Tachi
IPC分类号： H01L21/302 , G05B19/418 , H01L21/00 , H01L21/02 , H01L21/3065 , G06F19/00
CPC分类号： G05B19/41875 , G05B2219/31288 , G05B2219/32053 , G05B2219/32198 , G05B2219/45031 , H01L21/67276 , Y02P90/14 , Y02P90/18 , Y02P90/20 , Y02P90/22 , Y02P90/26 , Y02P90/86
摘要： Automatic generation of processing conditions will be provided, based on a database and process modeling by a computer equipped in semiconductor device fabrication equipment, by using input of wafer processing history including the thickness and quality. The computer equipped in semiconductor device fabrication equipment obtains the wafer processing and inspection results from a production line management computer in order to assist input of the process history. The computer in the fabrication equipment can be connected to computers in a fabrication equipment manufacturer on a communication network to automatically provide process conditions and maintenance schedule.
摘要翻译：将通过使用半导体器件制造设备中配备的计算机的数据库和过程建模，通过使用包括厚度和质量的晶片处理历史的输入来提供自动生成处理条件。配备在半导体器件制造设备中的计算机从生产线管理计算机获得晶片处理和检查结果，以帮助输入过程历史。制造设备中的计算机可以连接到通信网络上制造设备制造商中的计算机，以自动提供过程条件和维护计划。

88. 发明授权

US06677244B2 Specimen surface processing method 有权
标题翻译：试样表面处理方法
公开(公告)号：US06677244B2
公开(公告)日：2004-01-13
申请号：US10135516
申请日：2002-05-01
申请人： Tetsuo Ono , Yasuhiro Nishimori , Takashi Sato , Naoyuki Kofuji , Masaru Izawa , Yasushi Goto , Ken Yoshioka , Hideyuki Kazumi , Tatsumi Mizutani , Tokuo Kure , Masayuki Kojima , Takafumi Tokunaga , Motohiko Yoshigai
发明人： Tetsuo Ono , Yasuhiro Nishimori , Takashi Sato , Naoyuki Kofuji , Masaru Izawa , Yasushi Goto , Ken Yoshioka , Hideyuki Kazumi , Tatsumi Mizutani , Tokuo Kure , Masayuki Kojima , Takafumi Tokunaga , Motohiko Yoshigai
IPC分类号： H01L21302
CPC分类号： H01J37/32082 , H01L21/32136
摘要： A plasma processing method for etching a sample having a gate oxide film includes generating a plasma in a vacuum chamber using electromagnetic waves, applying an rf bias power to the sample, turning off the rf bias power before a charged voltage of the sample reaches a breakdown voltage, turning on the rf bias power after the charged voltage of the sample has substantially dropped, and repeating the turning on and off of the rf bias power to process the sample. The off-time is set at least longer than the on-time.
摘要翻译：用于蚀刻具有栅极氧化膜的样品的等离子体处理方法包括使用电磁波在真空室中产生等离子体，向样品施加rf偏置功率，在样品的充电电压达到击穿之前关闭rf偏置功率电压，在样品的充电电压基本上下降之后接通rf偏置功率，并且重复接通和关断rf偏置功率以处理样品。关闭时间至少比准时更长。

89. 发明授权

US06673685B2 Method of manufacturing semiconductor devices 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US06673685B2
公开(公告)日：2004-01-06
申请号：US10083397
申请日：2002-02-27
申请人： Masahito Mori , Naoshi Itabashi , Masaru Izawa
发明人： Masahito Mori , Naoshi Itabashi , Masaru Izawa
IPC分类号： H01L21336
CPC分类号： H01L21/28123 , H01L21/31138 , H01L21/32136 , H01L21/32137 , H01L21/32139
摘要： A process for economical and efficient fabrication of gate electrodes no larger than 50 nm, which is beyond the limit of exposure, is characterized by gate-electrode trimming and mask trimming with high resist selectivity which are performed in combination. The process is also preferably characterized by performing trimming and drying cleaning in a vacuum environment and may also include steps of inspecting dimensions and contamination in a vacuum environment. The process can be implemented to provide the effects of forming a gate no longer than 50 nm (beyond the limit of exposure) without restrictions on the resist thickness; reducing contamination resulting from transfer of wafers from one step to next, thereby improving yields; preventing resist from hydrolysis by ArF laser, thereby reducing roughening which adversely affects the gate width; and ensuring stable yields despite variation in dimensions and contamination owing to the additional dry cleaning step and feed-forward control based on CD inspection and contamination inspection.
摘要翻译：用于经济有效地制造不超过50nm的栅电极的方法，其超出了曝光的限度，其特征在于组合执行的具有高抗蚀剂选择性的栅电极修整和掩模修剪。该方法还优选的特征在于在真空环境中进行修整和干燥清洁，并且还可以包括在真空环境中检查尺寸和污染的步骤。可以实现该过程以提供形成栅极不超过50nm（超过曝光极限）而不限制抗蚀剂厚度的效果; 减少晶片从一步转移到下一步导致的污染，从而提高产量; 防止ArF激光器的抗水解，从而减少对栅极宽度有不利影响的粗糙化; 并确保稳定的产量，尽管由于额外的干洗步骤和基于CD检查和污染检查的前馈控制而导致尺寸和污染的变化。

90. 发明授权

US06506674B2 Method of manufacturing a semiconductor integrated circuit device 有权
公开(公告)号：US06506674B2
公开(公告)日：2003-01-14
申请号：US09964628
申请日：2001-09-28
申请人： Takenobu Ikeda , Masahiro Tadokoro , Masaru Izawa , Takashi Yunogami
发明人： Takenobu Ikeda , Masahiro Tadokoro , Masaru Izawa , Takashi Yunogami
IPC分类号： H01L214763
CPC分类号： H01L21/76897 , H01L21/31116 , H01L21/76802 , H01L21/76814
摘要： A hole is formed on an insulating film made of silicon oxide by selectively plasma-etching the insulating film with an etching gas containing C5F8, O2, and Ar firstly under a condition in which the deposition property of a polymer layer is weak and secondly under a condition in which that of the polymer layer is strong.

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