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1. 发明授权

US06677244B2 Specimen surface processing method 有权
标题翻译：试样表面处理方法
公开(公告)号：US06677244B2
公开(公告)日：2004-01-13
申请号：US10135516
申请日：2002-05-01
申请人： Tetsuo Ono , Yasuhiro Nishimori , Takashi Sato , Naoyuki Kofuji , Masaru Izawa , Yasushi Goto , Ken Yoshioka , Hideyuki Kazumi , Tatsumi Mizutani , Tokuo Kure , Masayuki Kojima , Takafumi Tokunaga , Motohiko Yoshigai
发明人： Tetsuo Ono , Yasuhiro Nishimori , Takashi Sato , Naoyuki Kofuji , Masaru Izawa , Yasushi Goto , Ken Yoshioka , Hideyuki Kazumi , Tatsumi Mizutani , Tokuo Kure , Masayuki Kojima , Takafumi Tokunaga , Motohiko Yoshigai
IPC分类号： H01L21302
CPC分类号： H01J37/32082 , H01L21/32136
摘要： A plasma processing method for etching a sample having a gate oxide film includes generating a plasma in a vacuum chamber using electromagnetic waves, applying an rf bias power to the sample, turning off the rf bias power before a charged voltage of the sample reaches a breakdown voltage, turning on the rf bias power after the charged voltage of the sample has substantially dropped, and repeating the turning on and off of the rf bias power to process the sample. The off-time is set at least longer than the on-time.
摘要翻译：用于蚀刻具有栅极氧化膜的样品的等离子体处理方法包括使用电磁波在真空室中产生等离子体，向样品施加rf偏置功率，在样品的充电电压达到击穿之前关闭rf偏置功率电压，在样品的充电电压基本上下降之后接通rf偏置功率，并且重复接通和关断rf偏置功率以处理样品。关闭时间至少比准时更长。

2. 发明授权

US07049243B2 Surface processing method of a specimen and surface processing apparatus of the specimen 有权
标题翻译：试样的表面处理方法和试样的表面处理装置
公开(公告)号：US07049243B2
公开(公告)日：2006-05-23
申请号：US10754594
申请日：2004-01-12
申请人： Tetsuo Ono , Yasuhiro Nishimori , Takashi Sato , Naoyuki Kofuji , Masaru Izawa , Yasushi Goto , Ken Yoshioka , Hideyuki Kazumi , Tatsumi Mizutani , Tokuo Kure , Masayuki Kojima , Takafumi Tokunaga , Motohiko Yoshigai
发明人： Tetsuo Ono , Yasuhiro Nishimori , Takashi Sato , Naoyuki Kofuji , Masaru Izawa , Yasushi Goto , Ken Yoshioka , Hideyuki Kazumi , Tatsumi Mizutani , Tokuo Kure , Masayuki Kojima , Takafumi Tokunaga , Motohiko Yoshigai
IPC分类号： H01L21/302
CPC分类号： H01J37/32082 , H01L21/32136
摘要： A plasma processing method for etching a sample having a gate oxide film which generates a plasma in a vacuum chamber using electromagnetic waves, applies an rf bias power to the sample, turns off the rf bias power before a charged voltage of the sample reaches a breakdown voltage of the gate oxide film, turns on the rf bias power after the charged voltage of the sample has substantially dropped and repeats the turning on and off of the rf bias power to process the sample. The off-time is set at least longer than the on-time, and the plasma is generated by continuously supplying power to enable generation of the plasma during the repeated turning on and off of the rf bias power.
摘要翻译：一种用于蚀刻具有使用电磁波在真空室中产生等离子体的栅极氧化膜的样品的等离子体处理方法，对样品施加rf偏置功率，在样品的充电电压达到击穿之前关断rf偏置功率栅极氧化膜的电压在样品的充电电压基本上下降之后导通rf偏置功率，并重复rf偏置功率的导通和截止以处理样品。关断时间至少比导通时间长，并且通过连续供电以在反复打开和关闭rf偏置功率期间产生等离子体而产生等离子体。

3. 发明授权

US06492277B1 Specimen surface processing method and apparatus 有权
标题翻译：试样表面处理方法和装置
公开(公告)号：US06492277B1
公开(公告)日：2002-12-10
申请号：US09393893
申请日：1999-09-10
申请人： Tetsuo Ono , Yasuhiro Nishimori , Takashi Sato , Naoyuki Kofuji , Masaru Izawa , Yasushi Goto , Ken Yoshioka , Hideyuki Kazumi , Tatsumi Mizutani , Tokuo Kure , Masayuki Kojima , Takafumi Tokunaga , Motohiko Yoshigai
发明人： Tetsuo Ono , Yasuhiro Nishimori , Takashi Sato , Naoyuki Kofuji , Masaru Izawa , Yasushi Goto , Ken Yoshioka , Hideyuki Kazumi , Tatsumi Mizutani , Tokuo Kure , Masayuki Kojima , Takafumi Tokunaga , Motohiko Yoshigai
IPC分类号： H01L21302
CPC分类号： H01J37/32082 , H01L21/32136
摘要： Electrical damage to semiconductor elements in the plasma etching thereof is suppressed. In processing of a fine pattern by plasma etching, the high frequency power supply to be applied to the specimen is turned off before the charge potential at a portion of the pattern reaches the breakdown voltage of the gate oxide film which is interconnected to said fine pattern, and then the high frequency power supply is turned on when the charge potential at the portion of the pattern drops substantially. This on and off control is effected in a repetitive mode of operation.
摘要翻译：抑制其等离子体蚀刻对半导体元件的电气损伤。在通过等离子体蚀刻处理精细图案时，在图案的一部分处的电荷电位达到与所述精细图案互连的栅极氧化膜的击穿电压之前，施加到样本的高频电源被关断，然后当图案部分的电荷电位基本上下降时，高频电源被接通。该开启和关闭控制以重复的操作模式进行。

4. 发明授权

US06309980B1 Semiconductor integrated circuit arrangement fabrication method 有权
标题翻译：半导体集成电路布置制造方法
公开(公告)号：US06309980B1
公开(公告)日：2001-10-30
申请号：US09564754
申请日：2000-05-04
申请人： Takafumi Tokunaga , Sadayuki Okudaira , Tatsumi Mizutani , Kazutami Tago , Hideyuki Kazumi , Ken Yoshioka
发明人： Takafumi Tokunaga , Sadayuki Okudaira , Tatsumi Mizutani , Kazutami Tago , Hideyuki Kazumi , Ken Yoshioka
IPC分类号： H01L2100
CPC分类号： H01L21/31116 , H01L21/76802
摘要： To realize etching with a high selection ratio and a high accuracy in fabrication of an LSI, the composition of dissociated species of a reaction gas is accurately controlled when dry-etching a thin film on a semiconductor substrate by causing an inert gas excited to a metastable state in a plasma and a flon gas to interact with each other and selectively obtaining desired dissociated species.
摘要翻译：为了在LSI的制造中以高选择率和高精度实现蚀刻，当通过使惰性气体激发成亚稳态来干法蚀刻半导体衬底上的薄膜时，反应气体的解离物质的组成被精确地控制状态在等离子体和氟里昂气体中彼此相互作用并选择性地获得期望的解离物种。

5. 再颁专利

USRE39895E1 Semiconductor integrated circuit arrangement fabrication method 有权
标题翻译：半导体集成电路布置制造方法
公开(公告)号：USRE39895E1
公开(公告)日：2007-10-23
申请号：US10094157
申请日：2002-03-08
申请人： Takafumi Tokunaga , Sadayuki Okudaira , Tatsumi Mizutani , Kazutami Tago , Hideyuki Kazumi , Ken Yoshioka
发明人： Takafumi Tokunaga , Sadayuki Okudaira , Tatsumi Mizutani , Kazutami Tago , Hideyuki Kazumi , Ken Yoshioka
IPC分类号： H01L21/00
CPC分类号： H01L21/76802 , H01L21/31116
摘要： To realize etching with a high selection ratio and a high accuracy in fabrication of an LSI, the composition of dissociated species of a reaction gas is accurately controlled when dry-etching a thin film on a semiconductor substrate by causing an inert gas excited to a metastable state in a plasma and a flon gas to interact with each other and selectively obtaining desired dissociated species.
摘要翻译：为了在LSI的制造中以高选择率和高精度实现蚀刻，当通过使惰性气体激发成亚稳态来干法蚀刻半导体衬底上的薄膜时，反应气体的解离物质的组成被精确地控制状态在等离子体和氟里昂气体中彼此相互作用并选择性地获得期望的解离物种。

6. 发明授权

US06074958A Semiconductor integrated circuit arrangement fabrication method 有权
标题翻译：半导体集成电路布置制造方法
公开(公告)号：US06074958A
公开(公告)日：2000-06-13
申请号：US339041
申请日：1999-06-23
申请人： Takafumi Tokunaga , Sadayuki Okudaira , Tatsumi Mizutani , Kazutami Tago , Hideyuki Kazumi , Ken Yoshioka
发明人： Takafumi Tokunaga , Sadayuki Okudaira , Tatsumi Mizutani , Kazutami Tago , Hideyuki Kazumi , Ken Yoshioka
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/311 , H01L21/70 , H01L21/768 , H01L21/77 , H01L21/00
CPC分类号： H01L21/31116 , H01L21/76802
摘要： To realize etching with a high selection ratio and a high accuracy in fabrication of an LSI, the composition of dissociated species of a reaction gas is accurately controlled when dry-etching a thin film on a semiconductor substrate by causing an inert gas excited to a metastable state in a plasma and a flon gas to interact with each other and selectively obtaining desired dissociated species.
摘要翻译：为了在LSI的制造中以高选择率和高精度实现蚀刻，当通过使惰性气体激发成亚稳态来干法蚀刻半导体衬底上的薄膜时，反应气体的解离物质的组成被精确地控制状态在等离子体和氟里昂气体中彼此相互作用并选择性地获得期望的解离物种。

7. 发明授权

US5874013A Semiconductor integrated circuit arrangement fabrication method 失效
标题翻译：半导体集成电路布置制造方法
公开(公告)号：US5874013A
公开(公告)日：1999-02-23
申请号：US857167
申请日：1997-05-15
申请人： Takafumi Tokunaga , Sadayuki Okudaira , Tatsumi Mizutani , Kazutami Tago , Hideyuki Kazumi , Ken Yoshioka
发明人： Takafumi Tokunaga , Sadayuki Okudaira , Tatsumi Mizutani , Kazutami Tago , Hideyuki Kazumi , Ken Yoshioka
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/311 , H01L21/70 , H01L21/768 , H01L21/77 , B44C1/22 , C03C15/00 , C23F1/00
CPC分类号： H01L21/31116 , H01L21/76802
摘要： To realize etching with a high selection ratio and a high accuracy in fabrication of an LSI, the composition of dissociated species of a reaction gas is accurately controlled when dry-etching a thin film on a semiconductor substrate by causing an inert gas excited to a metastable state in a plasma and a flon gas to interact with each other, and selectively obtaining desired dissociated species.
摘要翻译：为了在LSI的制造中以高选择率和高精度实现蚀刻，当通过使惰性气体激发成亚稳态来干法蚀刻半导体衬底上的薄膜时，反应气体的解离物质的组成被精确地控制状态在等离子体和氟里昂气体中彼此相互作用，并且选择性地获得所需的解离物种。

8. 发明授权

US5962347A Semiconductor integrated circuit arrangement fabrication method 有权
公开(公告)号：US5962347A
公开(公告)日：1999-10-05
申请号：US188371
申请日：1998-11-10
申请人： Takafumi Tokunaga , Sadayuki Okudaira , Tatsumi Mizutani , Kazutami Tago , Hideyuki Kazumi , Ken Yoshioka
发明人： Takafumi Tokunaga , Sadayuki Okudaira , Tatsumi Mizutani , Kazutami Tago , Hideyuki Kazumi , Ken Yoshioka
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/311 , H01L21/70 , H01L21/768 , H01L21/77 , H01L21/00
CPC分类号： H01L21/31116 , H01L21/76802
摘要： To realize etching with a high selection ratio and a high accuracy in fabrication of an LSI, the composition of dissociated species of a reaction gas is accurately controlled when dry-etching a thin film on a semiconductor substrate by causing an inert gas excited to a metastable state in a plasma and a flon gas to interact with each other and selectively obtaining desired dissociated species.

9. 发明申请

US20060171093A1 Plasma processing method and plasma processing apparatus 有权
标题翻译：等离子体处理方法和等离子体处理装置
公开(公告)号：US20060171093A1
公开(公告)日：2006-08-03
申请号：US11069551
申请日：2005-03-02
申请人： Hiroaki Ishimura , Ken Yoshioka , Takahiro Abe , Go Saito , Motohiko Yoshigai
发明人： Hiroaki Ishimura , Ken Yoshioka , Takahiro Abe , Go Saito , Motohiko Yoshigai
IPC分类号： H01H1/00
CPC分类号： H01J37/32706 , H01J37/321 , H01L21/6833
摘要： In a plasma processing apparatus using electrostatic chuck, increase of plasma potential is prevented and abnormal discharge is avoided. The plasma processing apparatus comprises an RF source for generating plasma in a vacuum container, another RF source for applying an RF bias power to a sample, a sample stage having an electrostatic chuck electrode, a DC power supply for applying an electrostatic chuck voltage to the electrode, and a controller for shifting the electrostatic chuck voltage to negative by a potential difference of quarter to half of peak-to-peak voltage of the RF bias power for suppressing increase of plasma potential.
摘要翻译：在使用静电卡盘的等离子体处理装置中，防止等离子体电位的增加，避免异常放电。等离子体处理装置包括用于在真空容器中产生等离子体的RF源，用于向样品施加RF偏置功率的另一RF源，具有静电卡盘电极的样品台，用于向静电卡盘电压施加静电卡盘电压的DC电源电极，以及控制器，用于将静电卡盘电压转换为负值，以抑制RF偏置功率的峰 - 峰电压的四分之一到一半的电位差，以抑制等离子体电位的增加。

10. 发明授权

US09039865B2 Plasma processing apparatus 有权
标题翻译：等离子体处理装置
公开(公告)号：US09039865B2
公开(公告)日：2015-05-26
申请号：US12694363
申请日：2010-01-27
申请人： Ken Yoshioka , Motohiko Yoshigai , Ryoji Nishio , Tadayoshi Kawaguchi
发明人： Ken Yoshioka , Motohiko Yoshigai , Ryoji Nishio , Tadayoshi Kawaguchi
IPC分类号： H01L21/306 , C23C16/00 , H01J37/32
CPC分类号： H01J37/32623 , H01J37/321 , H01J37/3211
摘要： The invention provides a plasma processing apparatus in which ring-like conductors 8a and 8b are arranged closed to and along an induction antenna 1 composed of an inner circumference coil 1a and an outer circumference coil 1b. Ring-like conductors 8a and 8b are each characterized in that the radius from the center of the apparatus and the cross-sectional shape of the conductor body varies along the circumferential angle of the coils. Since the mutual inductances between the ring-like conductors 8a and 8b and the induction antenna 1 and between the ring-like conductors 8a and 8b and the plasma along the circumferential position are controlled, it becomes possible to compensate for the coil currents varied along the circumference of the coils of the induction antenna 1, and to improve the non-uniformity in the circumferential direction of the current in the generated plasma.
摘要翻译：本发明提供一种等离子体处理装置，其中环状导体8a和8b布置在由内周线圈1a和外周线圈1b构成的感应天线1的附近。环形导体8a和8b的特征在于，从设备中心的半径和导体主体的横截面形状沿线圈的圆周角度变化。由于控制环状导体8a，8b与感应天线1之间以及环状导体8a，8b与周边位置之间的等离子体之间的互感，因此能够补偿沿着感应天线1的线圈的周长，并且提高所产生的等离子体中的电流的圆周方向的不均匀性。

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