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81. 发明申请

US20070045676A1 SELF ALIGNED METAL GATES ON HIGH-K DIELECTRICS 有权
标题翻译：高K电子自对准金属门
公开(公告)号：US20070045676A1
公开(公告)日：2007-03-01
申请号：US11451703
申请日：2006-06-13
申请人： Leonard Forbes , Kie Ahn
发明人： Leonard Forbes , Kie Ahn
IPC分类号： H01L29/76 , H01L29/94 , H01L31/00
CPC分类号： H01L29/517 , H01L21/28114 , H01L21/28273 , H01L29/42376 , H01L29/495 , H01L29/6653 , H01L29/66545 , Y10S438/926
摘要： A method for forming a transistor including a self aligned metal gate is provided. According to various method embodiments, a high-k gate dielectric is formed on a substrate and a sacrificial carbon gate is formed on the gate dielectric. Sacrificial carbon sidewall spacers are formed adjacent to the sacrificial carbon gate, and source/drain regions for the transistor are formed using the sacrificial carbon sidewall spacers to define the source/drain regions. The sacrificial carbon sidewall spacers are replaced with non-carbon sidewall spacers, and the sacrificial carbon gate is replaced with a desired metal gate material to provide the desired metal gate material on the gate dielectric. Various embodiments form source/drain extensions after removing the carbon sidewall spacers and before replacing with non-carbon sidewall spacers. An etch barrier is used in various embodiments to separate the sacrificial carbon gate from the sacrificial carbon sidewall spacers. Other aspects and embodiments are provided herein.
摘要翻译：提供一种形成包括自对准金属栅极的晶体管的方法。根据各种方法实施例，在衬底上形成高k栅极电介质，并且在栅极电介质上形成牺牲碳栅。牺牲碳侧壁间隔件邻近牺牲碳栅形成，并且使用牺牲碳侧壁间隔物形成用于晶体管的源/漏区，以限定源极/漏极区。牺牲碳侧壁间隔物被非碳侧壁间隔物代替，并且牺牲碳栅被替换为期望的金属栅极材料以在栅极电介质上提供所需的金属栅极材料。各种实施例在去除碳侧壁间隔物之后并且在用非碳侧壁间隔物替换之前形成源极/漏极扩展。在各种实施例中使用蚀刻阻挡层将牺牲碳栅极与牺牲碳侧壁间隔物分离。本文提供了其它方面和实施例。

82. 发明申请

US20070020835A1 Atomic layer deposition of CeO2/Al2O3 films as gate dielectrics 失效
标题翻译： CeO2 / Al2O3薄膜的原子层沉积作为栅极电介质
公开(公告)号：US20070020835A1
公开(公告)日：2007-01-25
申请号：US11528776
申请日：2006-09-28
申请人： Kie Ahn , Leonard Forbes
发明人： Kie Ahn , Leonard Forbes
IPC分类号： H01L21/8234
CPC分类号： H01L21/28194 , C23C16/40 , C23C16/45529 , H01L21/02178 , H01L21/02192 , H01L21/022 , H01L21/0228 , H01L21/3142 , H01L21/31604 , H01L21/3162 , H01L29/513 , H01L29/517 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： The use of atomic layer deposition (ALD) to form a nanolaminate layered dielectric layer of cerium oxide and aluminum oxide acting as a single dielectric layer with a ratio of approximately two to one between the cerium oxide and the aluminum oxide, and a method of fabricating such a dielectric layer is described. The described arrangement produces a reliable structure with a high dielectric constant (high-k) for use in a variety of electronic devices. The dielectric structure is formed by depositing cerium oxide by atomic layer deposition onto a substrate surface using precursor chemicals, followed by depositing aluminum oxide onto the substrate using precursor chemicals, and repeating to form the thin laminate structure. Such a dielectric layer of cerium oxide and aluminum oxide may be used as the gate insulator of a MOSFET, as a capacitor dielectric in a DRAM, as a tunnel gate insulator in flash memory, or as a dielectric in an NROM device, because the high dielectric constant (high-k) of the film provides the functionality of a much thinner silicon dioxide film.
摘要翻译：使用原子层沉积（ALD）在氧化铈和氧化铝之间形成作为单一电介质层的二氧化铈和氧化铝的纳米级层状电介质层，其比例约为2比1，以及制造方法描述这种介电层。所描述的布置产生用于各种电子设备的具有高介电常数（高k）的可靠结构。通过使用前体化学品，通过原子层沉积将氧化铈沉积到衬底表面上，然后使用前体化学品将氧化铝沉积到衬底上并重复形成薄层压结构来形成电介质结构。这样的氧化铈和氧化铝的电介质层可以用作MOSFET的栅极绝缘体，作为DRAM中的电容器电介质，作为闪速存储器中的隧道栅极绝缘体，或者作为NROM器件中的电介质，因为高的膜的介电常数（high-k）提供了更薄的二氧化硅膜的功能。

83. 发明申请

US20060289993A1 Barrier-metal-free copper damascene technology using atomic hydrogen enhanced reflow 失效
公开(公告)号：US20060289993A1
公开(公告)日：2006-12-28
申请号：US11511652
申请日：2006-08-29
申请人： Kie Ahn , Leonard Forbes
发明人： Kie Ahn , Leonard Forbes
IPC分类号： H01L23/52 , H01L23/48
CPC分类号： H01L21/76807 , H01L21/2855 , H01L21/3144 , H01L21/31629 , H01L21/76814 , H01L21/76826 , H01L21/76831 , H01L21/76882 , H01L2924/0002 , H01L2924/00
摘要： A method for forming conductive contacts and interconnects in a semiconductor structure, and the resulting conductive components are provided. In particular, the method is used to fabricate single or dual damascene copper contacts and interconnects in integrated circuits such as memory devices and microprocessor.

84. 发明申请

US20060264064A1 Zirconium-doped tantalum oxide films 有权
标题翻译：掺锆氧化钽薄膜
公开(公告)号：US20060264064A1
公开(公告)日：2006-11-23
申请号：US11493112
申请日：2006-07-26
申请人： Kie Ahn , Leonard Forbes
发明人： Kie Ahn , Leonard Forbes
IPC分类号： H01L21/31
CPC分类号： H01L21/0228 , C23C16/405 , C23C16/45529 , C23C16/45531 , H01L21/02183 , H01L21/02189 , H01L21/02194 , H01L21/02321 , H01L21/3141 , H01L21/31637 , H01L21/31641
摘要： Dielectric layers containing a zirconium-doped tantalum oxide layer, where the zirconium-doped tantalum oxide layer is arranged as a structure of one or more monolayers of tantalum oxide doped with zirconium, provide an insulating layer in a variety of structures for use in a wide range of electronic devices.
摘要翻译：含有锆掺杂钽氧化物层的介电层，其中锆掺杂的钽氧化物层被布置为掺杂有锆的一个或多个单层钽氧化物的结构，提供了用于广泛的各种结构的绝缘层电子设备范围。

85. 发明申请

US20060237771A1 Flash memory device having a graded composition, high dielectric constant gate insulator 有权
标题翻译：具有渐变组成的闪存器件，高介电常数栅极绝缘体
公开(公告)号：US20060237771A1
公开(公告)日：2006-10-26
申请号：US11114403
申请日：2005-04-26
申请人： Leonard Forbes , Kie Ahn
发明人： Leonard Forbes , Kie Ahn
IPC分类号： H01L29/788
CPC分类号： H01L27/11517 , H01L21/8239 , H01L27/11563 , H01L29/513 , H01L29/7881
摘要： A graded composition, high dielectric constant gate insulator is formed between a substrate and floating gate in a flash memory cell transistor. The gate insulator is comprised of amorphous germanium or a graded composition of germanium carbide and silicon carbide. If the composition of the gate insulator is closer to silicon carbide near the substrate, the electron barrier for hot electron injection will be lower. If the gate insulator is closer to the silicon carbide near the floating gate, the tunnel barrier can be lower at the floating gate.
摘要翻译：在闪速存储单元晶体管中的衬底和浮置栅极之间形成分级成分，高介电常数栅极绝缘体。栅极绝缘体由无定形锗或碳化锗和碳化硅的分级组成构成。如果栅极绝缘体的组成更靠近基板附近的碳化硅，则热电子注入的电子势垒将更低。如果栅极绝缘体靠近浮动栅极附近的碳化硅，隧道势垒可以在浮动栅极处较低。

86. 发明申请

US20060237764A1 LANTHANIDE DOPED TiOx DIELECTRIC FILMS 有权
标题翻译： LANTHANIDE DOPED TiOx电介质膜
公开(公告)号：US20060237764A1
公开(公告)日：2006-10-26
申请号：US11427569
申请日：2006-06-29
申请人： Kie Ahn , Leonard Forbes
发明人： Kie Ahn , Leonard Forbes
IPC分类号： H01L29/94 , H01L27/108 , H01L29/76 , H01L31/119
CPC分类号： H01L21/02194 , C23C16/40 , C23C16/405 , C23C16/45531 , H01L21/02186 , H01L21/02192 , H01L21/0228 , H01L21/28185 , H01L21/28194 , H01L21/3115 , H01L21/31604 , H01L21/31683 , H01L29/513 , H01L29/517 , H01L29/518
摘要： A dielectric film containing lanthanide doped TiOx and a method of fabricating such a dielectric film produce a reliable dielectric layer having an equivalent oxide thickness thinner than attainable using SiO2. The lanthanide doped TiOx dielectric layer is arranged as a layered structure of one or more monolayers of the lanthanide doped TiOx. The dopant may be selected from a group consisting of Nd, Tb, and Dy.
摘要翻译：含有镧系元素掺杂TiO 2的电介质膜和制造这种电介质膜的方法产生可靠的电介质层，该电介质层的等效氧化物厚度比使用SiO 2可获得的薄。掺杂镧系元素的TiO 2 x电介质层被布置为掺杂镧系元素的TiO 2的一个或多个单层的层状结构。掺杂剂可以选自Nd，Tb和Dy组成的组。

87. 发明申请

US20060231886A1 Programmable array logic or memory with p-channel devices and asymmetrical tunnel barriers 有权
公开(公告)号：US20060231886A1
公开(公告)日：2006-10-19
申请号：US11471008
申请日：2006-06-20
申请人： Leonard Forbes , Jerome Eldridge , Kie Ahn
发明人： Leonard Forbes , Jerome Eldridge , Kie Ahn
IPC分类号： H01L29/76
CPC分类号： H01L27/11556 , G11C16/0416 , H01L27/115 , H01L29/51 , H01L29/511 , H01L29/7881 , H01L29/7885
摘要： Structures and methods for programmable array type logic and/or memory with p-channel devices and asymmetrical low tunnel barrier intergate insulators are provided. The programmable array type logic and/or memory devices include p-channel non-volatile memory which has a first source/drain region and a second source/drain region separated by a p-type channel region in an n-type substrate. A floating gate opposing the p-type channel region and is separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by an asymmetrical low tunnel barrier intergate insulator. The asymmetrical low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of Al2O3, Ta2O5, TiO2, ZrO2, Nb2O5, SrBi2Ta2O3, SrTiO3, PbTiO3, and PbZrO3. The floating gate includes a polysilicon floating gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator. And, the control gate includes a polysilicon control gate having a metal layer, having a different work function from the metal layer formed on the floating gate, formed thereon in contact with the low tunnel barrier intergate insulator.

88. 发明申请

US20060223337A1 Atomic layer deposited titanium silicon oxide films 失效
标题翻译：原子层沉积钛氧化硅薄膜
公开(公告)号：US20060223337A1
公开(公告)日：2006-10-05
申请号：US11093104
申请日：2005-03-29
申请人： Kie Ahn , Leonard Forbes
发明人： Kie Ahn , Leonard Forbes
IPC分类号： H01L21/31
CPC分类号： H01L21/0228 , C23C16/401 , C23C16/45531 , H01L21/02153 , H01L21/022 , H01L21/28167 , H01L21/28194 , H01L21/3141 , H01L21/3142 , H01L21/31604 , H01L21/31608 , H01L28/40 , H01L29/513 , H01L29/517 , H01L29/78
摘要： A dielectric layer containing an atomic layer deposited titanium silicon oxide film disposed in an integrated circuit and a method of fabricating such a dielectric layer provide a dielectric layer for use in a variety of electronic devices. Embodiments include forming titanium silicates and/or mixtures of titanium oxide and silicon oxides as dielectric layers in devices in an integrated circuit. In an embodiment, a titanium silicon oxide film is formed by depositing titanium oxide by atomic layer deposition and silicon oxide by atomic layer deposition onto a substrate surface. Embodiments include structures for capacitors, transistors, memory devices, and electronic systems with dielectric layers containing an atomic layer deposited titanium silicon oxide film, and methods for forming such structures.
摘要翻译：包含设置在集成电路中的原子层沉积的钛氧化硅膜的电介质层和制造这种电介质层的方法提供用于各种电子器件的电介质层。实施例包括在集成电路的器件中形成硅酸钛和/或二氧化钛和氧化硅的混合物作为电介质层。在一个实施方案中，通过原子层沉积将氧化钛和原子层沉积的氧化硅沉积在基底表面上形成钛氧化硅膜。实施例包括用于电容器，晶体管，存储器件和具有包含原子层沉积的钛氧化硅膜的电介质层的电子系统的结构，以及用于形成这种结构的方法。

89. 发明申请

US20060208335A1 Films deposited at glancing incidence for multilevel metallization 失效
公开(公告)号：US20060208335A1
公开(公告)日：2006-09-21
申请号：US11406186
申请日：2006-04-18
申请人： Kie Ahn , Leonard Forbes
发明人： Kie Ahn , Leonard Forbes
IPC分类号： H01L29/00
CPC分类号： H01L28/82 , C23C14/10 , C23C14/226 , H01L21/02164 , H01L21/02203 , H01L21/02263 , H01L21/31695 , H01L23/5222 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Systems, devices and methods are provided to improve performance of integrated circuits by providing a low-k insulator. One aspect is an integrated circuit insulator structure that includes a vapor-deposited dielectric material. The dielectric material has a predetermined microstructure formed using a glancing angle deposition (GLAD) process. The microstructure includes columnar structures that provide a porous dielectric material. One aspect is a method of forming a low-k insulator structure. In one embodiment, a predetermined vapor flux incidence angle θ is set with respect to a normal vector for a substrate surface so as to promote a dielectric microstructure with individual columnar structures. Vapor deposition and substrate motion are coordinated so as to form columnar structures in a predetermined shape. Other aspects are provided herein.

90. 发明申请

US20060183271A1 High density stepped, non-planar nitride read only memory 审中-公开
公开(公告)号：US20060183271A1
公开(公告)日：2006-08-17
申请号：US11399874
申请日：2006-04-07
申请人： Leonard Forbes , Kie Ahn
发明人： Leonard Forbes , Kie Ahn
IPC分类号： H01L21/82
CPC分类号： G11C16/0475 , H01L27/115 , H01L27/11568
摘要： A non-planar, stepped NROM array is comprised of cells formed in trenches and on pillars that are etched into a substrate. Each cell has a plurality of charge storage regions in its nitride layer and a pair of source/drain regions that are shared with adjacent cells in a column. The source/drain regions, formed in the pillar/trench sidewalls, couple the column cells serially into bitlines. The rows of the array are each coupled by a wordline. A second set of trenches separates the columns of cells.

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