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1. 发明申请

US20070195608A1 Germanium-silicon-carbide floating gates in memories 审中-公开
标题翻译：锗 - 碳化硅浮动门在回忆中
公开(公告)号：US20070195608A1
公开(公告)日：2007-08-23
申请号：US11731255
申请日：2007-03-30
申请人： Leonard Forbes , Kie Ahn
发明人： Leonard Forbes , Kie Ahn
IPC分类号： G11C16/04
CPC分类号： H01L29/42324 , H01L29/40114
摘要： The use of a germanium carbide (GeC), or a germanium silicon carbide (GeSiC) layer as a floating gate material to replace heavily doped polysilicon (poly) in fabricating floating gates in EEPROM and flash memory results in increased tunneling currents and faster erase operations. Forming the floating gate includes depositing germanium-silicon-carbide in various combinations to obtain the desired tunneling current values at the operating voltage of the memory device.
摘要翻译：在EEPROM和闪速存储器中制造浮动栅极时，使用碳化锗（GeC）或锗碳化硅（GeSiC）层作为浮栅材料来代替重掺杂多晶硅（poly）导致增加的隧道电流和更快的擦除操作。形成浮栅包括以各种组合沉积锗 - 碳化硅以在存储器件的工作电压下获得所需的隧穿电流值。

2. 发明申请

US20070178635A1 Atomic layer deposition of metal oxide and/or low asymmetrical tunnel barrier interpoly insulators 有权
标题翻译：原子层沉积金属氧化物和/或低不对称隧道势垒绝缘体
公开(公告)号：US20070178635A1
公开(公告)日：2007-08-02
申请号：US11728671
申请日：2007-03-27
申请人： Jerome Eldridge , Kie Ahn , Leonard Forbes
发明人： Jerome Eldridge , Kie Ahn , Leonard Forbes
IPC分类号： H01L21/8238
CPC分类号： H01L27/11556 , G11C16/0416 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/51 , H01L29/511 , H01L29/513 , H01L29/66825 , H01L29/7885
摘要： Structures and methods for programmable array type logic and/or memory devices with asymmetrical low tunnel barrier intergate insulators are provided. The programmable array type logic and/or memory devices include non-volatile memory which has a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposing the channel region and is separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by an asymmetrical low tunnel barrier intergate insulator formed by atomic layer deposition. The asymmetrical low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of Al2O3, Ta2O5, TiO2, ZrO2, Nb2O5, SrBi2Ta2O3, SrTiO3, PbTiO3, and PbZrO3.
摘要翻译：提供了具有不对称低隧道势垒隔离绝缘子的可编程阵列型逻辑和/或存储器件的结构和方法。可编程阵列型逻辑和/或存储器件包括具有第一源极/漏极区域和由衬底中的沟道区域分开的第二源极/漏极区域的非易失性存储器。与沟道区相对的浮栅，并由栅极氧化物分离。控制门反对浮动门。控制栅极通过由原子层沉积物形成的不对称的低隧道势垒隔间绝缘体与浮动栅极分离。非对称低隧道势垒隔间绝缘体包括选自Al 2 O 3 O 3，Ta 2 O 3的金属氧化物绝缘体， 5，TiO 2，ZrO 2，Nb 2 O 5，SrBi 2 TaTiO 3，PbTiO 3 3和PbZrO 3 3，3， / SUB>。

3. 发明申请

US20070101929A1 METHODS FOR ATOMIC-LAYER DEPOSITION 失效
标题翻译：原子沉积方法
公开(公告)号：US20070101929A1
公开(公告)日：2007-05-10
申请号：US11620324
申请日：2007-01-05
申请人： Kie Ahn , Leonard Forbes
发明人： Kie Ahn , Leonard Forbes
IPC分类号： C30B28/14 , H01L21/00
CPC分类号： C23C16/45574 , C23C16/4412 , C23C16/45544 , C23C16/45565
摘要： Atomic-Layer deposition systems and methods provide a variety of electronic products. In an embodiment, a method uses an atomic-layer deposition system that includes an outer chamber, a substrate holder, and a gas-distribution fixture that engages or cooperates with the substrate holder to form an inner chamber within the outer chamber. The inner chamber has a smaller volume than the outer chamber, which leads to less time to fill and purge during cycle times for deposition of materials.
摘要翻译：原子层沉积系统和方法提供各种电子产品。在一个实施例中，一种方法使用原子层沉积系统，其包括与衬底保持器接合或协作以在外腔内形成内室的外室，衬底保持器和气体分配夹具。内室具有比外室小的体积，这导致在用于沉积材料的循环时间期间更少的填充和吹扫时间。

4. 发明申请

US20070096193A1 Non-volatile memory device with tensile strained silicon layer 有权
标题翻译：具有拉伸应变硅层的非易失性存储器件
公开(公告)号：US20070096193A1
公开(公告)日：2007-05-03
申请号：US11260339
申请日：2005-10-27
申请人： Leonard Forbes , Kie Ahn , Alan Reinberg
发明人： Leonard Forbes , Kie Ahn , Alan Reinberg
IPC分类号： H01L29/788
CPC分类号： H01L29/7883 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L2924/0002 , H01L2924/00
摘要： A non-volatile memory device has improved performance from a stressed, silicon nitride capping layer. The device is comprised of memory cells in a substrate that have source and drain regions. A tunnel dielectric is formed over the substrate between each pair of source and drain regions. If the memory device is an NROM, a nitride charge storage layer is formed over the tunnel dielectric. If the memory device is a flash memory, a floating gate is formed over the tunnel dielectric. An inter-gate insulator and control gate are then formed over the charge storage layer. The stressed, silicon nitride capping layer is formed over the control gate.
摘要翻译：非易失性存储器件具有来自受压氮化硅覆盖层的性能的改善。该器件由具有源极和漏极区域的衬底中的存储器单元组成。在每对源极和漏极区之间的衬底上形成隧道电介质。如果存储器件是NROM，则在隧道电介质上形成氮化物电荷存储层。如果存储器件是闪速存储器，则在隧道电介质上形成浮栅。然后在电荷存储层上形成栅极间绝缘体和控制栅极。应力的氮化硅覆盖层形成在控制栅上。

5. 发明申请

US20070090441A1 TITANIUM ALUMINUM OXIDE FILMS 有权
标题翻译：钛氧化铝薄膜
公开(公告)号：US20070090441A1
公开(公告)日：2007-04-26
申请号：US11566042
申请日：2006-12-01
申请人： KIE AHN , Leonard Forbes
发明人： KIE AHN , Leonard Forbes
IPC分类号： H01L29/94
CPC分类号： H01L21/0228 , C23C16/0281 , C23C16/40 , C23C16/45531 , H01L21/02178 , H01L21/02186 , H01L21/02194 , H01L21/022 , H01L21/02337 , H01L21/28229 , H01L21/3141 , H01L21/3142 , H01L29/513 , H01L29/517
摘要： A dielectric layer containing an insulating metal oxide film having multiple metal components and a method of fabricating such a dielectric layer produce a reliable dielectric layer for use in a variety of electronic devices. Embodiments include a titanium aluminum oxide film structured as one or more monolayers. Embodiments also include structures for capacitors, transistors, memory devices, and electronic systems with dielectric layers containing a titanium aluminum oxide film.
摘要翻译：包含具有多个金属成分的绝缘金属氧化物膜的介质层和制造这种电介质层的方法产生用于各种电子器件的可靠的介电层。实施方案包括被构造为一个或多个单层的钛氧化铝膜。实施例还包括用于电容器，晶体管，存储器件和具有包含钛氧化铝膜的电介质层的电子系统的结构。

6. 发明申请

US20070048989A1 Atomic layer deposition of GdScO3 films as gate dielectrics 有权
标题翻译： GdScOsub3薄膜的原子层沉积作为栅极电介质
公开(公告)号：US20070048989A1
公开(公告)日：2007-03-01
申请号：US11215507
申请日：2005-08-30
申请人： Kie Ahn , Leonard Forbes
发明人： Kie Ahn , Leonard Forbes
IPC分类号： H01L21/3205 , H01L21/336 , H01L21/31 , H01L21/8242
CPC分类号： H01L21/02192 , C23C16/40 , C23C16/45529 , C23C16/4554 , C23C16/45553 , H01L21/022 , H01L21/0228 , H01L21/28194 , H01L21/28273 , H01L21/28282 , H01L21/3142 , H01L21/31604 , H01L28/40 , H01L29/513 , H01L29/517 , H01L29/788 , H01L29/792
摘要： The use of atomic layer deposition (ALD) to form a nanolaminate dielectric of gadolinium oxide (Gd2O3) and scandium oxide (Sc2O3) acting as a single dielectric layer with a formula of GdScO3, and a method of fabricating such a dielectric layer, is described that produces a reliable structure with a high dielectric constant (high k) for use in a variety of electronic devices. The dielectric structure is formed by depositing gadolinium oxide by atomic layer deposition onto a substrate surface using precursor chemicals, followed by depositing scandium oxide onto the substrate using precursor chemicals, and repeating to form the thin laminate structure. Such a dielectric may be used as gate insulator of a MOSFET, a capacitor dielectric in a DRAM, as tunnel gate insulators in flash memories, or as a NROM dielectric, because the high dielectric constant (high k) of the film provides the functionality of a much thinner silicon dioxide film.
摘要翻译：使用原子层沉积（ALD）形成氧化钆（Gd 2 O 3 O 3）和氧化钪（Sc 2 O 3）的纳米层间电介质， O 3 3），以及制造这种电介质层的方法，其制造具有高的可靠结构介电常数（高k）用于各种电子设备。通过使用前体化学品，通过原子层沉积将氧化钆沉积到衬底表面上，然后使用前体化学品将氧化钪沉积到衬底上并重复形成薄层压结构，形成电介质结构。这种电介质可以用作MOSFET的栅绝缘体，DRAM中的电容器电介质，作为闪存中的隧道栅绝缘体，或者作为NROM电介质，因为膜的高介电常数（高k）提供了更薄的二氧化硅膜。

7. 发明申请

US20070045752A1 Self aligned metal gates on high-K dielectrics 审中-公开
标题翻译：高K电介质上的自对准金属栅极
公开(公告)号：US20070045752A1
公开(公告)日：2007-03-01
申请号：US11451712
申请日：2006-06-13
申请人： Leonard Forbes , Kie Ahn
发明人： Leonard Forbes , Kie Ahn
IPC分类号： H01L29/76 , H01L29/94 , H01L31/00
CPC分类号： H01L29/517 , H01L21/28114 , H01L29/40114 , H01L29/42376 , H01L29/495 , H01L29/6653 , H01L29/66545 , Y10S438/926
摘要： A method for forming a transistor including a self aligned metal gate is provided. According to various method embodiments, a high-k gate dielectric is formed on a substrate and a sacrificial carbon gate is formed on the gate dielectric. Sacrificial carbon sidewall spacers are formed adjacent to the sacrificial carbon gate, and source/drain regions for the transistor are formed using the sacrificial carbon sidewall spacers to define the source/drain regions. The sacrificial carbon sidewall spacers are replaced with non-carbon sidewall spacers, and the sacrificial carbon gate is replaced with a desired metal gate material to provide the desired metal gate material on the gate dielectric. Various embodiments form source/drain extensions after removing the carbon sidewall spacers and before replacing with non-carbon sidewall spacers. An etch barrier is used in various embodiments to separate the sacrificial carbon gate from the sacrificial carbon sidewall spacers. Other aspects and embodiments are provided herein.
摘要翻译：提供一种形成包括自对准金属栅极的晶体管的方法。根据各种方法实施例，在衬底上形成高k栅极电介质，并且在栅极电介质上形成牺牲碳栅。牺牲碳侧壁间隔件邻近牺牲碳栅形成，并且使用牺牲碳侧壁间隔物形成用于晶体管的源/漏区，以限定源极/漏极区。牺牲碳侧壁间隔物被非碳侧壁间隔物代替，并且牺牲碳栅被替换为期望的金属栅极材料以在栅极电介质上提供所需的金属栅极材料。各种实施例在去除碳侧壁间隔物之后并且在用非碳侧壁间隔物替换之前形成源极/漏极扩展。在各种实施例中使用蚀刻阻挡层将牺牲碳栅极与牺牲碳侧壁间隔物分离。本文提供了其它方面和实施例。

8. 发明申请

US20070037415A1 Lanthanum hafnium oxide dielectrics 有权
标题翻译：镧氧化铪电介质
公开(公告)号：US20070037415A1
公开(公告)日：2007-02-15
申请号：US11584229
申请日：2006-10-20
申请人： Kie Ahn , Leonard Forbes
发明人： Kie Ahn , Leonard Forbes
IPC分类号： H01L21/00
CPC分类号： H01L21/02181 , C23C16/40 , C23C16/45531 , C23C16/45553 , H01L21/02194 , H01L21/022 , H01L21/0228 , H01L21/3141 , H01L21/31645 , H01L2924/0002 , H01L2924/00
摘要： Dielectric layers containing a lanthanum hafnium oxide layer, where the lanthanum hafnium oxide layer is arranged as a structure of one or more monolayers, provide an insulating layer in a variety of structures for use in a wide range of electronic devices.
摘要翻译：含有镧氧化铪层的介质层，其中氧化镧镧氧化物层被布置为一个或多个单层的结构，提供了用于各种电子器件的各种结构的绝缘层。

9. 发明申请

US20070010061A1 Metal-substituted transistor gates 失效
标题翻译：金属取代晶体管栅极
公开(公告)号：US20070010061A1
公开(公告)日：2007-01-11
申请号：US11444993
申请日：2006-06-01
申请人： Leonard Forbes , Paul Farrar , Kie Ahn
发明人： Leonard Forbes , Paul Farrar , Kie Ahn
IPC分类号： H01L21/336
CPC分类号： H01L21/02164 , H01L21/02175 , H01L21/02178 , H01L21/02181 , H01L21/02186 , H01L21/02192 , H01L21/02194 , H01L21/0228 , H01L21/28079 , H01L21/28194 , H01L21/28229 , H01L21/3142 , H01L21/31641 , H01L21/31645 , H01L29/513 , H01L29/517 , H01L29/66545 , H01L2924/0002 , Y10S438/926 , Y10T428/12354 , H01L2924/00
摘要： One aspect of this disclosure relates to a method for forming an integrated circuit. According to various embodiments of the method, a plurality of transistors is formed. For each transistor, a gate dielectric is formed on a substrate, a substitutable structure is formed on the gate dielectric, and source/drain regions for the transistor are formed. At least two substitution processes are performed. Each substitution process includes substituting a desired gate material for the substitutable structure. Other aspects and embodiments are provided herein.
摘要翻译：本公开的一个方面涉及一种用于形成集成电路的方法。根据该方法的各种实施例，形成多个晶体管。对于每个晶体管，在衬底上形成栅极电介质，在栅极电介质上形成可取代的结构，并且形成用于晶体管的源/漏区。至少执行两个替换过程。每个取代过程包括用期望的栅极材料代替可替代结构。本文提供了其它方面和实施例。

10. 发明申请

US20060292857A1 METHODS FOR MAKING INTEGRATED-CIRCUIT WIRING FROM COPPER, SILVER, GOLD, AND OTHER METALS 有权
标题翻译：从铜，银，金和其他金属制造集成电路接线的方法
公开(公告)号：US20060292857A1
公开(公告)日：2006-12-28
申请号：US11458975
申请日：2006-07-20
申请人： Kie Ahn , Leonard Forbes
发明人： Kie Ahn , Leonard Forbes
IPC分类号： H01L21/4763
CPC分类号： H01L21/76852 , H01L21/28512 , H01L21/76856 , H01L21/76885
摘要： Integrated circuits, the key components in thousands of electronic and computer products, include interconnected networks of electrical components. The components are typically wired, or interconnected, together with aluminum wires. In recent years, researchers have begun using copper instead of aluminum to form integrated-circuit wiring, because copper offers lower electrical resistance and better reliability at smaller dimensions. However, copper typically requires use of a diffusion barrier to prevent it from contaminating other parts of an integrated circuit. Unfortunately, typical diffusion barrier materials add appreciable resistance to the copper wiring, and thus negate some advantages of using copper. Moreover, conventional methods of forming the copper wiring are costly and time consuming. Accordingly, the inventors devised one or more exemplary methods for making integrated-circuit wiring from materials, such as copper-, silver-, and gold-based metals. One exemplary method removes two or more masks in a single removal procedure, forms a low-resistance diffusion barrier on two or more wiring levels in a single formation procedure, and fills insulative material around and between two or more wiring levels in a single fill procedure. This and other embodiments hold the promise of simplifying fabrication of integrated-circuit wiring dramatically.
摘要翻译：集成电路是成千上万种电子和计算机产品的关键组件，包括电气组件的互连网络。组件通常与铝线连接或互连。近年来，研究人员已经开始使用铜而不是铝来形成集成电路布线，因为铜在较小的尺寸下具有更低的电阻和更好的可靠性。然而，铜通常需要使用扩散阻挡层以防止其污染集成电路的其它部分。不幸的是，典型的扩散阻挡材料对铜布线增加了显着的阻力，因此不利于使用铜的一些优点。此外，形成铜布线的常规方法是昂贵且耗时的。因此，本发明人设计了一种或多种用于从诸如铜，银和金基金属的材料制造集成电路布线的示例性方法。一种示例性方法在单个去除过程中去除两个或更多个掩模，在单个形成过程中在两个或更多个布线层上形成低电阻扩散阻挡层，并且在单个填充程序中在两个或多个布线层之间和之间填充绝缘材料。本实施例和其他实施例显然简化了集成电路布线的制造。

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