专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07361928B2 Doped aluminum oxide dielectrics 有权
标题翻译：掺杂的氧化铝电介质
公开(公告)号：US07361928B2
公开(公告)日：2008-04-22
申请号：US10808189
申请日：2004-03-24
申请人： Kie Ahn , Leonard Forbes
发明人： Kie Ahn , Leonard Forbes
IPC分类号： H01L29/12
CPC分类号： H01L21/28211 , C23C14/081 , C23C14/58 , H01L21/02145 , H01L21/02178 , H01L21/02203 , H01L21/02269 , H01L21/02321 , H01L21/02337 , H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/28229 , H01L21/28273 , H01L21/3162 , H01L21/31637 , H01L21/31641 , H01L21/31645 , H01L21/31695 , H01L27/10811 , H01L27/1085 , H01L27/10852 , H01L27/10873 , H01L27/115 , H01L28/40 , H01L28/84 , H01L29/517 , H01L29/518 , H01L29/7883 , Y10T428/249953
摘要： Doped aluminum oxide layers having a porous aluminum oxide layer and methods of their fabrication. The porous aluminum oxide layer may be formed by evaporation physical vapor deposition techniques to facilitate formation of a high-purity aluminum oxide layer. A dopant material is embedded in the pores of the porous aluminum oxide layer and subsequently converted to a dielectric form. The degree of porosity of the porous aluminum oxide layer may be controlled during formation to facilitate control of the level of doping of the doped aluminum oxide layer. Such doped aluminum oxide layers are useful as gate dielectric layers, intergate dielectric layers and capacitor dielectric layers in various integrated circuit devices.
摘要翻译：具有多孔氧化铝层的掺杂氧化铝层及其制造方法。多孔氧化铝层可以通过蒸发物理气相沉积技术形成，以便于形成高纯度的氧化铝层。掺杂剂材料嵌入在多孔氧化铝层的孔中并随后转变为电介质形式。可以在形成期间控制多孔氧化铝层的孔隙率，以便于控制掺杂的氧化铝层的掺杂水平。这种掺杂的氧化铝层可用作各种集成电路器件中的栅极电介质层，隔间电介质层和电容器介电层。

2. 发明申请

US20080067064A1 METHODS AND APPARATUS FOR MAKING INTEGRATED-CIRCUIT WIRING FROM COPPER, SILVER, GOLD, AND OTHER METALS 失效
标题翻译：从铜，银，金和其他金属制造集成电路接线的方法和装置
公开(公告)号：US20080067064A1
公开(公告)日：2008-03-20
申请号：US11861927
申请日：2007-09-26
申请人： Kie Ahn , Leonard Forbes
发明人： Kie Ahn , Leonard Forbes
IPC分类号： C23C14/00
CPC分类号： H01L21/76846 , C23C14/3471 , C23C16/517 , G02F1/13454 , H01J37/3408 , H01L21/76843 , H01L21/76856 , H01L21/76873 , H01L29/78696
摘要： In recent years, copper wiring has emerged as a promising substitute for the aluminum wiring in integrated circuits, because copper offers lower electrical resistance and better reliability at smaller dimensions than aluminum. However, use of copper typically requires forming a diffusion barrier to prevent contamination of other parts of an integrated circuit and forming a seed layer to facilitate copper plating steps. Unfortunately, conventional methods of forming the diffusion barriers and seed layers require use of separate wafer-processing chambers, giving rise to transport delays and the introduction of defect-causing particles. Accordingly, the inventors devised unique wafer-processing chambers and methods of forming barrier and seed layers. One embodiment of the wafer-processing chamber includes equipment for physical vapor deposition and equipment for chemical vapor deposition to facilitate formation of diffusion barriers and seed layers within one chamber, thereby promoting fabrication efficiency and reducing defects.
摘要翻译：近年来，由于铜在比铝更小的尺寸下具有较低的电阻和更好的可靠性，因此铜布线已经成为集成电路中铝布线的有前途的替代品。然而，铜的使用通常需要形成扩散阻挡层以防止集成电路的其它部分的污染并形成种子层以促进镀铜步骤。不幸的是，形成扩散阻挡层和种子层的常规方法需要使用单独的晶片处理室，从而导致运输延迟和引入缺陷颗粒。因此，本发明人设计了独特的晶片处理室和形成阻挡层和种子层的方法。晶片处理室的一个实施例包括用于物理气相沉积的设备和用于化学气相沉积的设备，以便于在一个室内形成扩散阻挡层和种子层，从而提高制造效率并减少缺陷。

3. 发明申请

US20070243682A1 Flash memory device having a graded composition, high dielectric constant gate insulator 有权
公开(公告)号：US20070243682A1
公开(公告)日：2007-10-18
申请号：US11811609
申请日：2007-06-11
申请人： Leonard Forbes , Kie Ahn
发明人： Leonard Forbes , Kie Ahn
IPC分类号： H01L21/336
CPC分类号： H01L27/11517 , H01L21/8239 , H01L27/11563 , H01L29/513 , H01L29/7881
摘要： A graded composition, high dielectric constant gate insulator is formed between a substrate and floating gate in a flash memory cell transistor. The gate insulator is comprised of amorphous germanium or a graded composition of germanium carbide and silicon carbide. If the composition of the gate insulator is closer to silicon carbide near the substrate, the electron barrier for hot electron injection will be lower. If the gate insulator is closer to the silicon carbide near the floating gate, the tunnel barrier can be lower at the floating gate.

4. 发明申请

US20070181931A1 HAFNIUM TANTALUM OXIDE DIELECTRICS 有权
标题翻译：高锰氧化物电介质
公开(公告)号：US20070181931A1
公开(公告)日：2007-08-09
申请号：US11735247
申请日：2007-04-13
申请人： Kie Ahn , Leonard Forbes
发明人： Kie Ahn , Leonard Forbes
IPC分类号： H01L29/94 , H01L29/00
CPC分类号： H01L21/0228 , H01L21/02181 , H01L21/02183 , H01L21/02194 , H01L21/022 , H01L21/02318 , H01L21/28194 , H01L21/28273 , H01L21/28282 , H01L21/3141 , H01L21/31637 , H01L21/31645 , H01L29/4908 , H01L29/517
摘要： A dielectric layer containing a hafnium tantalum oxide film and a method of fabricating such a dielectric layer produce a dielectric layer for use in a variety of electronic devices. Embodiments include structures for capacitors, transistors, memory devices, and electronic systems with dielectric layers containing a hafnium tantalum oxide film structured as one or more monolayers.
摘要翻译：包含铪钽氧化物膜的介电层和制造这种电介质层的方法产生用于各种电子器件的介电层。实施例包括用于电容器，晶体管，存储器件和具有包含以一个或多个单层构成的铪钽氧化物膜的电介质层的电子系统的结构。

5. 发明申请

US20070178643A1 Memory utilizing oxide-conductor nanolaminates 审中-公开
标题翻译：记忆利用氧化物导体的Nanolaminates
公开(公告)号：US20070178643A1
公开(公告)日：2007-08-02
申请号：US11217767
申请日：2005-08-31
申请人： Leonard Forbes , Kie Ahn
发明人： Leonard Forbes , Kie Ahn
IPC分类号： H01L21/336
CPC分类号： G11C11/5671 , G11C16/0416 , H01L27/115 , H01L29/42332 , H01L29/7885
摘要： Structures, systems and methods for floating gate transistors utilizing oxide-conductor nanolaminates are provided. One floating gate transistor embodiment includes a first source/drain region, a second source/drain region, and a channel region therebetween. A floating gate is separated from the channel region by a first gate oxide. The floating gate includes oxide-conductor nanolaminate layers to trap charge in potential wells formed by different electron affinities of the oxide-conductor nanolaminate layers.
摘要翻译：提供了使用氧化物导体纳米层压材料的浮栅晶体管的结构，系统和方法。一个浮栅晶体管实施例包括第一源极/漏极区域，第二源极/漏极区域和它们之间的沟道区域。浮置栅极通过第一栅极氧化物与沟道区分离。浮动栅极包括氧化物 - 导体纳米层间层，以在由氧化物 - 导体层压材料层的不同电子亲和力形成的势阱中捕获电荷。

6. 发明申请

US20070145462A1 Low tunnel barrier insulators 有权
标题翻译：低隧道隔离绝缘子
公开(公告)号：US20070145462A1
公开(公告)日：2007-06-28
申请号：US11708438
申请日：2007-02-20
申请人： Jerome Eldridge , Kie Ahn , Leonard Forbes
发明人： Jerome Eldridge , Kie Ahn , Leonard Forbes
IPC分类号： H01L29/76
CPC分类号： H01L27/11556 , G11C16/0416 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/51 , H01L29/511 , H01L29/513 , H01L29/66825 , H01L29/7885
摘要： Structures and methods for programmable array type logic and/or memory devices with asymmetrical low tunnel barrier intergate insulators are provided. The programmable array type logic and/or memory devices include non-volatile memory which has a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposing the channel region and is separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by an asymmetrical low tunnel barrier intergate insulator formed by atomic layer deposition. The asymmetrical low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of Al2O3, Ta2O5, TiO2, ZrO2, Nb2O5, SrBi2Ta2O3, SrTiO3, PbTiO3, and PbZrO3.
摘要翻译：提供了具有不对称低隧道势垒隔离绝缘子的可编程阵列型逻辑和/或存储器件的结构和方法。可编程阵列型逻辑和/或存储器件包括具有第一源极/漏极区域和由衬底中的沟道区域分开的第二源极/漏极区域的非易失性存储器。与沟道区相对的浮栅，并由栅极氧化物分离。控制门反对浮动门。控制栅极通过由原子层沉积物形成的不对称的低隧道势垒隔间绝缘体与浮动栅极分离。非对称低隧道势垒隔间绝缘体包括选自Al 2 O 3 O 3，Ta 2 O 3的金属氧化物绝缘体， 5，TiO 2，ZrO 2，Nb 2 O 5，SrBi 2 TaTiO 3，PbTiO 3 3和PbZrO 3 3，3， / SUB>。

7. 发明申请

US20070138534A1 Deposition of metal oxide and/or low asymmetrical tunnel barrier interpoly insulators 有权
标题翻译：沉积金属氧化物和/或低不对称隧道势垒绝缘子
公开(公告)号：US20070138534A1
公开(公告)日：2007-06-21
申请号：US11704458
申请日：2007-02-09
申请人： Jerome Eldridge , Kie Ahn , Leonard Forbes
发明人： Jerome Eldridge , Kie Ahn , Leonard Forbes
IPC分类号： H01L29/76
CPC分类号： H01L27/11556 , G11C16/0416 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/51 , H01L29/511 , H01L29/513 , H01L29/66825 , H01L29/7885
摘要： Structures and methods for programmable array type logic and/or memory devices with asymmetrical low tunnel barrier intergate insulators are provided. The programmable array type logic and/or memory devices include non-volatile memory which has a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposing the channel region and is separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by an asymmetrical low tunnel barrier intergate insulator formed by atomic layer deposition. The asymmetrical low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of Al2O3, Ta2O5, TiO2, ZrO2, Nb2O5, SrBi2Ta2O3, SrTiO3, PbTiO3, and PbZrO3.
摘要翻译：提供了具有不对称低隧道势垒隔离绝缘子的可编程阵列型逻辑和/或存储器件的结构和方法。可编程阵列型逻辑和/或存储器件包括具有第一源极/漏极区域和由衬底中的沟道区域分开的第二源极/漏极区域的非易失性存储器。与沟道区相对的浮栅，并由栅极氧化物分离。控制门反对浮动门。控制栅极通过由原子层沉积物形成的不对称的低隧道势垒隔间绝缘体与浮动栅极分离。非对称低隧道势垒隔间绝缘体包括选自Al 2 O 3 O 3，Ta 2 O 3的金属氧化物绝缘体， 5，TiO 2，ZrO 2，Nb 2 O 5，SrBi 2 TaTiO 3，PbTiO 3 3和PbZrO 3 3，3， / SUB>。

8. 发明申请

US20070085213A1 Selective electroless-plated copper metallization 审中-公开
标题翻译：选择性无电镀铜金属化
公开(公告)号：US20070085213A1
公开(公告)日：2007-04-19
申请号：US11639020
申请日：2006-12-14
申请人： Kie Ahn , Leonard Forbes
发明人： Kie Ahn , Leonard Forbes
IPC分类号： H01L23/48
CPC分类号： H01L21/288 , H01L21/7682 , H01L21/76852 , H01L21/76874 , H01L21/76879 , H01L21/76885 , H01L23/4821 , H01L23/5222 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Structures and methods are provided which include a selective electroless copper metallization. The present invention includes a novel methodology for forming copper vias on a substrate, including depositing a thin film seed layer of Palladium (Pd) or Copper (Cu) on a substrate to a thickness of less than 15 nanometers (nm). A number of via holes is defined above the seed layer. A layer of copper is deposited over the seed layer using electroless plating to fill the via holes to a top surface of the patterned photoresist layer. The method can be repeated any number of times, forming second, third and fourth layers of copper. The photoresist layers along with the seed layers in other regions can then be removed, such as by oxygen plasma etching, such that a chemical mechanical planarization process is avoided.
摘要翻译：提供了包括选择性无电镀铜金属化的结构和方法。本发明包括在衬底上形成铜通孔的新颖方法，包括在衬底上沉积厚度小于15纳米（nm）的钯（Pd）或铜（Cu）的薄膜晶种层。在种子层上面定义了多个通孔。使用化学镀将一层铜沉积在种子层上，以将通孔填充到图案化光致抗蚀剂层的顶表面。该方法可以重复任意次数，形成第二层，第三层和第四层铜层。然后可以例如通过氧等离子体蚀刻去除光致抗蚀剂层以及其它区域中的种子层，从而避免化学机械平面化过程。

9. 发明申请

US20070049023A1 Zirconium-doped gadolinium oxide films 审中-公开
标题翻译：锆掺杂钆氧化物膜
公开(公告)号：US20070049023A1
公开(公告)日：2007-03-01
申请号：US11215578
申请日：2005-08-29
申请人： Kie Ahn , Leonard Forbes
发明人： Kie Ahn , Leonard Forbes
IPC分类号： H01L21/44
CPC分类号： H01L21/02194 , C23C16/40 , C23C16/45529 , C23C16/45531 , C23C16/45553 , H01L21/02189 , H01L21/02192 , H01L21/022 , H01L21/0228 , H01L21/28194 , H01L21/3141 , H01L21/3142 , H01L21/823857 , H01L29/513 , H01L29/517 , H01L29/78
摘要： Electronic apparatus and methods of forming the electronic apparatus include a zirconium-doped gadolinium oxide film for use in a variety of electronic systems. The zirconium-doped gadolinium oxide film may be structured as one or more monolayers. The zirconium-doped gadolinium oxide film may be formed by atomic layer deposition.
摘要翻译：形成电子设备的电子设备和方法包括用于各种电子系统的锆掺杂氧化钆膜。锆掺杂的氧化钆膜可以被构造为一个或多个单层。锆掺杂的氧化钆膜可以通过原子层沉积形成。

10. 发明授权

US07157733B2 Floating-gate field-effect transistors having doped aluminum oxide dielectrics 有权
标题翻译：具有掺杂的氧化铝电介质的浮栅场效应晶体管
公开(公告)号：US07157733B2
公开(公告)日：2007-01-02
申请号：US11213156
申请日：2005-08-26
申请人： Kie Ahn , Leonard Forbes
发明人： Kie Ahn , Leonard Forbes
IPC分类号： H01L29/12 , H01L29/76
CPC分类号： H01L21/28211 , C23C14/081 , C23C14/58 , H01L21/02145 , H01L21/02178 , H01L21/02203 , H01L21/02269 , H01L21/02321 , H01L21/02337 , H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/28229 , H01L21/28273 , H01L21/3162 , H01L21/31637 , H01L21/31641 , H01L21/31645 , H01L21/31695 , H01L27/10811 , H01L27/1085 , H01L27/10852 , H01L27/10873 , H01L27/115 , H01L28/40 , H01L28/84 , H01L29/517 , H01L29/518 , H01L29/7883 , Y10T428/249953
摘要： Doped aluminum oxide layers having a porous aluminum oxide layer and methods of their fabrication. The porous aluminum oxide layer may be formed by evaporation physical vapor deposition techniques to facilitate formation of a high-purity aluminum oxide layer. A dopant material is embedded in the pores of the porous aluminum oxide layer and subsequently converted to a dielectric form. The degree of porosity of the porous aluminum oxide layer may be controlled during formation to facilitate control of the level of doping of the doped aluminum oxide layer. Such doped aluminum oxide layers are useful as gate dielectric layers, intergate dielectric layers and capacitor dielectric layers in various integrated circuit devices.
摘要翻译：具有多孔氧化铝层的掺杂氧化铝层及其制造方法。多孔氧化铝层可以通过蒸发物理气相沉积技术形成，以便于形成高纯度的氧化铝层。掺杂剂材料嵌入在多孔氧化铝层的孔中并随后转变为电介质形式。可以在形成期间控制多孔氧化铝层的孔隙率，以便于控制掺杂的氧化铝层的掺杂水平。这种掺杂的氧化铝层可用作各种集成电路器件中的栅极电介质层，隔间电介质层和电容器介电层。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式