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81. 发明授权

US07183142B2 FinFETs with long gate length at high density 失效
标题翻译： FinFET长栅长度为高密度
公开(公告)号：US07183142B2
公开(公告)日：2007-02-27
申请号：US10905615
申请日：2005-01-13
申请人： Brent A. Anderson , Kerry Bernstein , Edward J. Nowak
发明人： Brent A. Anderson , Kerry Bernstein , Edward J. Nowak
IPC分类号： H01L21/335
CPC分类号： H01L29/785 , H01L27/1211 , H01L29/42384 , H01L29/66795
摘要： A method of manufacturing fin-type field effect transistors (FinFETs) forms a silicon layer above a substrate, forms a mask pattern above the silicon layer using a multi-step mask formation process, patterns the silicon layer into silicon fins using the mask pattern such that the silicon fins only remain below the mask pattern, removes the mask pattern to leave the fins on the substrate, and forms gate conductors over the fins at a non-perpendicular angle to the fins.
摘要翻译：制造鳍型场效应晶体管（FinFET）的方法在衬底上形成硅层，使用多步骤掩模形成工艺在硅层上形成掩模图案，使用掩模图案将硅层图案化为硅散热片硅片仅保留在掩模图案之下，去除掩模图案以将散热片留在基板上，并且以与散热片非垂直的角度在翅片上形成栅极导体。

82. 发明申请

US20060231893A1 Hybrid crystal orientation CMOS structure for adaptive well biasing and for power and performance enhancement 有权
公开(公告)号：US20060231893A1
公开(公告)日：2006-10-19
申请号：US11107611
申请日：2005-04-15
申请人： Kerry Bernstein , Jeffrey Sleight , Min Yang
发明人： Kerry Bernstein , Jeffrey Sleight , Min Yang
IPC分类号： H01L27/12
CPC分类号： H01L27/1203 , H01L21/823807 , H01L21/823878 , H01L27/0922 , H01L27/1207
摘要： The present invention provides a semiconducting structure including a substrate having an SOI region and a bulk-Si region, wherein the SOI region and the bulk-Si region have a same or differing crystallographic orientation; an isolation region separating the SOI region from the bulk-Si region; and at least one first device located in the SOI region and at least one second device located in the bulk-Si region. The SOI region has an silicon layer atop an insulating layer. The bulk-Si region further comprises a well region underlying the second device and a contact to the well region, wherein the contact stabilizes floating body effects. The well contact is also used to control the threshold voltages of the FETs in the bulk-Si region to optimized the power and performance of circuits built from the combination of the SOI and bulk-Si region FETs.

83. 发明申请

US20050184720A1 Circuitry and methodology to establish correlation between gate dielectric test site reliability and product gate reliability 失效
标题翻译：电路和方法建立栅介质测试点可靠性与产品门可靠性之间的相关性
公开(公告)号：US20050184720A1
公开(公告)日：2005-08-25
申请号：US11088953
申请日：2005-03-24
申请人： Kerry Bernstein , Ronald Bolam , Edward Nowak , Alvin Strong , Jody Van Horn , Ernest Wu
发明人： Kerry Bernstein , Ronald Bolam , Edward Nowak , Alvin Strong , Jody Van Horn , Ernest Wu
IPC分类号： G01N27/00 , G01R27/00 , G01R31/02 , G01R31/28
CPC分类号： G01R31/2855
摘要： A method and system for predicting gate reliability. The method comprises the steps of stressing a gate dielectric test site to obtain gate dielectric test site data and using the test site data to predict gate reliability. Preferably, the test structure and the product structure are integrated in such a manner that a test site occupies some of the product area and the product itself occupies the remainder of the product area. A preferred methodology, more specifically, is as follows: (1) Test structures at start both in parallel stress mode and in ring oscillator or “product” mode; (2) Analyze the breakdown data as per the present state of the art for each of the areas based on the parallel stress mode; (3) Combine the above breakdown distributions using the area scaling to improve the confidence bounds of the Weibull slope of the cumulative distribution function; (4) Test the ring oscillators in the product mode to determine how many of the stress fails are also product fails as defined by an operational degradation; (5) Subdivide the failures to determine the relationship between the first fail, and the second fail, and the nth fail; (6) Investigate which stress fail, if not the first stress fail, is more likely to cause a product fail as defined by operational degradation; and (7) Based on the subdivision in step 5 and the results in step 6, make projection based on that fail which is most likely to cause fail. The methodology as outlined above bridges between dielectric stress fails and product degradation both in the case of each stress fail causing a product degradation, as well as in the case where more than one stress fail occurs before any product degradation occurs. And this relationship can be quantified.
摘要翻译：一种用于预测门可靠性的方法和系统。该方法包括以下步骤：施加栅极电介质测试点以获得栅极介电测试点数据，并使用测试点数据来预测栅极的可靠性。优选地，测试结构和产品结构以这样的方式集成，使得测试位置占据产品区域中的一些，并且产品本身占据产品区域的其余部分。更具体地说，优选的方法如下：（1）并联应力模式和环形振荡器或“产品”模式下的测试结构; （2）根据平行应力模式分析每个区域的现有技术状况; （3）使用面积缩放结合上述分解分布，以提高累积分布函数的威布尔斜率的置信范围; （4）在产品模式下测试环形振荡器，以确定应力失效的数量是否也是由操作退化定义的产品故障; （5）细分失败，确定第一个失败与第二个失败之间的关系，第n个失败; （6）调查哪些压力失败，如果不是第一次压力失败，更有可能导致产品按作业退化所定义的失效; 和（7）基于步骤5中的细分和步骤6中的结果，基于最可能导致失败的失败进行投影。如上所述的方法在介电应力失效和产物退化两者之间，在每个应力失效导致产物降解的情况下，以及在任何产物降解发生之前发生多于一个应力失效的情况下。这种关系可以量化。

84. 发明授权

US06577178B1 Transient gate tunneling current control 有权
标题翻译：瞬态栅极隧道电流控制
公开(公告)号：US06577178B1
公开(公告)日：2003-06-10
申请号：US10064504
申请日：2002-07-23
申请人： Kerry Bernstein , Peter E. Cottrell , Edward J. Nowak , Norman J. Rohrer , Douglas W. Stout
发明人： Kerry Bernstein , Peter E. Cottrell , Edward J. Nowak , Norman J. Rohrer , Douglas W. Stout
IPC分类号： H03K1730
CPC分类号： H03K19/00361 , H03K19/0948
摘要： A circuit includes a resistance-capacitance (RC) structure connected to a first set of transistors and a second set of transistors that perform the same logical function as the first set of transistors. The first set of transistors have thinner gate oxides than the second set of transistors. The RC structure drains an electric field from the first set of transistors, such that the first set of transistors are on only during initial transistor switching. In other words, the RC structure turns off the first set of transistors after transistor switching is completed. Also, the first set of transistors and the second set of transistors share common inputs and outputs. The first set of transistors exhibit higher tunneling currents than the second set of transistors. The thinner gate oxides of the first set of transistors cause the first set of transistors to exhibit higher device currents than the second set of transistors. The RC structure includes a capacitor connected to a gate of the first set of transistors and a resistor connected to the capacitor and to ground.
摘要翻译：电路包括连接到第一组晶体管的电阻 - 电容（RC）结构和执行与第一组晶体管相同的逻辑功能的第二组晶体管。第一组晶体管具有比第二组晶体管更薄的栅极氧化物。 RC结构从第一组晶体管引出电场，使得第一组晶体管仅在初始晶体管切换期间导通。换句话说，在晶体管切换完成之后，RC结构关闭第一组晶体管。此外，第一组晶体管和第二组晶体管共享公共输入和输出。第一组晶体管表现出比第二组晶体管更高的隧穿电流。第一组晶体管的较薄的栅极氧化物导致第一组晶体管表现出比第二组晶体管更高的器件电流。 RC结构包括连接到第一组晶体管的栅极的电容器和连接到电容器并接地的电阻器。

85. 发明授权

US06509725B1 Self-regulating voltage divider for series-stacked voltage rails 失效
标题翻译：用于串联堆叠电压轨的自调节分压器
公开(公告)号：US06509725B1
公开(公告)日：2003-01-21
申请号：US09683025
申请日：2001-11-09
申请人： Kerry Bernstein , Peter Edwin Cottrell , Roger Paul Gregor , Stephen V. Kosonocky , Edward Joseph Nowak
发明人： Kerry Bernstein , Peter Edwin Cottrell , Roger Paul Gregor , Stephen V. Kosonocky , Edward Joseph Nowak
IPC分类号： G05F304
CPC分类号： G06F1/26
摘要： A system and method for achieving self-regulated voltage division among multiple serially stacked voltage planes. The system of the present invention is incorporated within a source voltage plane having a source supply node for supplying current and a source ground node for sinking current supplied therefrom. An intermediate voltage supply node is coupled between the source supply voltage node and the source ground node for dividing the source voltage plane into a plurality of intermediate voltage planes. The self-regulated voltage divider of the present invention includes a first capacitor and a second capacitor that are each controllably coupled between either the source supply voltage node and the intermediate voltage supply node, or between the intermediate voltage supply node and the source ground node, such that a voltage level balance is achieved among the intermediate voltage planes.
摘要翻译：一种用于在多个串联电压平面之间实现自调节电压分配的系统和方法。本发明的系统结合在具有用于提供电流的源电源节点的源极电压平面和用于吸收从其提供的电流的源极接地节点。中间电压供应节点耦合在源电源电压节点和源极接地节点之间，用于将源极电压平面分成多个中间电压平面。本发明的自调节分压器包括第一电容器和第二电容器，每个可控制地耦合在源电源电压节点和中间电压供应节点之间，或者在中间电压供应节点和源极接地节点之间，使得在中间电压平面之间实现电压电平平衡。

86. 发明授权

US06191628B1 Circuit for controlling the slew rate of a digital signal 失效
标题翻译：用于控制数字信号的转换速率的电路
公开(公告)号：US06191628B1
公开(公告)日：2001-02-20
申请号：US09224763
申请日：1999-01-04
申请人： Kerry Bernstein , Edward J. Nowak , Norman J. Rohrer
发明人： Kerry Bernstein , Edward J. Nowak , Norman J. Rohrer
IPC分类号： H03K512
CPC分类号： H03K19/00323 , H03K5/131 , H03K5/133 , H03K19/00361 , H03K2005/00071
摘要： A circuit for selectively controlling the slew rate of a signal on a data line. A capacitor is connected at one end to a common terminal of a power supply and to a switching circuit. The switching circuit advantageously connects the capacitor to the data line in response to a control pulse, capacitively loading the data line so that slew rate is decreased. When the control pulse assumes a different state, the capacitor is connected by the switching circuit to a terminal of a power supply, and acts as a decoupling capacitor. The dual role of the capacitor provides for efficient circuit layout by utilizing one component in two functions.
摘要翻译：用于选择性地控制数据线上的信号的转换速率的电路。电容器一端连接到电源的公共端子和开关电路。开关电路有利地将电容器响应于控制脉冲连接到数据线，电容性地加载数据线，使得转换速率降低。当控制脉冲处于不同状态时，电容器通过开关电路连接到电源的端子，并用作去耦电容器。电容器的双重作用通过利用两个功能中的一个组件来提供有效的电路布局。

87. 发明授权

US08576599B2 Multi-wafer 3D CAM cell 失效
标题翻译：多晶圆3D CAM单元
公开(公告)号：US08576599B2
公开(公告)日：2013-11-05
申请号：US13364607
申请日：2012-02-02
申请人： Jagreet S. Atwal , Joseph S. Barnes , Kerry Bernstein , Robert J. Bucki , Jason A. Cox
发明人： Jagreet S. Atwal , Joseph S. Barnes , Kerry Bernstein , Robert J. Bucki , Jason A. Cox
IPC分类号： G11C15/00 , G11C5/14
CPC分类号： H01L25/18 , G06F12/0895 , G06F12/1027 , G11C15/00 , G11C15/04 , H01L27/1203 , H01L2225/06541 , H01L2924/0002 , H01L2924/00
摘要： A multi-wafer CAM cell in which the negative effects of increased travel distance have been substantially reduced is provided. The multi-wafer CAM cell is achieved in the present invention by utilizing three-dimensional integration in which multiple active circuit layers are vertically stack and vertically aligned interconnects are employed to connect a device from one of the stacked layers to another device in another stack layer. By vertically stacking multiple active circuit layers with vertically aligned interconnects, each compare port of the inventive CAM cell can be implemented on a separate layer above or below the primary data storage cell. This allows the multi-wafer CAM structure to be implemented within the same area footprint as a standard Random Access Memory (RAM) cell, minimizing data access and match compare delays.
摘要翻译：提供了一种多晶圆CAM单元，其中增加行程距离的负面影响已经大大减少。本发明通过利用三维积分实现多晶片CAM单元，其中多个有源电路层是垂直堆叠的并且垂直排列的互连件用于将来自堆叠层之一的器件连接到另一堆叠层中的另一器件。通过垂直堆叠具有垂直排列的互连的多个有源电路层，可以在主数据存储单元上方或下方的单独的层上实现本发明的CAM单元的每个比较端口。这允许多晶片CAM结构在与标准随机存取存储器（RAM）单元相同的区域覆盖范围内实现，从而最小化数据访问并匹配比较延迟。

88. 发明授权

US08487427B2 Assembly including plural through wafer vias, method of cooling the assembly and method of fabricating the assembly 有权
标题翻译：组装包括通过晶片通孔的多个通孔，冷却组件的方法和制造组件的方法
公开(公告)号：US08487427B2
公开(公告)日：2013-07-16
申请号：US12544344
申请日：2009-08-20
申请人： Kerry Bernstein , Thomas Brunschwiler , Bruno Michel
发明人： Kerry Bernstein , Thomas Brunschwiler , Bruno Michel
IPC分类号： H01L23/24
CPC分类号： H01L23/49827 , H01L23/46 , H01L23/473 , H01L25/0657 , H01L2224/16 , H01L2225/06541 , H01L2225/06589 , H01L2924/15159 , H01L2924/3011
摘要： An assembly includes a chip including an integrated circuit, a casing including an integrated circuit and having an upper portion formed on a side of the chip and lower portion formed on another side of the chip, plural through-wafer vias (TWVs) for electrically connecting the integrated circuit of the chip and the integrated circuit of the casing, and a card connected to the casing for electrically connecting the casing to a system board.
摘要翻译：一种组件，包括集成电路的芯片，包括集成电路的壳体，并且具有形成在芯片的一侧的上部和形成在芯片的另一侧的下部，用于电连接的多个贯通晶片通孔（TWV）芯片的集成电路和壳体的集成电路，以及连接到壳体的卡，用于将壳体电连接到系统板。

89. 发明授权

US08294149B2 Test structure and methodology for three-dimensional semiconductor structures 有权
标题翻译：三维半导体结构的测试结构和方法
公开(公告)号：US08294149B2
公开(公告)日：2012-10-23
申请号：US11935724
申请日：2007-11-06
申请人： Kerry Bernstein , Jerome L. Cann , Christopher M. Durham , Paul D. Kartschoke , Peter J. Klim , Donald L. Wheater
发明人： Kerry Bernstein , Jerome L. Cann , Christopher M. Durham , Paul D. Kartschoke , Peter J. Klim , Donald L. Wheater
IPC分类号： H01L23/58
CPC分类号： H01L22/32 , H01L21/4846 , H01L21/6835 , H01L21/76898 , H01L23/49827 , H01L24/11 , H01L24/13 , H01L25/0657 , H01L25/50 , H01L2221/6835 , H01L2224/13005 , H01L2224/16 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06596 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079
摘要： A plurality of peripheral test structure substrate (PTSS) through vias is formed within a peripheral test structure substrate. A peripheral test structure layer and at least one functional layer are formed on one side of the plurality of the PTSS through vias. The other side of the plurality of the PTSS through vias is exposed throughout fabrication of the peripheral test structure layer and the at least one functional layer to provide access points for testing functionality of the various layers throughout the manufacturing sequence. C4 bonding may be performed after manufacture of all of the at least one functional layer is completed. A 3D assembly carrier or a C4 carrier substrate is not required since the peripheral test structure substrate has sufficient mechanical strength to support the peripheral test structure layer and the at least one functional layer.
摘要翻译：在外围测试结构衬底内形成通孔的多个外围测试结构衬底（PTSS）。周边测试结构层和至少一个功能层通过通孔形成在多个PTSS的一侧上。多个PTSS通孔中的另一侧在外围测试结构层和至少一个功能层的制造过程中暴露出来，以提供用于在整个制造顺序中测试各个层的功能性的接入点。可以在完成所有至少一个功能层的所有制造之后执行C4键合。不需要3D组装载体或C4载体衬底，因为外围测试结构衬底具有足够的机械强度以支撑外围测试结构层和至少一个功能层。

90. 发明授权

US08250303B2 Adaptive linesize in a cache 失效
标题翻译：自适应在缓存中进行排序
公开(公告)号：US08250303B2
公开(公告)日：2012-08-21
申请号：US12570440
申请日：2009-09-30
申请人： Kerry Bernstein , Moinuddin K. Qureshi
发明人： Kerry Bernstein , Moinuddin K. Qureshi
IPC分类号： G06F13/00 , G06F12/00
CPC分类号： G06F12/0886 , G06F12/0864 , G06F2212/1016 , G06F2212/502
摘要： A mechanism is provided in a cache for emulating larger linesize in a substrate with smaller linesize using gang fetching and gang replacement. Gang fetching fetches multiple lines on a cache miss to ensure that all smaller lines that make up the larger line are resident in cache at the same time. Gang replacement evicts all smaller lines in cache that would have been evicted had the cache linesize been larger. The mechanism provides adaptive linesize using set dueling by dynamically selecting between multiple linsizes depending on which linesize performs the best at runtime. Set dueling dedicates a portion of sets of the cache to always use smaller linesize and dedicates one or more portions of the sets of cache to always emulate larger linesizes. One or more counters keep track of which linesize has the best performance. The cache uses that linesize for the remainder of the sets.
摘要翻译：在缓存中提供了一种机制，用于在使用帮派取出和帮派替换的较小线条模拟衬底中较大的线条化。 Gang提取在高速缓存未命中获取多行，以确保组成较大行的所有较小行同时驻留在缓存中。如果缓存线条化较大，Gang替换会将缓存中的所有较小的行排除在被驱逐之后。该机制通过根据哪些linesize在运行时执行最好的多个linsizes之间的动态选择，提供使用集合决策的自适应线性化。设置决斗专用于缓存的一部分，以始终使用较小的线条化，并且专用于高速缓存集中的一个或多个部分来始终模拟较大的线条。一个或多个计数器跟踪哪些linesize具有最佳性能。缓存使用其余集合的linesize。

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