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1. 发明申请

US20110078382A1 Adaptive Linesize in a Cache 失效
标题翻译：缓存中的自适应线性化
公开(公告)号：US20110078382A1
公开(公告)日：2011-03-31
申请号：US12570440
申请日：2009-09-30
申请人： Kerry Bernstein , Moinuddin K. Qureshi
发明人： Kerry Bernstein , Moinuddin K. Qureshi
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0886 , G06F12/0864 , G06F2212/1016 , G06F2212/502
摘要： A mechanism is provided in a cache for emulating larger linesize in a substrate with smaller linesize using gang fetching and gang replacement. Gang fetching fetches multiple lines on a cache miss to ensure that all smaller lines that make up the larger line are resident in cache at the same time. Gang replacement evicts all smaller lines in cache that would have been evicted had the cache linesize been larger. The mechanism provides adaptive linesize using set dueling by dynamically selecting between multiple linsizes depending on which linesize performs the best at runtime. Set dueling dedicates a portion of sets of the cache to always use smaller linesize and dedicates one or more portions of the sets of cache to always emulate larger linesizes. One or more counters keep track of which linesize has the best performance. The cache uses that linesize for the remainder of the sets.
摘要翻译：在缓存中提供了一种机制，用于在使用帮派取出和帮派替换的较小线条模拟衬底中较大的线条化。 Gang提取在高速缓存未命中获取多行，以确保组成较大行的所有较小行同时驻留在缓存中。如果缓存线条化较大，Gang替换会将缓存中的所有较小的行排除在被驱逐之后。该机制通过根据哪些linesize在运行时执行最好的多个linsizes之间的动态选择，提供使用集合决策的自适应线性化。设置决斗专用于缓存的一部分，以始终使用较小的线条化，并且专用于高速缓存集中的一个或多个部分来始终模拟较大的线条。一个或多个计数器跟踪哪些linesize具有最佳性能。缓存使用其余集合的linesize。

2. 发明授权

US08250303B2 Adaptive linesize in a cache 失效
标题翻译：自适应在缓存中进行排序
公开(公告)号：US08250303B2
公开(公告)日：2012-08-21
申请号：US12570440
申请日：2009-09-30
申请人： Kerry Bernstein , Moinuddin K. Qureshi
发明人： Kerry Bernstein , Moinuddin K. Qureshi
IPC分类号： G06F13/00 , G06F12/00
CPC分类号： G06F12/0886 , G06F12/0864 , G06F2212/1016 , G06F2212/502
摘要： A mechanism is provided in a cache for emulating larger linesize in a substrate with smaller linesize using gang fetching and gang replacement. Gang fetching fetches multiple lines on a cache miss to ensure that all smaller lines that make up the larger line are resident in cache at the same time. Gang replacement evicts all smaller lines in cache that would have been evicted had the cache linesize been larger. The mechanism provides adaptive linesize using set dueling by dynamically selecting between multiple linsizes depending on which linesize performs the best at runtime. Set dueling dedicates a portion of sets of the cache to always use smaller linesize and dedicates one or more portions of the sets of cache to always emulate larger linesizes. One or more counters keep track of which linesize has the best performance. The cache uses that linesize for the remainder of the sets.
摘要翻译：在缓存中提供了一种机制，用于在使用帮派取出和帮派替换的较小线条模拟衬底中较大的线条化。 Gang提取在高速缓存未命中获取多行，以确保组成较大行的所有较小行同时驻留在缓存中。如果缓存线条化较大，Gang替换会将缓存中的所有较小的行排除在被驱逐之后。该机制通过根据哪些linesize在运行时执行最好的多个linsizes之间的动态选择，提供使用集合决策的自适应线性化。设置决斗专用于缓存的一部分，以始终使用较小的线条化，并且专用于高速缓存集中的一个或多个部分来始终模拟较大的线条。一个或多个计数器跟踪哪些linesize具有最佳性能。缓存使用其余集合的linesize。

3. 发明授权

US08417917B2 Processor core stacking for efficient collaboration 有权
标题翻译：处理器核心堆叠进行高效协作
公开(公告)号：US08417917B2
公开(公告)日：2013-04-09
申请号：US12570351
申请日：2009-09-30
申请人： Philip G. Emma , Eren Kursun , Moinuddin K. Qureshi , Vijayalakshmi Srinivasan
发明人： Philip G. Emma , Eren Kursun , Moinuddin K. Qureshi , Vijayalakshmi Srinivasan
IPC分类号： G06F9/00
CPC分类号： G06F9/3836 , G06F9/3838 , G06F9/3851 , G06F9/3857 , G06F9/3885 , G06F9/3889
摘要： A mechanism is provided for improving the performance and efficiency of multi-core processors. A system controller in a data processing system determines an operational function for each primary processor core in a set of primary processor cores in a primary processor core logic layer and for each secondary processor core in a set of secondary processor cores in a secondary processor core logic layer, thereby forming a set of determined operational functions. The system controller then generates an initial configuration, based on the set of determined operational functions, for initializing the set of primary processor cores and the set of secondary processor cores in the three-dimensional processor core architecture. The initial configuration indicates how at least one primary processor core of the set of primary processor cores collaborate with at least one secondary processor core of the set of secondary processor cores.
摘要翻译：提供了一种提高多核处理器性能和效率的机制。数据处理系统中的系统控制器确定主处理器核心逻辑层中的一组主处理器核心中的每个主处理器核心的操作功能，以及辅助处理器核心逻辑中的一组次要处理器核心中的每个辅助处理器核心从而形成一组确定的操作功能。系统控制器然后基于所确定的操作功能的集合生成用于初始化三维处理器核心体系结构中的主处理器核心集合和次要处理器核心组的初始配置。初始配置指示主处理器核心组中的至少一个主处理器核与第二处理器核集合中的至少一个辅助处理器核协作。

4. 发明申请

US20140195996A1 ADAPTIVE WORKLOAD BASED OPTIMIZATIONS COUPLED WITH A HETEROGENEOUS CURRENT-AWARE BASELINE DESIGN TO MITIGATE CURRENT DELIVERY LIMITATIONS IN INTEGRATED CIRCUITS 有权
标题翻译：基于自适应工作负载的优化与异构电流基准设计相结合，以减轻集成电路中的电流传输限制
公开(公告)号：US20140195996A1
公开(公告)日：2014-07-10
申请号：US13526252
申请日：2012-06-18
申请人： Pradip Bose , Alper Buyuktosunoglu , John A. Darringer , Moinuddin K. Qureshi , Jeonghee Shin
发明人： Pradip Bose , Alper Buyuktosunoglu , John A. Darringer , Moinuddin K. Qureshi , Jeonghee Shin
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5036
摘要： A dynamic system coupled with “pre-Silicon” design methodologies and “post-Silicon” current optimizing programming methodologies to improve and optimize current delivery into a chip, which is limited by the physical properties of the connections (e.g., Controlled Collapse Chip Connection or C4s). The mechanism consists of measuring or estimating power consumption at a certain granularity within a chip, converting the power information into C4 current information using a method, and triggering throttling mechanisms (including token based throttling) where applicable to limit the current delivery per C4 beyond pre-established limits or periods. Design aids are used to allocate C4s throughout the chip based on the current delivery requirements. The system coupled with design and programming methodologies improve and optimize current delivery is extendable to connections across layers in a multilayer 3D chip stack.
摘要翻译：与“前置硅”设计方法和“后硅”当前优化编程方法相结合的动态系统，以改进和优化当前传输到芯片的传输，这受到连接的物理特性的限制（例如，受控崩溃芯片连接或 C4s）。该机制包括测量或估计芯片内特定粒度的功耗，使用一种方法将功率信息转换为C4当前信息，并在适用的情况下触发限流机制（包括基于令牌的限制），以限制每个C4超过预先的当前传输 - 建立的限制或期限。设计辅助工具用于根据当前交付要求在整个芯片上分配C4。该系统与设计和编程方法相结合，改进并优化电流传递可扩展到多层3D芯片堆叠中的层间连接。

5. 发明申请

US20140082574A1 Token-Based Current Control to Mitigate Current Delivery Limitations in Integrated Circuits 有权
标题翻译：基于令牌的电流控制，以缓解集成电路中的当前传输限制
公开(公告)号：US20140082574A1
公开(公告)日：2014-03-20
申请号：US13526153
申请日：2012-06-18
申请人： Pradip Bose , Alper Buyuktosunoglu , John A. Darringer , Moinuddin K. Qureshi , Jeonghee Shin
发明人： Pradip Bose , Alper Buyuktosunoglu , John A. Darringer , Moinuddin K. Qureshi , Jeonghee Shin
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F9/455 , G06F9/46 , G06F9/5044 , G06F15/177 , G06F17/5022 , G06F17/5045 , G06F2212/1041 , G06F2217/78
摘要： A dynamic system coupled with “pre-Silicon” design methodologies and “post-Silicon” current optimizing programming methodologies to improve and optimize current delivery into a chip, which is limited by the physical properties of the connections (e.g., Controlled Collapse Chip Connection or C4s). The mechanism consists of measuring or estimating power consumption at a certain granularity within a chip, converting the power information into C4 current information using a method, and triggering throttling mechanisms (including token based throttling) where applicable to limit the current delivery per C4 beyond pre-established limits or periods. Design aids are used to allocate C4s throughout the chip based on the current delivery requirements. The system coupled with design and programming methodologies improve and optimize current delivery is extendable to connections across layers in a multilayer 3D chip stack.
摘要翻译：与“前置硅”设计方法和“后硅”当前优化编程方法相结合的动态系统，以改进和优化当前传输到芯片的传输，这受到连接的物理特性的限制（例如，受控崩溃芯片连接或 C4s）。该机制包括测量或估计芯片内特定粒度的功耗，使用一种方法将功率信息转换为C4当前信息，并在适用的情况下触发限流机制（包括基于令牌的限制），以限制每个C4超过预先的当前传输 - 建立的限制或期限。设计辅助工具用于根据当前交付要求在整个芯片上分配C4。该系统与设计和编程方法相结合，改进并优化电流传递可扩展到多层3D芯片堆叠中的层间连接。

6. 发明申请

US20120311262A1 MEMORY CELL PRESETTING FOR IMPROVED MEMORY PERFORMANCE 审中-公开
标题翻译：用于改善记忆性能的存储单元预置
公开(公告)号：US20120311262A1
公开(公告)日：2012-12-06
申请号：US13151043
申请日：2011-06-01
申请人： Michele M. Franceschini , Ashish Jagmohan , John P. Karidis , Luis A. Lastras-Montano , Moinuddin K. Qureshi
发明人： Michele M. Franceschini , Ashish Jagmohan , John P. Karidis , Luis A. Lastras-Montano , Moinuddin K. Qureshi
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/00 , G06F12/08 , G06F12/0802 , G06F12/0891
摘要： Memory cell presetting for improved performance including a system that includes a memory, a cache, and a memory controller. The memory includes memory lines made up of memory cells. The cache includes cache lines that correspond to a subset of the memory lines. The memory controller is in communication with the memory and the cache. The memory controller is configured to perform a method that includes scheduling a request to set memory cells of a memory line to a common specified state in response to a cache line attaining a dirty state.
摘要翻译：用于改进性能的存储单元预置，包括包括存储器，高速缓存和存储器控制器的系统。存储器包括由存储单元组成的存储器线。缓存包括对应于存储器线的子集的高速缓存行。存储器控制器与存储器和缓存器通信。存储器控制器被配置为执行一种方法，该方法包括根据达到肮脏状态的高速缓存线来调度将存储器线的存储单元设置为公共指定状态的请求。

7. 发明申请

US20110026318A1 ITERATIVE WRITE PAUSING TECHNIQUES TO IMPROVE READ LATENCY OF MEMORY SYSTEMS 有权
标题翻译：迭代写暂停技术来改善读取存储器系统的延迟
公开(公告)号：US20110026318A1
公开(公告)日：2011-02-03
申请号：US12533548
申请日：2009-07-31
申请人： Michele M. Franceschini , Luis A. Lastras-Montano , Moinuddin K. Qureshi , Vijayalakshmi Srinivasan
发明人： Michele M. Franceschini , Luis A. Lastras-Montano , Moinuddin K. Qureshi , Vijayalakshmi Srinivasan
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G06F13/1642 , G06F13/161
摘要： Iterative write pausing techniques to improve read latency of memory systems including memory systems with phase change memory (PCM) devices. A PCM device includes a plurality of memory locations and a mechanism for executing an iterative write to one or more of the memory locations in response to receiving a write command that includes data to be written. The executing includes initiating the iterative write, updating a state of the iterative write, pausing the iterative write including saving the state in response to receiving a pause command, and resuming the iterative write in response to receiving a resume command. The resuming is responsive to the saved state and to the data to be written.
摘要翻译：迭代写暂停技术，以提高内存系统（包括具有相变存储器（PCM）设备的存储器系统）的读取延迟。 PCM设备包括多个存储器位置和用于响应于接收到包括要写入的数据的写入命令而执行对一个或多个存储器位置的迭代写入的机制。执行包括启动迭代写入，更新迭代写入的状态，暂停迭代写入，包括响应于接收到暂停命令而保存状态，以及响应于接收到恢复命令恢复迭代写入。恢复响应于保存的状态和要写入的数据。

8. 发明申请

US20090006742A1 Method and apparatus improving performance of a digital memory array device 审中-公开
标题翻译：提高数字存储器阵列器件性能的方法和装置
公开(公告)号：US20090006742A1
公开(公告)日：2009-01-01
申请号：US11823358
申请日：2007-06-27
申请人： Min Huang , Chris Wilkerson , Nam Sung Kim , Moinuddin K. Qureshi
发明人： Min Huang , Chris Wilkerson , Nam Sung Kim , Moinuddin K. Qureshi
IPC分类号： G06F12/00
CPC分类号： G06F12/0893 , G06F2212/1032 , G11C7/1006 , G11C11/413
摘要： A method for improving performance of a digital memory array device including a plurality of memory cells; each respective memory cell storing a first digital value and a second digital value being an inverse of the first digital value; storing of the first and second digital values being controlled by a first digital signal effecting selection of a specified memory cell for storing; includes: (a) determining an extant value relating to the first digital signal; (b) if the extant value has a first value, effecting a bit flip operation in the specified memory cell to invert values of at least one of the stored first digital and the second digital values; (c) if the extant value does not have the first value, foregoing the bit flip operation in the specified memory cell.
摘要翻译：一种用于提高包括多个存储单元的数字存储器阵列器件的性能的方法; 每个相应的存储单元存储第一数字值，而第二数字值是第一数字值的倒数; 第一数字值和第二数字值的存储由第一数字信号控制，第一数字信号执行用于存储的指定存储单元的选择; 包括：（a）确定与第一数字信号相关的现有值; （b）如果现有值具有第一值，则在指定的存储器单元中进行位翻转操作以反转所存储的第一数字和第二数字值中的至少一个的值; （c）如果现存值不具有第一值，则前述指定存储单元中的位翻转操作。

9. 发明授权

US08848471B2 Method for optimizing refresh rate for DRAM 有权
标题翻译：优化DRAM刷新率的方法
公开(公告)号：US08848471B2
公开(公告)日：2014-09-30
申请号：US13569486
申请日：2012-08-08
申请人： Michele M. Franceschini , Hillery C. Hunter , Ashish Jagmohan , Charles A. Kilmer , Kyu-hyoun Kim , Luis A. Lastras , Moinuddin K. Qureshi
发明人： Michele M. Franceschini , Hillery C. Hunter , Ashish Jagmohan , Charles A. Kilmer , Kyu-hyoun Kim , Luis A. Lastras , Moinuddin K. Qureshi
IPC分类号： G11C29/00 , G11C29/50
CPC分类号： G11C29/50 , G11C11/406 , G11C29/023 , G11C29/028 , G11C29/50016
摘要： A method for determining an optimized refresh rate involves testing a refresh rate on rows of cells, determining an error rate of the rows, evaluating the error rate of the rows; and repeating these steps for a decreased refresh rate until the error rate is greater than a constraint, at which point a slow refresh rate is set.
摘要翻译：用于确定优化的刷新速率的方法涉及测试单元行的刷新率，确定行的错误率，评估行的错误率; 并重复这些步骤以减少刷新率，直到错误率大于约束，此时设置较慢的刷新率。

10. 发明申请

US20130339762A1 ADAPTIVE WORKLOAD BASED OPTIMIZATIONS TO MITIGATE CURRENT DELIVERY LIMITATIONS IN INTEGRATED CIRCUITS 有权
标题翻译：基于自适应工作负载的优化，以减轻集成电路中的当前交付限制
公开(公告)号：US20130339762A1
公开(公告)日：2013-12-19
申请号：US13526230
申请日：2012-06-18
申请人： Pradip Bose , Alper Buyuktosunoglu , John A. Darringer , Moinuddin K. Qureshi , Jeonghee Shin
发明人： Pradip Bose , Alper Buyuktosunoglu , John A. Darringer , Moinuddin K. Qureshi , Jeonghee Shin
IPC分类号： G06F1/26 , G06F9/46 , H03K3/00
CPC分类号： H01L23/00 , G06F11/00 , G06F11/3062 , H01L23/50 , H01L25/065 , H01L2224/16145 , H01L2224/16225
摘要： A dynamic system coupled with “pre-Silicon” design methodologies and “post-Silicon” current optimizing programming methodologies to improve and optimize current delivery into a chip, which is limited by the physical properties of the connections (e.g., Controlled Collapse Chip Connection or C4s). The mechanism consists of measuring or estimating power consumption at a certain granularity within a chip, converting the power information into C4 current information using a method, and triggering throttling mechanisms (including token based throttling) where applicable to limit the current delivery per C4 beyond pre-established limits or periods. Design aids are used to allocate C4s throughout the chip based on the current delivery requirements. The system coupled with design and programming methodologies improve and optimize current delivery is extendable to connections across layers in a multilayer 3D chip stack.
摘要翻译：与“前置硅”设计方法和“后硅”当前优化编程方法相结合的动态系统，以改进和优化当前传输到芯片的传输，这受到连接的物理特性的限制（例如，受控崩溃芯片连接或 C4s）。该机制包括测量或估计芯片内特定粒度的功耗，使用一种方法将功率信息转换为C4当前信息，并在适用的情况下触发节流机制（包括基于令牌的节流），以限制每个C4的当前传输超过预先 - 建立的限制或期限。设计辅助工具用于根据当前交付要求在整个芯片上分配C4。该系统与设计和编程方法相结合，改进并优化电流传递可扩展到多层3D芯片堆叠中的层间连接。

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