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1. 发明授权

US06509725B1 Self-regulating voltage divider for series-stacked voltage rails 失效
标题翻译：用于串联堆叠电压轨的自调节分压器
公开(公告)号：US06509725B1
公开(公告)日：2003-01-21
申请号：US09683025
申请日：2001-11-09
申请人： Kerry Bernstein , Peter Edwin Cottrell , Roger Paul Gregor , Stephen V. Kosonocky , Edward Joseph Nowak
发明人： Kerry Bernstein , Peter Edwin Cottrell , Roger Paul Gregor , Stephen V. Kosonocky , Edward Joseph Nowak
IPC分类号： G05F304
CPC分类号： G06F1/26
摘要： A system and method for achieving self-regulated voltage division among multiple serially stacked voltage planes. The system of the present invention is incorporated within a source voltage plane having a source supply node for supplying current and a source ground node for sinking current supplied therefrom. An intermediate voltage supply node is coupled between the source supply voltage node and the source ground node for dividing the source voltage plane into a plurality of intermediate voltage planes. The self-regulated voltage divider of the present invention includes a first capacitor and a second capacitor that are each controllably coupled between either the source supply voltage node and the intermediate voltage supply node, or between the intermediate voltage supply node and the source ground node, such that a voltage level balance is achieved among the intermediate voltage planes.
摘要翻译：一种用于在多个串联电压平面之间实现自调节电压分配的系统和方法。本发明的系统结合在具有用于提供电流的源电源节点的源极电压平面和用于吸收从其提供的电流的源极接地节点。中间电压供应节点耦合在源电源电压节点和源极接地节点之间，用于将源极电压平面分成多个中间电压平面。本发明的自调节分压器包括第一电容器和第二电容器，每个可控制地耦合在源电源电压节点和中间电压供应节点之间，或者在中间电压供应节点和源极接地节点之间，使得在中间电压平面之间实现电压电平平衡。

2. 发明授权

US08053819B2 Three-dimensional cascaded power distribution in a semiconductor device 有权
标题翻译：半导体器件中的三维级联功率分布
公开(公告)号：US08053819B2
公开(公告)日：2011-11-08
申请号：US12120899
申请日：2008-05-15
申请人： Kerry Bernstein , Paul W. Coteus , Philip George Emma , Allan Mark Hartstein , Stephen V. Kosonocky , Ruchir Puri , Mark B. Ritter
发明人： Kerry Bernstein , Paul W. Coteus , Philip George Emma , Allan Mark Hartstein , Stephen V. Kosonocky , Ruchir Puri , Mark B. Ritter
IPC分类号： H01L29/80
CPC分类号： G11C5/063 , G11C5/14 , H01L21/8221 , H01L27/0688 , H03H1/0007
摘要： An IC structure having reduced power loss and/or noise includes two or more active semiconductor regions stacked in a substantially vertical dimension, each active semiconductor region including an active layer. The IC structure further includes two or more voltage supply planes, each of the voltage supply planes corresponding to a respective one of the active layers.
摘要翻译：具有降低的功率损耗和/或噪声的IC结构包括以基本上垂直的尺寸堆叠的两个或更多个有源半导体区域，每个有源半导体区域包括有源层。 IC结构还包括两个或更多个电压供应平面，每个电压供应平面对应于相应的一个有源层。

3. 发明申请

US20080023731A1 Three-dimensional cascaded power distribution in a semiconductor device 有权
标题翻译：半导体器件中的三维级联功率分布
公开(公告)号：US20080023731A1
公开(公告)日：2008-01-31
申请号：US11496120
申请日：2006-07-31
申请人： Kerry Bernstein , Paul W. Coteus , Philip George Emma , Allan Mark Hartstein , Stephen V. Kosonocky , Ruchir Puri , Mark B. Ritter
发明人： Kerry Bernstein , Paul W. Coteus , Philip George Emma , Allan Mark Hartstein , Stephen V. Kosonocky , Ruchir Puri , Mark B. Ritter
IPC分类号： H01L29/80
CPC分类号： G11C5/063 , G11C5/14 , H01L21/8221 , H01L27/0688 , H03H1/0007
摘要： An IC structure having reduced power loss and/or noise includes two or more active semiconductor regions stacked in a substantially vertical dimension, each active semiconductor region including an active layer. The IC structure further includes two or more voltage supply planes, each of the voltage supply planes corresponding to a respective one of the active layers.
摘要翻译：具有降低的功率损耗和/或噪声的IC结构包括以基本上垂直的尺寸堆叠的两个或更多个有源半导体区域，每个有源半导体区域包括有源层。 IC结构还包括两个或更多个电压供应平面，每个电压供应平面对应于相应的一个有源层。

4. 发明授权

US06917221B2 Method and apparatus for enhancing the soft error rate immunity of dynamic logic circuits 失效
标题翻译：提高动态逻辑电路的软错误率抗扰度的方法和装置
公开(公告)号：US06917221B2
公开(公告)日：2005-07-12
申请号：US10249642
申请日：2003-04-28
申请人： Kerry Bernstein , Stephen V. Kosonocky , Randy W. Mann , Jeffrey H. Oppold
发明人： Kerry Bernstein , Stephen V. Kosonocky , Randy W. Mann , Jeffrey H. Oppold
IPC分类号： G06F11/00 , H03K19/017 , H03K19/094
CPC分类号： H03K19/01728
摘要： An apparatus and method for selectively enhancing the soft error rate (SER) immunity of a dynamic logic circuit. The apparatus includes a bootstrap capacitor coupled to a precharge input signal and a dynamic node of the dynamic logic circuit, and a device, such as an FET, for selectively connecting the bootstrap capacitor to the dynamic node.
摘要翻译：一种用于选择性地增强动态逻辑电路的软错误率（SER）抗扰度的装置和方法。该装置包括耦合到预充电输入信号和动态逻辑电路的动态节点的自举电容器，以及用于选择性地将自举电容器连接到动态节点的诸如FET的装置。

5. 发明申请

US20080203445A1 Three-Dimensional Cascaded Power Distribution in a Semiconductor Device 有权
标题翻译：半导体器件中的三维级联配电
公开(公告)号：US20080203445A1
公开(公告)日：2008-08-28
申请号：US12120899
申请日：2008-05-15
申请人： Kerry Bernstein , Paul W. Coteus , Philip George Emma , Allan Mark Hartstein , Stephen V. Kosonocky , Ruchir Puri , Mark B. Ritter
发明人： Kerry Bernstein , Paul W. Coteus , Philip George Emma , Allan Mark Hartstein , Stephen V. Kosonocky , Ruchir Puri , Mark B. Ritter
IPC分类号： H01L29/80
CPC分类号： G11C5/063 , G11C5/14 , H01L21/8221 , H01L27/0688 , H03H1/0007
摘要： An IC structure having reduced power loss and/or noise includes two or more active semiconductor regions stacked in a substantially vertical dimension, each active semiconductor region including an active layer. The IC structure further includes two or more voltage supply planes, each of the voltage supply planes corresponding to a respective one of the active layers.
摘要翻译：具有降低的功率损耗和/或噪声的IC结构包括以基本上垂直的尺寸堆叠的两个或更多个有源半导体区域，每个有源半导体区域包括有源层。 IC结构还包括两个或更多个电压供应平面，每个电压供应平面对应于相应的一个有源层。

6. 发明授权

US07402854B2 Three-dimensional cascaded power distribution in a semiconductor device 有权
公开(公告)号：US07402854B2
公开(公告)日：2008-07-22
申请号：US11496120
申请日：2006-07-31
申请人： Kerry Bernstein , Paul W. Coteus , Philip George Emma , Allan Mark Hartstein , Stephen V. Kosonocky , Ruchir Puri , Mark B. Ritter
发明人： Kerry Bernstein , Paul W. Coteus , Philip George Emma , Allan Mark Hartstein , Stephen V. Kosonocky , Ruchir Puri , Mark B. Ritter
IPC分类号： H01L29/80
CPC分类号： G11C5/063 , G11C5/14 , H01L21/8221 , H01L27/0688 , H03H1/0007
摘要： An IC structure having reduced power loss and/or noise includes two or more active semiconductor regions stacked in a substantially vertical dimension, each active semiconductor region including an active layer. The IC structure further includes two or more voltage supply planes, each of the voltage supply planes corresponding to a respective one of the active layers.

7. 发明授权

US06580293B1 Body-contacted and double gate-contacted differential logic circuit and method of operation 有权
标题翻译：身体接触和双门接触差分逻辑电路及其操作方法
公开(公告)号：US06580293B1
公开(公告)日：2003-06-17
申请号：US09683325
申请日：2001-12-14
申请人： Kerry Bernstein , Peter E. Cottrell , Stephen V. Kosonocky , David Meltzer , Edward J. Nowak , Kevin J. Nowka , Norman J. Rohrer
发明人： Kerry Bernstein , Peter E. Cottrell , Stephen V. Kosonocky , David Meltzer , Edward J. Nowak , Kevin J. Nowka , Norman J. Rohrer
IPC分类号： H03K19096
CPC分类号： H03K19/1737 , H03K3/356113 , H03K19/0963
摘要： A differential logic circuit (20, 120, 220, 320, 420 and 520) designed to ensure stability of the output of the circuit. The logic circuit includes a differential load structure (22, 122, 222, 322, 422) that is connected to evaluate transistors (50, 52, 54, 56). In several embodiments, the outputs of the load transistors (30, 32) in the differential load structure are connected to the bodies of the evaluate transistors. In the other embodiments, the outputs of the load transistors in the differential structure are connected to one of the gates of a double-gated evaluate transistors. Level-shifting output buffers (160, 178) are used in connection with the embodiments of the invention that do not include double-gated evaluate transistors.
摘要翻译：设计用于确保电路输出的稳定性的差分逻辑电路（20,120,220,320,420和520）。逻辑电路包括被连接以评估晶体管（50,52,54,56）的差分负载结构（22,122,222,322,422）。在几个实施例中，差分负载结构中的负载晶体管（30,32）的输出连接到评估晶体管的主体。在其他实施例中，差分结构中的负载晶体管的输出连接到双门控评估晶体管的栅极之一。结合本发明的不包括双门控评估晶体管的实施例，使用电平移位输出缓冲器（160,178）。

8. 发明授权

US08587288B2 Digital interface for fast, inline, statistical characterization of process, MOS device and circuit variations 有权
标题翻译：数字接口，用于快速，在线，统计表征过程，MOS器件和电路变化
公开(公告)号：US08587288B2
公开(公告)日：2013-11-19
申请号：US12823984
申请日：2010-06-25
申请人： Azeez Jennudin Bhavnagarwala , Stephen V. Kosonocky , Carl John Radens , Kevin Geoffrey Stawiasz
发明人： Azeez Jennudin Bhavnagarwala , Stephen V. Kosonocky , Carl John Radens , Kevin Geoffrey Stawiasz
IPC分类号： G01R31/3187
CPC分类号： G01R31/3004
摘要： A Circuit architecture and a method for rapid and accurate statistical characterization of the variations in the electrical characteristics of CMOS process structures, MOS devices and Circuit parameters is provided. The proposed circuit architecture and method enables a statistical characterization throughput of
摘要翻译：提供了一种用于快速准确地统计表征CMOS工艺结构，MOS器件和电路参数的电气特性变化的电路架构和方法。所提出的电路架构和方法使得在<2mV或<1nA分辨率的测试设备的电压或电流变化的分辨率精度下<1ms / DC扫描的统计特征吞吐量。提出的电路架构的显着特征包括一个可激励被测器件的可编程斜坡电压发生器，一个双输入9-11位循环ADC，用于捕获输入和输出来自被测器件的直流电压/电流信号，一个2 Kb的锁存器存储器，以可编程粒度的直流扫描为每个测量点捕获9-11位流，以及时钟和控制方案，其能够连续测量和流出数字数据块，从该模块重新测量被测器件的模拟特性。

9. 发明授权

US08561004B2 Ring power gating with distributed currents using non-linear contact placements 有权
标题翻译：使用非线性触点放置的分布电流的环形电源门控
公开(公告)号：US08561004B2
公开(公告)日：2013-10-15
申请号：US12758525
申请日：2010-04-12
申请人： Stephen V. Kosonocky
发明人： Stephen V. Kosonocky
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： H01L27/0207 , H01L23/5286 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A power gate includes a series of electrical contacts along at least a portion of an integrated circuit and a series of power gate transistors electrically coupled to the electrical contacts on the integrated circuit to form a power gate boundary, e.g., at the integrated circuit periphery. The electrical contacts along at least a portion of a running length of the power gate boundary define a substantially non-linear profile. The non-linear profile provides increased contact density which improves current balancing across the electrical contacts and current throughput through the power gate. The non-linear profile is a sinusoidal or zigzag pattern with intermediate offset bump contacts. The contact profiles along the power gate boundary can include both linear and non-linear profiles.
摘要翻译：功率门包括沿着集成电路的至少一部分的一系列电触点和电耦合到集成电路上的电触点的一系列功率栅极晶体管，以形成例如集成电路外围的功率门边界。沿着电源栅极边界的运行长度的至少一部分的电触点限定了基本上非线性的轮廓。非线性轮廓提供增加的接触密度，其改善电触头之间的电流平衡和通过功率门的电流吞吐量。非线性轮廓是具有中间偏移碰撞触点的正弦曲线或锯齿形图案。沿着功率门边界的接触曲线可以包括线性和非线性轮廓。

10. 发明申请

US20120126847A1 POWER SUPPLY MONITOR 有权
标题翻译：电源监控
公开(公告)号：US20120126847A1
公开(公告)日：2012-05-24
申请号：US12950584
申请日：2010-11-19
申请人： Stephen V. Kosonocky , Gregory K. Chen
发明人： Stephen V. Kosonocky , Gregory K. Chen
IPC分类号： G01R31/40
CPC分类号： G01R31/40
摘要： Power supply variations and jitter are measured by monitoring the performance of a ring oscillator on a cycle-by-cycle basis. Performance is measured by counting the number of stages of the ring oscillator that are traversed during the clock cycle and mapping the number of stages traversed to a particular voltage level. Counters are used to count the number of ring oscillator revolutions and latches are used to latch the state of the ring oscillator at the end of the cycle. Based on the counters and latches, a monitor output is generated that may also incorporate an adjustment for a reset delay associated with initializing the ring oscillator and counters to a known state.
摘要翻译：通过逐周期监测环形振荡器的性能来测量电源变化和抖动。通过对在时钟周期内遍历的环形振荡器的级数进行计数来测量性能，并将遍历的级数映射到特定的电压电平。计数器用于计数环形振荡器转数，锁存器用于在循环结束时锁存环形振荡器的状态。基于计数器和锁存器，产生监视器输出，其还可以包括与初始化环形振荡器和计数器相关联的复位延迟的调整到已知状态。

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